Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/5/2026 has been entered.
Response to Amendment
The 112 rejections of claims 3 and 5 are hereby withdrawn in view of the claim amendments.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Sakuishi” (US 2017/0092885).
Regarding claim 21, Sakuishi anticipates 21. An apparatus, comprising: a substrate layer having an upper surface and a lower surface (Fig. 1A, [0084]; the substrate 109 has an upper and lower surface. Examiner’s note: in the context of Fig. 1A, the upper surface of the substrate 109 is facing in the downward direction and the lower surface is facing the upward direction);
an integrated circuit (IC) die having a top surface and a bottom surface, the top surface having a top surface area including a target region that is smaller than the top surface area and located at a corner of the top surface area (Figs. 1A, 12A-12I, [0084], [0281]-[0283]; the semiconductor element layer 106 is a semi-conductor element having a top surface and a bottom surface, the top surface of the semiconductor element layer 106 having a top surface area comprising a target region which is the area of the peeling layer 103 that is smaller than the top surface area, it is preferable to form the peeling starting point 117 at the corner portion, see Fig. 12A),
the bottom surface attached to the upper surface of the substrate layer (Fig. 1A, [0084]; the bottom surface of the semiconductor element layer 106 is attached to the upper surface of the substrate 109);
and a debonding film located on the top surface of the IC die and confined to the target region, wherein at least a portion of the debonding film extends to the corner of the top surface area (Figs. 1A, 12A-12I, [0084], [0281]-[0283]; the peeling layer 103 is located on the top surface of the semiconductor element layer 106 and is confined to the target region, and a portion of the peeling layer extends to the corner of the top surface area as it is preferable to form the peeling starting point 117 at the corner portion, see Fig. 12A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuishi in view of “Eid” (US 2021/0407884).
Regarding claim 1, Sakuishi discloses 1. An apparatus, comprising: a substrate layer having an upper surface and a lower surface (Fig. 1A, [0084]; the substrate 109 has an upper and lower surface. Examiner’s note: in the context of Fig. 1A, the upper surface of the substrate 109 is facing in the downward direction and the lower surface is facing the upward direction);
an integrated circuit (IC) die having a top surface and a bottom surface, the top surface having a top surface area comprising a target region that is smaller than the top surface area and located on an edge of the top surface area, the bottom surface attached to the upper surface of the substrate layer (Figs. 1A, 12A-12I, [0084]; the semiconductor element layer 106 is a semi-conductor element having a top surface and a bottom surface which is attached to the upper surface of the substrate 109, the top surface of the semiconductor element layer 106 having a top surface area comprising a target region which is the area of the peeling layer 103 that is smaller than the top surface area and located on an edge of the top surface area);
a debonding film located adjacent to the top surface of the IC die and confined to the target region (Figs. 1A, 12A-12I, [0084]; the peeling layer 103 is adjacent to the top surface of the semiconductor element layer 106 and confined to the target region);
and a heat management component attached to the top surface of the IC die (Figs. 1A, 12G, [0084], [0215]; the substrate 101 is attached to the top surface of the semiconductor element layer 106, and the substrate 101 having at least heat resistance high enough to withstand process temperature in a manufacturing process).
Sakuishi does not disclose the heat management component attached to the top surface of the IC die by an adhesive layer, wherein the adhesive layer overlays at least a portion of the top surface outside the target region and overlays the debonding film in the target region.
Eid discloses a heat management component attached to the top surface of the IC die by an adhesive layer, wherein the adhesive layer overlays at least a portion of the top surface outside the target region and overlays the debonding film in the target region (Fig. 1, [0042], [0044]; the heat dissipation device 150 is attached to the IC 120 via the epoxy layer 170. The epoxy layer 170 covers the entirety of the top surface area of the IC 120, therefore the epoxy layer 170 would overlay at least a portion of the top surface outside the target region and overlays the debonding film in the target region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 3, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not explicitly disclose wherein the target region has an area that is in a range from 0.1% to 5%, inclusive, of the top surface area. However, Sakuishi, Fig. 12G, and [0283], suggests that the area of the peeling layer 103, which is the target region, is substantially smaller than the top surface area. It would have been an obvious matter of design choice, to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s peeling layer 103 as illustrated in Fig. 12G, to have an area that is in a range from 0.1% to 5%, inclusive, of the top surface area since the illustrated proportion of the area of the peeling layer 103 in Fig. 12G to the top surface area is consistent with this claim limitation. Furthermore, Sakuishi, [0281], teaches that the planar shape of the peeling layer 103 used in one particular embodiment is not limited. Therefore, this limitation is not patentable under 103 over Sakuishi in view of Eid.
Regarding claim 4, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
The cited embodiment of Sakuishi does not disclose the target region comprises scalloped edges.
In a different embodiment, Sakuishi discloses the target region comprises scalloped edges (Fig. 12F, [0281]; the peeling starting portion 117 of the peeling layer 103 has scalloped edges).
It would have been an obvious matter of design choice, to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s peeling layer 103 as illustrated in Fig. 12F, to have scalloped edges as, Sakuishi, [0281], teaches that the disclosed planar shapes of the peeling layer 103 provide a force of separating the layer to be peeled and the peeling layer to be concentrated at the peeling starting point 117, which has scalloped edges as shown in Fig. 12F. Therefore, this limitation is not patentable under 103 over Sakuishi in view of Eid.
Regarding claim 5, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi discloses 5. The apparatus of claim 1, wherein the target region includes a leg extending along a top edge of the IC die (Figs. 1A, 12G, [0283], he peeling layer 103 includes a leg extending along a top edge of the semiconductor element layer 106).
Sakuishi does not disclose the leg having a width in a range from 0.1 millimeter to 1 millimeter, inclusive. However, Sakuishi, Fig. 12G, and [0283], suggests that width of the leg of the peeling layer 103 is substantially smaller than the width of the top surface. It would have been an obvious matter of design choice, to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s peeling layer 103 as illustrated in Fig. 12G, to have a width in a range from 0.1 millimeter to 1 millimeter, inclusive, of the top surface width since the illustrated proportion of the width of the peeling layer 103 to the top surface width is consistent with the claim limitation. Furthermore, Sakuishi, [0281], teaches that the planar shape of the peeling layer 103 used in one particular embodiment is not limited. Therefore, this limitation is not patentable under 103 over Sakuishi in view of Eid.
Regarding claim 9, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 9.
Eid discloses 9. The apparatus of claim 1, wherein the IC die is a platform controller die, the apparatus further comprising a processor die attached on the upper surface of the substrate layer (Fig. 1, [0037], [0042], [0044], [0062]; the IC 120 is a controller and includes a processor).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 11, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 11.
Eid discloses 11. The apparatus of claim 1, wherein the substrate layer is a printed circuit board (PCB) (Fig. 1, [0040], [0042], [0044], [0062]; the assembly is attached to a motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 12, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 12.
Eid discloses 12. The apparatus of claim 1, wherein the heat management component comprises a cold plate (Fig. 1, [0042], [0044]; the heat dissipation device 150 is cold plate).
Regarding claim 13, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 13.
Eid discloses 13. The apparatus of claim 1, wherein the heat management component comprises a heat pipe or a vapor chamber (Fig. 1, [0042], [0044]; the heat dissipation device 150 is a heat pipe).
Regarding claim 14, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 14.
Eid discloses 14. The apparatus of claim 1, wherein the IC die comprises a graphics processing unit (GPU) (Fig. 1, [0037]; the IC 120 is a microprocessor for a graphics device).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 15, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 15.
Eid discloses 15. The apparatus of claim 1, further comprising a printed circuit board operationally attached to the lower surface of the substrate layer (Fig. 1, [0040], [0042], [0044], [0062]; the assembly is attached to a motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sakuishi in view of Eid and “Xiao” (US 20240096802).
Regarding claim 6, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 6.
Xiao discloses 6. The apparatus of claim 1, wherein the target region is associated with a location in the IC die having an operational power more than 20% lower than a maximum operational power of the IC die (Figs. 1, 4, [0032]; the electrical current pathway at a location in the IC package 400 reduces power loss by 50%).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus, as modified by Eid, with Xiao’s low operational power more than 20% lower than a maximum operational power of the IC die in order to realize performance improvements by 50%, as suggested by Xiao at [0032].
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuishi in view of Eid and “Cannon” (US 10,696,080).
Regarding claim 7, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 7.
Cannon discloses 7. The apparatus of claim 1, wherein the debonding film comprises polytetrafluoroethylene (Figs. 1-3, col. T, lines 36-44; the debonding agent comprises PTFE).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus, as modified by Eid, with Cannon’s debonding agent in order to provide for a high throughput, high-resolution, low cost, parallel patterning method, as suggested by Cannon at col. 1, lines 25-32.
Regarding claim 8, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 8.
Cannon discloses 8. The apparatus of claim 1, wherein the debonding film comprises one or more of a soap, a grease, a wax, and an oil (Figs. 1-3, col. T, lines 36-44; the debonding agent comprises soap).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus, as modified by Eid, with Cannon’s debonding agent in order to provide for a high throughput, high-resolution, low cost, parallel patterning method, as suggested by Cannon at col. 1, lines 25-32.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sakuishi in view of Eid and “Su” (US 2023/0411174).
Regarding claim 10, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 10.
Su discloses 10. The apparatus of claim 1, further comprising a stiffener component, the stiffener component located on the substrate layer (Fig. 8, [0067]; step 83, a stiffener component is on the substrate).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus, as modified by Eid, with Su’s stiffener component in order to provide for a thermal conduction path to a subsequently-formed heat sink lid/cover, as suggested by Su at [0067].
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuishi in view of Eid and “Edwards” (US 2023/0335928).
Regarding claim 16, Sakuishi in view of Eid discloses the claimed invention as applied to claim 1, above.
Sakuishi does not disclose the limitations of claim 16.
Edwards discloses 16. A device, comprising the apparatus of claim 1, and further comprising: a printed circuit board (PCB) operationally attached to the lower surface of the substrate layer (Figs. 1A, 2B, [0041], [0048]-[0049]; PCB 230);
and a standoff positioned near the target region (Figs. 1A, 2B, [0041], [0048]-[0049]; standoff 278),
wherein the standoff extends from the PCB at a first end to the heat management component at a second end (Figs. 1A, 2B, [0041], [0048]-[0049]; standoff 278 extends to the heat sink 280).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s apparatus, as modified by Eid, with Edward’s device in order to mitigate the effects of the loading at the edges of the contact areas than at the center and results in warpage, as suggested by Edwards at [0003].
Regarding claim 17, Sakuishi in view of Eid and Edwards discloses the claimed invention as applied to claim 16, above.
Sakuishi does not disclose the limitations of claim 17.
Edwards discloses 17. The device of claim 16, further comprising a fastener means to adjustably secure the heat management component to the PCB (Figs. 1A, 2B, [0041], [0048]-[0049]; the load cells 190 adjustably secure the heat management component to the PCB).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Sakuishi.
Regarding claim 22, Sakuishi discloses the claimed invention as applied to claim 21, above.
Sakuishi discloses the debonding film including scalloped edges (Fig. 12F, [0281]; the peeling starting portion 117 of the peeling layer 103 has scalloped edges).
Sakuishi does not explicitly disclose the debonding film has a triangular shape or a triangular shape including scalloped edges.
It would have been an obvious matter of design choice, to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Sakuishi’s peeling layer 103 as illustrated in Figs. 12A-12F, to have a triangular shape or a triangular shape including scalloped edges since Sakuishi, Figs. 12A-12F illustrates several different shapes of the peeling layer 103, and [0281], teaches that the planar shape of the peeling layer 103 used in one particular embodiment is not limited. Therefore, a person of ordinary skill in the art would have predictably constructed the peeling layer to have a triangular shape or a triangular shape including scalloped edges in view of the various and diverse shapes of the peeling layer 103 as illustrated in Figs. 12A-12F and [0281]. In addition, a person of ordinary skill in the art could construe that the peeling starting portion 117 of Sakuishi, Fig. 12B has a triangular shape. Therefore, this limitation is not patentable under 103 over Sakuishi.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STANLEY TSO/ Primary Examiner, Art Unit 2847
Prosecution Insights