Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/14/2025.
Applicant’s arguments regarding claims 16-17 are persuasive and the species restriction of claims 16-17 is hereby withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 3 and 5, the term “about” is a relative term which renders the claim indefinite. The term “about” is not defined by the claim. The specification at [0018] recites: “Terms or values modified by the word “about” include values inclusive of 10% less than the term or value to inclusive of 10% greater than the term or value.”
This description of “about” provides one example that can be construed as being 10% less than or 10% greater than the claimed value. However, this definition does not exclusively limit the values to 10% less than or 10% greater than the claimed value because other values could also be included within the scope of “about.”
Regarding claim 6, the phrase “low power” is a relative term which renders the claim indefinite. The phrase “low power” is not defined by the claim. The specification at [0028] recites: “For this purpose, “low power” may mean more than 20% lower than a maximum operational power of the respective IC die.”
This description of the phrase “low power” provides one example that may be construed as described in paragraph [0028]. However, this definition does not exclusively limit the values to what is described in [0028] because other values could also be included within the scope of the phrase “low power.”
In order to expedite prosecution, the word “about” and the phrase “low power” are construed as how they might be interpreted by a person of ordinary skill in the art.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Kusumoto” (US 2008/0001280).
Regarding claim 1, Kusumoto anticipates 1. An apparatus, comprising: a substrate layer having an upper surface and a lower surface (Figs. 22A, 24A, [0110]; the substrate 101);
an integrated circuit (IC) die having a top surface and a bottom surface, the top surface having an area, the area comprising a target region that is smaller than the area and located on an edge of the area, the bottom surface attached to the upper surface of the substrate layer (Figs. 22A, 24A, [0110]; the integrated circuit 100 has an area on the top surface that is construed as a target region);
and a debonding film located adjacent to the top surface of the IC die and confined to the target region of the area (Figs. 22A, 24A, [0110]; the release film).
Regarding claim 3, Kusumoto anticipates 3. The apparatus of claim 1, wherein the target region is in a range of about 0.1% and about 5% of the area (Figs. 22A, 24A, [0110]; the top surface has a target region. Examiner’s note: see the 112 rejection above for the construction of this limitation.).
Regarding claim 5, Kusumoto anticipates 5. The apparatus of claim 1, wherein the target region includes a leg extending along a top edge of the IC die, the leg having a width between about 0.1 millimeter and about 1 millimeter (Figs. 22A, 24A, [0110]; the target region has a leg. Examiner’s note: see the 112 rejection above for the construction of this limitation.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Eid” (US 2021/0407884).
Regarding claim 2, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 2.
Eid discloses 2. The apparatus of claim 1, further comprising a heat management component attached to the top surface via an adhesive layer (Fig. 1, [0042], [0044]; the heat dissipation device 150 is attached to the IC 120 via the epoxy layer 170).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 9, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 9.
Eid discloses 9. The apparatus of claim 1, wherein the IC die is a platform controller die and further including a processor die attached on the upper surface of the substrate layer (Fig. 1, [0037], [0042], [0044], [0062]; the IC 120 is a controller and includes a processor).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 11, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 11.
Eid discloses 11. The apparatus of claim 1, wherein the substrate layer is a printed circuit board (PCB) (Fig. 1, [0040], [0042], [0044], [0062]; the assembly is attached to a motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 12, Kusumoto in view of Eid discloses the claimed invention as applied to claim 2, above.
Kusumoto does not disclose the limitations of claim 12.
Eid discloses 12. The apparatus of claim 2, wherein the heat management component comprises a cold plate (Fig. 1, [0042], [0044]; the heat dissipation device 150 is cold plate).
Regarding claim 13, Kusumoto in view of Eid discloses the claimed invention as applied to claim 2, above.
Kusumoto does not disclose the limitations of claim 13.
Eid discloses 13. The apparatus of claim 2, wherein the heat management component comprises a heat pipe or a vapor chamber (Fig. 1, [0042], [0044]; the heat dissipation device 150 is a heat pipe).
Regarding claim 14, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 14.
Eid discloses 14. The apparatus of claim 1, wherein the IC die comprises a graphics processing unit (GPU) (Fig. 1, [0037]; the IC 120 is a microprocessor for a graphics device).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Regarding claim 15, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 15.
Eid discloses 15. The apparatus of claim 1, further comprising a printed circuit board operationally attached to the lower surface of the substrate layer (Fig. 1, [0040], [0042], [0044], [0062]; the assembly is attached to a motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Namkung” (US 2015/0077953).
Regarding claim 4, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 4.
Namkung discloses 4. The apparatus of claim 1, wherein the target region comprises scalloped edges (Figs. 7-8, [0043]; the PTFE pattern 157 can may have various other shapes in section).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Namkung’s PTFE pattern 157 with scalloped edges. Although Namkung does not explicitly disclose the scalloped edges, this limitation is obvious since Namkung teaches the pattern may have various other shapes, as suggested by Namkung at [0043]
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Singh” (US 2023/0010934).
Regarding claim 6, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 6.
Singh discloses 6. The apparatus of claim 1, wherein the target region is associated with a low power area in the IC die ([0001]; semiconductor chips have a low power region. Examiner’s note: see the 112 rejection above for the construction of this limitation.).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Singh’s low power region in order to produce competitive electronic devices with several different power regions that vary according to speed and power, as suggested by Singh at [0001].
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Cannon” (US 10,696,080).
Regarding claim 7, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 7.
Cannon discloses 7. The apparatus of claim 1, wherein the debonding film comprises polytetrafluoroethylene (Figs. 1-3, col. T, lines 36-44; the debonding agent comprises PTFE).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Cannon’s debonding agent in order to provide for a high throughput, high-resolution, low cost, parallel patterning method, as suggested by Cannon at col. 1, lines 25-32.
Regarding claim 8, Kusumoto discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 8.
Cannon discloses 8. The apparatus of claim 1, wherein the debonding film comprises one or more of a soap, a grease, a wax, and an oil (Figs. 1-3, col. T, lines 36-44; the debonding agent comprises soap).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Cannon’s debonding agent in order to provide for a high throughput, high-resolution, low cost, parallel patterning method, as suggested by Cannon at col. 1, lines 25-32.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Su” (US 2023/0411174).
Regarding claim 10, Kusumoto in view of Eid discloses the claimed invention as applied to claim 1, above.
Kusumoto does not disclose the limitations of claim 10.
Su discloses 10. The apparatus of claim 1, further comprising a stiffener component, the stiffener component located on the substrate layer (Fig. 8, [0067]; step 83, a stiffener component is on the substrate).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Su’s stiffener component in order to provide for a thermal conduction path to a subsequently-formed heat sink lid/cover, as suggested by Su at [0067].
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of Eid and “Edwards” (US 2023/0335928).
Regarding claim 16, Kusumoto in view of Eid discloses the claimed invention as applied to claim 2, above.
Kusumoto does not disclose the limitations of claim 16.
Edwards discloses 16. A device, comprising the apparatus of claim 2, and further comprising: a printed circuit board (PCB) operationally attached to the lower surface of the substrate layer (Figs. 1A, 2B, [0041], [0048]-[0049]; PCB 230);
a standoff positioned near the target region (Figs. 1A, 2B, [0041], [0048]-[0049]; standoff 278);
and the standoff extends from the PCB at a first end to the heat management component at a second end (Figs. 1A, 2B, [0041], [0048]-[0049]; standoff 278 extends to the heat sink 280).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus, as modified by Eid, with Edward’s device in order to mitigate the effects of the loading at the edges of the contact areas than at the center and results in warpage, as suggested by Edwards at [0003].
Regarding claim 17, Kusumoto in view of Eid and Edwards discloses the claimed invention as applied to claim 16, above.
Kusumoto does not disclose the limitations of claim 17.
Edwards discloses 17. The device of claim 16, further comprising a fastener means to adjustably secure the heat management component to the PCB (Figs. 1A, 2B, [0041], [0048]-[0049]; load cells 190).
Conclusion
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/STANLEY TSO/Primary Examiner, Art Unit 2847