Prosecution Insights
Last updated: May 29, 2026
Application No. 18/188,297

ARCHITECTURES AND METHODS THAT ENABLE A REWORKABLE HEAT MANAGEMENT COMPONENT

Final Rejection §102§103§112
Filed
Mar 22, 2023
Examiner
TSO, STANLEY
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
377 granted / 493 resolved
+8.5% vs TC avg
Strong +34% interview lift
Without
With
+34.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
525
Total Applications
across all art units

Statute-Specific Performance

§103
91.2%
+51.2% vs TC avg
§102
6.1%
-33.9% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 493 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment of claim 6 traverses the 112 rejection of claim 6. As such, the 112 rejection of claim 6 is withdrawn. Response to Arguments On pages 2-3, Applicant alleges that Kusumoto does not disclose “a debonding film located adjacent to the top surface of the IC die and confined to the target region of the area” and “a target region that is smaller than the area and located on an edge of the area” as recited in claim 1. Applicant’s allegations have been fully considered but are not persuasive. Kusumoto, Figs. 22A, 22B and 24A discloses these cited features of claim 1. See, for example, Kusumoto, Fig. 24A, annotated, below. PNG media_image1.png 313 816 media_image1.png Greyscale On page 3, Applicant alleges that Kusumoto does not identify the claimed smaller target region that is located at the edge of a top surface area of an IC die. The Examiner respectfully disagrees because Applicant’s specification does not exclusively define the meaning of the word “edge.” The Merriam-Webster defines the word “edge” can be construed as “the narrow part adjacent to a border.” Kusumoto’s target region is located on a narrow part adjacent to a border. Therefore, claim 1 is anticipated by Kusumoto. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3 and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 3 and 5, the term “substantially” is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim. The specification at [0018] recites: “Terms or values modified by the word “substantially” include arrangements, orientations, spacings, or positions that vary by plus or minus 20% (inclusive) from the meaning of the unmodified term or value.” This description of “substantially” provides one example that can be construed as being 20% less than or 20% greater than the claimed value. However, this definition does not exclusively limit the values to 20% less than or 20% greater than the claimed value. A person having ordinary skill in the art would reasonably interpret paragraph [0018] to mean that the word “substantially” includes, but is not limited to, a variance of plus or minus 20%. Therefore, other values could also be included within the scope of “substantially.” In order to expedite prosecution, the word “substantially” is construed as how they might be interpreted by a person of ordinary skill in the art. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Kusumoto” (US 2008/0001280). Regarding claim 1, Kusumoto anticipates 1. An apparatus, comprising: a substrate layer having an upper surface and a lower surface (Figs. 22A, 24A, [0110]; the substrate 101); an integrated circuit (IC) die having a top surface and a bottom surface, the top surface having an area, the area comprising a target region that is smaller than the area and located on an edge of the area, the bottom surface attached to the upper surface of the substrate layer (Figs. 22A, 24A, [0110]; the integrated circuit 100 has an area on the top surface that is construed as a target region); and a debonding film located adjacent to the top surface of the IC die and confined to the target region of the area (Figs. 22A, 24A, [0110]; the release film). Regarding claim 3, Kusumoto anticipates 3. The apparatus of claim 1, wherein the target region is in a range of substantially 0.1% and substantially 5% of the area (Figs. 22A, 24A, [0110]; the top surface has a target region. Examiner’s note: see the 112 rejection above for the construction of this limitation.). Regarding claim 5, Kusumoto anticipates 5. The apparatus of claim 1, wherein the target region includes a leg extending along a top edge of the IC die, the leg having a width substantially between 0.1 millimeter and 1 millimeter (Figs. 22A, 24A, [0110]; the target region has a leg. Examiner’s note: see the 112 rejection above for the construction of this limitation.). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 2, 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Eid” (US 2021/0407884). Regarding claim 2, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 2. Eid discloses 2. The apparatus of claim 1, further comprising a heat management component attached to the top surface via an adhesive layer (Fig. 1, [0042], [0044]; the heat dissipation device 150 is attached to the IC 120 via the epoxy layer 170). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001]. Regarding claim 9, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 9. Eid discloses 9. The apparatus of claim 1, wherein the IC die is a platform controller die and further including a processor die attached on the upper surface of the substrate layer (Fig. 1, [0037], [0042], [0044], [0062]; the IC 120 is a controller and includes a processor). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001]. Regarding claim 11, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 11. Eid discloses 11. The apparatus of claim 1, wherein the substrate layer is a printed circuit board (PCB) (Fig. 1, [0040], [0042], [0044], [0062]; the assembly is attached to a motherboard). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001]. Regarding claim 12, Kusumoto in view of Eid discloses the claimed invention as applied to claim 2, above. Kusumoto does not disclose the limitations of claim 12. Eid discloses 12. The apparatus of claim 2, wherein the heat management component comprises a cold plate (Fig. 1, [0042], [0044]; the heat dissipation device 150 is cold plate). Regarding claim 13, Kusumoto in view of Eid discloses the claimed invention as applied to claim 2, above. Kusumoto does not disclose the limitations of claim 13. Eid discloses 13. The apparatus of claim 2, wherein the heat management component comprises a heat pipe or a vapor chamber (Fig. 1, [0042], [0044]; the heat dissipation device 150 is a heat pipe). Regarding claim 14, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 14. Eid discloses 14. The apparatus of claim 1, wherein the IC die comprises a graphics processing unit (GPU) (Fig. 1, [0037]; the IC 120 is a microprocessor for a graphics device). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001]. Regarding claim 15, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 15. Eid discloses 15. The apparatus of claim 1, further comprising a printed circuit board operationally attached to the lower surface of the substrate layer (Fig. 1, [0040], [0042], [0044], [0062]; the assembly is attached to a motherboard). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Eid’s heat management component in order to provide for the removal of heat from integrated circuit devices, as suggested by Eid at [0001]. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Namkung” (US 2015/0077953). Regarding claim 4, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 4. Namkung discloses 4. The apparatus of claim 1, wherein the target region comprises scalloped edges (Figs. 7-8, [0043]; the PTFE pattern 157 can may have various other shapes in section). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Namkung’s PTFE pattern 157 with scalloped edges. Although Namkung does not explicitly disclose the scalloped edges, this limitation is obvious since Namkung teaches the pattern may have various other shapes, as suggested by Namkung at [0043] Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Xiao” (US 20240096802). Regarding claim 6, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 6. Xiao discloses 6. The apparatus of claim 1, wherein the target region is associated with a location in the IC die having an operational power more than 20% lower than a maximum operational power of the IC die (Figs. 1, 4, [0032]; the electrical current pathway at a location in the IC package 400 reduces power loss by 50%). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Xiao’s low operational power more than 20% lower than a maximum operational power of the IC die in order to realize performance improvements by 50%, as suggested by Xiao at [0032]. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Cannon” (US 10,696,080). Regarding claim 7, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 7. Cannon discloses 7. The apparatus of claim 1, wherein the debonding film comprises polytetrafluoroethylene (Figs. 1-3, col. T, lines 36-44; the debonding agent comprises PTFE). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Cannon’s debonding agent in order to provide for a high throughput, high-resolution, low cost, parallel patterning method, as suggested by Cannon at col. 1, lines 25-32. Regarding claim 8, Kusumoto discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 8. Cannon discloses 8. The apparatus of claim 1, wherein the debonding film comprises one or more of a soap, a grease, a wax, and an oil (Figs. 1-3, col. T, lines 36-44; the debonding agent comprises soap). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Cannon’s debonding agent in order to provide for a high throughput, high-resolution, low cost, parallel patterning method, as suggested by Cannon at col. 1, lines 25-32. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of “Su” (US 2023/0411174). Regarding claim 10, Kusumoto in view of Eid discloses the claimed invention as applied to claim 1, above. Kusumoto does not disclose the limitations of claim 10. Su discloses 10. The apparatus of claim 1, further comprising a stiffener component, the stiffener component located on the substrate layer (Fig. 8, [0067]; step 83, a stiffener component is on the substrate). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus with Su’s stiffener component in order to provide for a thermal conduction path to a subsequently-formed heat sink lid/cover, as suggested by Su at [0067]. Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto in view of Eid and “Edwards” (US 2023/0335928). Regarding claim 16, Kusumoto in view of Eid discloses the claimed invention as applied to claim 2, above. Kusumoto does not disclose the limitations of claim 16. Edwards discloses 16. A device, comprising the apparatus of claim 2, and further comprising: a printed circuit board (PCB) operationally attached to the lower surface of the substrate layer (Figs. 1A, 2B, [0041], [0048]-[0049]; PCB 230); a standoff positioned near the target region (Figs. 1A, 2B, [0041], [0048]-[0049]; standoff 278); and the standoff extends from the PCB at a first end to the heat management component at a second end (Figs. 1A, 2B, [0041], [0048]-[0049]; standoff 278 extends to the heat sink 280). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Kusumoto’s apparatus, as modified by Eid, with Edward’s device in order to mitigate the effects of the loading at the edges of the contact areas than at the center and results in warpage, as suggested by Edwards at [0003]. Regarding claim 17, Kusumoto in view of Eid and Edwards discloses the claimed invention as applied to claim 16, above. Kusumoto does not disclose the limitations of claim 17. Edwards discloses 17. The device of claim 16, further comprising a fastener means to adjustably secure the heat management component to the PCB (Figs. 1A, 2B, [0041], [0048]-[0049]; load cells 190). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANLEY TSO/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Mar 22, 2023
Application Filed
Dec 18, 2025
Non-Final Rejection mailed — §102, §103, §112
Apr 16, 2026
Response Filed
May 07, 2026
Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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PRINTED CIRCUIT BOARD, BATTERY MODULE, BATTERY PACK, AND ELECTRICAL DEVICE
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+34.0%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 493 resolved cases by this examiner. Grant probability derived from career allowance rate.

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