Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung ( Pub. No. US 20210366919 A1 ), hereinafter Sung.
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Regarding Independent Claim 1 (Original), Sung teaches a non-volatile memory device ( Sung, FIG. 1, 100; FIG. 12, 610; [0025], memory device 100; [0104], nonvolatile memory device 610 ), comprising:
a first semiconductor layer ( Sung, FIG. 3, C; FIG. 5, C, 10; [0046] Referring to FIG. 5, a memory structure C may be stacked on a logic structure P. The memory structure C may include a first substrate 10, and a plurality of electrode layers 20 and a plurality of interlayer dielectric layers 22, which are alternately stacked on the first substrate 10 ) including a plurality of memory cells ( Sung, FIG. 1, 110; [0025], memory cell array 110; FIG.2, MC; [0034], memory cells MC; FIG. 3, C; [0038], memory structure C ) electrically connected to a plurality of bit lines ( Sung, FIG.2, BL; [0033] Referring to FIG. 2, a memory block BLK may include a plurality of cell strings CSTR corresponding to a plurality of bit lines BL and to a common source line CSL ), each of the plurality of bit lines ( Sung, FIG.2, BL ) extending in a first direction ( Sung, [0033], The bit lines BL may extend in a second direction SD ), and a plurality of word lines ( Sung, FIG. 2, WL; [0035], word lines WL; [0027], The row lines RL may include … a plurality of word lines … ) stacked in a vertical direction, each of the plurality of word lines ( Sung, FIG. 2, WL ) extending in a second direction ( Sung, [0031], the first direction FD may correspond to the extending direction of word lines; [0039], a plurality of row lines RL may extend in the first direction FD ), that is different from the first direction, a plurality of word line pads ( Sung, FIG. 5, LP; [0049], pad part LP ) which respectively correspond to the plurality of word lines ( Sung, FIG. 2, WL ) and are arranged in a stair shape ( Sung, [0049], The electrode structure may have a step structure that is configured by the pad parts LP of the electrode layers 20 ), and a plurality of word line contacts ( Sung, FIG. 5, CNT2; [0055], contacts CNT2 pass through the step structure of the electrode structure in the vertical direction VD ) respectively electrically connected ( Sung, [0057], A sidewall conductive layer 50 may be defined on the outer wall of each contact CNT2 to couple the contact CNT2 and the pad part LP of a corresponding electrode layer 20 ) to the plurality of word line pads ( Sung, FIG. 5, LP ); and
a second semiconductor layer ( Sung, FIG. 3, P; FIG. 5, P, 12; [0053], The logic structure P may include a second substrate 12 and a plurality of pass transistors PTR, which are defined on the second substrate 12 ) including a plurality of pass transistors ( Sung, FIG. 5, PTR; [0053] The logic structure P may include a second substrate 12 and a plurality of pass transistors PTR, which are defined on the second substrate 12 ) respectively electrically connected to the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) and respectively overlapping ( Sung, [0053], Each of the pass transistors PTR may overlap with the pad part LP of a corresponding electrode layer 20) the plurality of word line pads ( Sung, FIG. 5, LP ) in the vertical direction,
wherein each of the plurality of word line pads ( Sung, FIG. 5, LP ) has a first width in the first direction and a second width in the second direction ( Sung, [0049], FIG. 5 shows that the pad part LP projects in the first direction FD … the pad part LP may project in the second direction SD; [0101], In order to properly land contacts CNT2, the width of the pad parts LP of the electrode layers 20 should have a minimum predetermined size ), and
wherein each of the plurality of pass transistors ( Sung, FIG. 5, PTR ) has a first pitch in the first direction ( Sung, FIG. 5, direction SD ) and a second pitch in the second direction ( Sung, FIG. 5, direction FD ).
Regarding Claim 2 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein each of the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) has the first pitch in the first direction ( Sung, FIG. 5, direction SD ) and the second pitch in the second direction ( Sung, FIG. 5, direction FD ).
Regarding Claim 3 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein the first width corresponds to the first pitch, and the second width corresponds to the second pitch ( Sung, FIG, 5, [0049], FIG. 5 shows that the pad part LP projects in the first direction FD, but the present invention is not limited thereto. For example, the pad part LP may project in the second direction SD; [0053], Each of the pass transistors PTR may overlap with the pad part LP of a corresponding electrode layer 20; [0101], In order to properly land contacts CNT2, the width of the pad parts LP of the electrode layers 20 should have a minimum predetermined size ).
Regarding Claim 4 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) pass through the plurality of word lines ( Sung, FIG. 2, WL ) in the vertical direction ( Sung, [0055], A plurality of contacts CNT2 pass through the step structure of the electrode structure in the vertical direction VD; [0047], The electrode layers 20 between the source select line SSL and the drain select line DSL may configure word lines WL ), each of the plurality of word lines ( Sung, FIG. 2, WL ) extend in the vertical direction, and are respectively electrically connected to the plurality of pass transistors ( Sung, FIG. 5, PTR ) ( Sung, [0055], Each of the contacts CNT2 may be coupled to a pass transistor PTR through the corresponding lower wiring lines UM1 and the contacts CNT1 ) .
Regarding Claim 5 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) respectively extend ( Sung, [0055], A plurality of contacts CNT2 pass through the step structure of the electrode structure in the vertical direction VD; [0047], The electrode layers 20 between the source select line SSL and the drain select line DSL may configure word lines WL ) in the vertical direction from the plurality of word lines ( Sung, FIG. 2, WL ) and are respectively electrically connected ( Sung, [0055], Each of the contacts CNT2 may be coupled to a pass transistor PTR through the corresponding lower wiring lines UM1 and the contacts CNT1 ) to the plurality of pass transistors ( Sung, FIG. 5, PTR ), and
wherein heights of the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) in the vertical direction differ from one another ( Sung, [0049], The electrode structure may have a step structure that is configured by the pad parts LP of the electrode layers 20; FIG. 5 illustrates that the contacts CNT2 connect to the pad parts LP arranged in the step structure at different vertical levels ).
Regarding Claim 6 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein the plurality of word line pads( Sung, FIG. 5, direction SD ) comprise first and second word line pads adjacent to each other in the first direction,
wherein heights of the first and second word line pads ( Sung, FIG. 5, LP ) differ in the vertical direction ( Sung, [0049], The electrode structure may have a step structure that is configured by the pad parts LP of the electrode layers 20; FIG. 5 illustrates that the pad parts LP arranged in the step structure at different vertical levels ), and
wherein the plurality of pass transistors ( Sung, FIG. 5, PTR ) comprise first and second pass transistors adjacent to each other in the first direction, the first pass transistor is electrically connected to the first word line pads ( Sung, FIG. 5, LP ) through a first word line contacts ( Sung, FIG. 5, CNT2 ), and the second pass transistor is electrically connected to the second word line pads ( Sung, FIG. 5, LP ) through a second word line contacts ( Sung, FIG. 5, CNT2 ).
Regarding Claim 7 (Original), Sung teaches the non-volatile memory device as claimed in claim 6, on which this claim is dependent, Sung further teaches:
wherein the plurality of word line pads ( Sung, FIG. 5, LP ) comprise a third word line pad adjacent to the second word line pad in the second direction ( Sung, FIG. 5, direction FD ), heights of the second and third word line pads word line pads ( Sung, FIG. 5, LP ) differ from one another in the vertical direction ( Sung, [0049], The electrode structure may have a step structure that is configured by the pad parts LP of the electrode layers 20; FIG. 5 illustrates that the pad parts LP arranged in the step structure at different vertical levels ), and
wherein the plurality of pass transistors ( Sung, FIG. 5, PTR ) further comprise a third pass transistor adjacent to the second pass transistor in the second direction ( Sung, FIG. 5, direction FD ), and the third pass transistor is electrically connected to the third word line pads ( Sung, FIG. 5, LP ) through a third word line contact ( Sung, FIG. 5, CNT2 ).
Regarding Claim 8 (Original), Sung teaches the non-volatile memory device as claimed in claim 6, on which this claim is dependent, Sung further teaches:
wherein the first pass transistors ( Sung, FIG. 5, PTR ) comprises a first gate terminal and a first source/drain terminal electrically connected ( Sung, [0055], Each of the contacts CNT2 may be coupled to a pass transistor PTR through the corresponding lower wiring lines UM1 and the contacts CNT1 ) to the first word line contacts ( Sung, FIG. 5, CNT2 ),
wherein the second pass transistors ( Sung, FIG. 5, PTR ) comprises a second gate terminal and a second source/drain terminal electrically connected ( Sung, [0055], Each of the contacts CNT2 may be coupled to a pass transistor PTR through the corresponding lower wiring lines UM1 and the contacts CNT1 ) to the second word line contacts ( Sung, FIG. 5, CNT2 ), and
wherein the first and second source/drain terminals are adjacent to each other ( Sung, FIG. 5, PTR are arranged as a plurality in the coupling region CNR, wherein the sources/drains of two neighboring PTRs are adjacent to each other ) in the first direction.
Regarding Claim 9 (Original), Sung teaches the non-volatile memory device as claimed in claim 6, on which this claim is dependent, Sung further teaches:
wherein the first pass transistor ( Sung, FIG. 5, PTR ) comprises a first gate terminal and a first source/drain terminal electrically connected ( Sung, [0055], Each of the contacts CNT2 may be coupled to a pass transistor PTR through the corresponding lower wiring lines UM1 and the contacts CNT1 ) to the first word line contacts ( Sung, FIG. 5, CNT2 ),
wherein the second pass transistor ( Sung, FIG. 5, PTR ) comprises a second gate terminal and a second source/drain terminal electrically connected ( Sung, [0055], Each of the contacts CNT2 may be coupled to a pass transistor PTR through the corresponding lower wiring lines UM1 and the contacts CNT1 ) to the second word line contacts ( Sung, FIG. 5, CNT2 ), and
wherein the first and second source/drain terminals are not adjacent to each other ( Sung, FIG. 5, PTR are arranged as a plurality in the coupling region CNR, wherein the source/drain of PTR are not adjacent to each other, or separated by the gate ) in the first direction.
Regarding Claim 10 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein the first semiconductor layer ( Sung, FIG. 3, C; FIG. 5, C, 10 ) further comprises a plurality of top bonding pads ( Sung, FIG. 8, PAD1; [0069], first bonding pads PAD1 ) respectively electrically connected to the plurality of word line contacts ( Sung, FIG. 5, CNT2 ),
wherein the second semiconductor layer ( Sung, FIG. 3, P; FIG. 5, P, 12 ) further comprises a plurality of bottom bonding pads ( Sung, FIG. 8, PAD2; [0070], second bonding pads PAD2 ) respectively electrically connected to the plurality of pass transistors ( Sung, FIG. 8, PTR ), and
wherein the plurality of top bonding pads ( Sung, FIG. 8, PAD1; [0069], first bonding pads PAD1 ) and the plurality of bottom bonding pads ( Sung, FIG. 8, PAD2; [0070], second bonding pads PAD2 ) have a same pitch ( Sung, FIG. 8, PAD1, PAD2 ).
Regarding Claim 11 (Original), Sung teaches the non-volatile memory device as claimed in claim 10, on which this claim is dependent, Sung further teaches:
wherein the first semiconductor layer ( Sung, FIG. 3, C; FIG. 5, C, 10; FIG. 8, CW; [0069], cell wafer CW ) further comprises:
at least one top metal layer ( Sung, FIG. 8, IMS1; [0069], first interconnect structure IMS1 ) including a plurality of top metal patterns ( Sung, FIG. 8, [0069], lower wiring lines UM2 ) respectively electrically connected to the plurality of word line contacts ( Sung, FIG. 5, CNT2 ); and
a plurality of top metal contacts ( Sung, FIG. 8, CNT4; [0069], contacts CNT4 ) respectively electrically connected to the plurality of top metal patterns ( Sung, FIG. 8, [0069], lower wiring lines UM2 ),
wherein the second semiconductor layer ( Sung, FIG. 3, P; FIG. 5, P, 12; FIG. 8, PW; [0069], peripheral wafer CW ) further comprises:
a plurality of bottom metal contacts ( Sung, FIG. 8, CNT5; [0070], contacts CNT5 ) respectively electrically connected to the plurality of bottom bonding pads ( Sung, FIG. 8, PAD2 ); and
at least one bottom metal layer ( Sung, FIG. 8, IMS1; [0070], second interconnect structure IMS2 ) including a plurality of bottom metal patterns ( Sung, FIG. 8, UM3; [0070], lower wiring lines UM3 ) respectively electrically connected to the plurality of bottom metal contacts ( Sung, FIG. 8, CNT5; [0070], contacts CNT5 ),
wherein the plurality of word line contacts ( Sung, FIG. 5, CNT2 ), the plurality of top metal patterns ( Sung, FIG. 8, [0069], lower wiring lines UM2 ), and a plurality of metal contacts ( Sung, FIG. 8, CNT4; [0069], contacts CNT4 ) have the same pitch as one another, or the plurality of ( Sung, FIG. 8, CNT5; [0070], contacts CNT5 ), the plurality of bottom metal patterns ( Sung, FIG. 8, [0070], lower wiring lines UM3 ), and the plurality of pass transistors ( Sung, FIG. 8, PTR ) have the same pitch as one another.
Regarding Claim 12 (Original), Sung teaches the non-volatile memory device as claimed in claim 11, on which this claim is dependent, Sung further teaches:
wherein the plurality of top metal contacts ( Sung, FIG. 8, CNT4; [0069], contacts CNT4 ) comprise a plurality of first top metal contacts disposed between a corresponding first top metal pattern of the plurality of top metal patterns ( Sung, FIG. 8, [0069], lower wiring lines UM2 ) and a corresponding first top bonding pad of the plurality of top bonding pads ( Sung, FIG. 8, PAD1 ), or
the plurality of bottom metal contacts ( Sung, FIG. 8, CNT5; [0070], contacts CNT5 ) comprise a plurality of first bottom metal contacts disposed between a corresponding first bottom metal pattern of the plurality of bottom metal patterns ( Sung, FIG. 8, [0070], lower wiring lines UM3 ) and a corresponding first bottom bonding pad of the plurality of bottom bonding pads ( Sung, FIG. 8, PAD2 ).
Regarding Claim 13 (Original), Sung teaches the non-volatile memory device as claimed in claim 10, on which this claim is dependent, Sung further teaches:
wherein the first semiconductor layer ( Sung, FIG. 3, C; FIG. 5, C, 10; FIG. 8, CW; [0069], cell wafer CW ) further comprises a plurality of top metal contacts ( Sung, FIG. 8, CNT4; [0069], contacts CNT4 ) respectively electrically connected to the plurality of word line contacts ( Sung, FIG. 5, CNT2 ),
wherein the second semiconductor layer ( Sung, FIG. 3, P; FIG. 5, P, 12; FIG. 8, PW; [0069], peripheral wafer CW ) further comprises a plurality of bottom metal contacts ( Sung, FIG. 8, CNT5; [0070], contacts CNT5 ) respectively electrically connected to the plurality of bottom bonding pads ( Sung, FIG. 8, PAD2 ), and
wherein the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) and a plurality of metal contacts ( Sung, FIG. 8, CNT4; [0069], contacts CNT4 ) have a same pitch as one another, or the plurality of bottom metal contacts ( Sung, FIG. 8, CNT5; [0070], contacts CNT5 ) and the plurality of pass transistors ( Sung, FIG. 8, PTR ) have a same pitch as one another.
Regarding Claim 14 (Original), Sung teaches the non-volatile memory device as claimed in claim 1, on which this claim is dependent, Sung further teaches:
wherein the plurality of word line contacts ( Sung, FIG. 5, CNT2 ) pass through the plurality of word lines ( Sung, FIG. 2, WL ) in the vertical direction,
wherein the second semiconductor layer ( Sung, FIG. 3, P; FIG. 5, P, 12; FIG. 8, PW; [0069], peripheral wafer CW ) further comprises:
at least one metal layer including a plurality of bottom metal patterns ( Sung, FIG. 5, UM1; [0054], lower wiring lines UM1 ) respectively electrically connected to the plurality of word line contacts ( Sung, FIG. 5, CNT2 ); and
a plurality of bottom metal contacts ( Sung, FIG. 5, CNT1; [0054], Contacts CNT1 ) respectively electrically connected to the plurality of bottom metal patterns ( Sung, FIG. 5, UM1; [0054], lower wiring lines UM1 ),
wherein the plurality of bottom metal patterns ( Sung, FIG. 5, UM1; [0054], lower wiring lines UM1 ), the plurality of bottom metal contacts ( Sung, FIG. 5, CNT1; [0054], Contacts CNT1 ), and the plurality of pass transistors ( Sung, FIG. 5, PTR ) have a same pitch.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817