DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 1/9/2026 is acknowledged.
Applicant amended claims 1 and 9.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/5/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "an opening of the second cavity is located on a vertical side of the side source/drain” (Claim 1, Lines 6-7; and Claim 9, Lines 6-7). It is unclear the term, “the side source/drain”, is “a first source/drain" (Claim 1, Line 2), “a second source/drain” (Claim 1, Line 5), or new source/drain. Claims 2-8 depending from claim 1 and claims 10-18 depending from claim 9 inherit its deficiencies. Examiner interprets “an opening of the second cavity is located on a vertical side of the side source/drain” to mean an opening of the second cavity is located on a vertical side of the second source/drain.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2018/0337176) (hereafter Lee), in view of Lim et al. (US 2021/0036121) (hereafter Lim).
Regarding claim 1, Lee discloses a microelectronic structure comprising:
a first nanosheet transistor (transistor with left 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a first source/drain (left 221 in Fig. 22B, paragraph 0132); and
a second nanosheet transistor (transistor with right 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a second source/drain (right 221 in Fig. 22B, paragraph 0132);
wherein the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) are adjacent to each other, wherein each of the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) have an asymmetrical profile (see Fig. 22B and paragraph 0132, wherein “the second conductivity type S/D structures 221 may have a slightly asymmetric cross section”) when cut through the first (left 221 in Fig. 22B) and second source/drain (right 221 in Fig. 22B).
Lee does not disclose first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; and
wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug.
Lim discloses first source/drain (first 150 from the left corner of Fig. 24, paragraph 0033) includes a first cavity (first H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the first cavity (first H from the left corner in Fig. 23) is located on a vertical side (lateral surface of first 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the first source/drain (first 150 from the left corner of Fig. 23), wherein the first cavity (first H from the left corner in Fig. 23) is filled by a first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117); and
wherein second source/drain (third 150 from the left corner of Fig. 24, paragraph 0033) includes a second cavity (third H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the second cavity (third H from the left corner in Fig. 23) is located on a vertical side (lateral surface of third 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the second source/drain (third 150 from the left corner of Fig. 24), wherein the second cavity (third H from the left corner in Fig. 23) is filled by a second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; and wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug, as taught by Lim, since the contact plug 180 (Lim, Fig. 24, paragraph 0052) may penetrate through the upper insulating layer 195 (Lim, Fig. 24, paragraph 0052), the source/drain regions 150 (Lim, Fig. 24, paragraph 0052), and the lower insulating law 190 (Lim, Fig. 24, paragraph 0052), and may apply an electrical signal to the source/drain region 150 (Lim, Fig. 24, paragraph 0052).
Regarding claim 2, Lee further discloses the microelectronic structure of claim 1, further comprising: a first semiconductor alloy liner (227 contacting 221 in Fig. 22B, paragraph 0126) located on top of the first source/drain (left 221 in Fig. 22B) and on top of the second source/drain (right 221 in Fig. 22B).
Regarding claim 3, Lee further discloses the microelectronic structure of claim 2, further comprising: a second semiconductor alloy liner (227 contacting 220 in Fig. 22B, paragraph 0126) located adjacent a sidewall of the first source/drain (left 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located adjacent to a sidewall of the second source/drain (right 221 in Fig. 22B).
Regarding claim 4, Lee further discloses the microelectronic structure of claim 3, further comprising: a first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) located adjacent to the first source/drain (left 221 in Fig. 22B); a second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) located adjacent to the second source/drain (right 221 in Fig. 22B); wherein each the first and second overlap sections are formed by a portion of the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) overlapping each other.
Regarding claim 5, Lee further discloses the microelectronic structure of claim 4, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), and wherein the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B).
Regarding claim 9, Lee discloses a microelectronic structure comprising:
a first nanosheet transistor (transistor with left 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a first source/drain (left 221 in Fig. 22B, paragraph 0132); and
a second nanosheet transistor (transistor with right 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a second source/drain (right 221 in Fig. 22B, paragraph 0132); and
a first source/drain contact (250 vertically on left 221 in Fig. 22B, paragraph 0128) and a second source/drain contact (250 vertically on right 221 in Fig. 22B, paragraph 0128);
wherein the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) are adjacent to each other, wherein each of the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) have an asymmetrical profile (see Fig. 22B and paragraph 0132, wherein “the second conductivity type S/D structures 221 may have a slightly asymmetric cross section”) when cut through the first (left 221 in Fig. 22B) and second source/drain (right 221 in Fig. 22B), wherein the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) combined have a substantially symmetrical profile when cut through the first (left 221 in Fig. 22B) and second source/drain (right 221 in Fig. 22B).
Lee does not disclose first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; and
wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug.
Lim discloses first source/drain (first 150 from the left corner of Fig. 24, paragraph 0033) includes a first cavity (first H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the first cavity (first H from the left corner in Fig. 23) is located on a vertical side (lateral surface of first 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the first source/drain (first 150 from the left corner of Fig. 23), wherein the first cavity (first H from the left corner in Fig. 23) is filled by a first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117); and
wherein second source/drain (third 150 from the left corner of Fig. 24, paragraph 0033) includes a second cavity (third H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the second cavity (third H from the left corner in Fig. 23) is located on a vertical side (lateral surface of third 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the second source/drain (third 150 from the left corner of Fig. 24), wherein the second cavity (third H from the left corner in Fig. 23) is filled by a second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; and wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug, as taught by Lim, since the contact plug 180 (Lim, Fig. 24, paragraph 0052) may penetrate through the upper insulating layer 195 (Lim, Fig. 24, paragraph 0052), the source/drain regions 150 (Lim, Fig. 24, paragraph 0052), and the lower insulating law 190 (Lim, Fig. 24, paragraph 0052), and may apply an electrical signal to the source/drain region 150 (Lim, Fig. 24, paragraph 0052).
Regarding claim 10, Lee further discloses the microelectronic structure of claim 9, further comprising: a first semiconductor alloy liner (227 contacting 221 in Fig. 22B, paragraph 0126) located on top of the first source/drain (left 221 in Fig. 22B) and on top of the second source/drain (right 221 in Fig. 22B).
Regarding claim 11, Lee further discloses the microelectronic structure of claim 10, wherein the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) is located between the first source/drain contact (250 vertically on left 221 in Fig. 22B) and the first source/drain (left 221 in Fig. 22B), wherein the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) is located between the second source/drain contact (250 vertically on right 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B).
Regarding claim 12, Lee further discloses the microelectronic structure of claim I1, further comprising: a second semiconductor alloy liner (227 contacting 220 in Fig. 22B, paragraph 0126) located adjacent a sidewall of the first source/drain (left 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located adjacent to a sidewall of the second source/drain (right 221 in Fig. 22B).
Regarding claim 13, Lee further discloses the microelectronic structure of claim 12, further comprising: a first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) located adjacent to the first source/drain (left 221 in Fig. 22B); a second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) located adjacent to the second source/drain (right 221 in Fig. 22B); wherein each the first and second overlaps sections are formed by a portion of the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) overlapping each other.
Regarding claim 14, Lee further discloses the microelectronic structure of claim 13, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), and wherein the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B).
Claims 6-8 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Lim as applied to claims 5 and 14 above, and further in view of Suh et al. (US 2017/0365604) (hereafter Suh).
Regarding claim 6, Lee in view of Lim discloses the microelectronic structure of claim 5, however Lee and Lim do not disclose the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and
wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain.
Suh discloses the first metal plug (first 190 from the left corner of Fig. 25B, paragraph 0106) is located adjacent to the second semiconductor alloy liner (first 164B from the left corner of Fig. 25B, paragraph 0106), wherein a portion of second semiconductor alloy liner is located between the first metal plug (first 190 from the left corner of Fig. 25B) and the first source/drain (first 162A from the left corner of Fig. 25B, paragraph 0055); and
wherein the second metal plug (fourth 190 from the left corner of Fig. 25B, paragraph 0106) located adjacent to the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), wherein a portion of second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located between the second metal plug (fourth 190 from the left corner of Fig. 25B) and the second source/drain (first 164A from the left corner of Fig. 25B, paragraph 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Lim to form the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain, as taught by Suh, since a metal silicide layer lowers the contact resistance between a metal plug and a source/drain.
Regarding claim 7, Lee in view of Lim and Suh discloses the microelectronic structure of claim 6, however Lee does not disclose a dielectric pillar located between the first metal plug and the second metal plug.
Lim discloses a dielectric pillar 200a (Fig. 24, paragraph 0036) located between the first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117) and the second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form a dielectric pillar located between the first metal plug and the second metal plug, as taught by Lim, since the isolation structure 200a (Lim, Fig. 24, paragraph 0061) may be disposed between adjacent source/drain regions 150 (Lim, Fig. 24, paragraph 0061) to prevent diffusion of impurities included in the adjacent source/drain regions 150 (Lim, Fig. 24, paragraph 0061).
Regarding claim 8, Lee further discloses the microelectronic structure of claim 7, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 is vertically above a lower portion of leftmost 250 below 227) of the first metal plug (first 250 from the left corner of Fig. 28, paragraph 0148) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 is vertically above a lower portion of rightmost 250 below 227) of the second metal plug (fourth 250 from the left corner of Fig. 28, paragraph 0148).
Regarding claim 15, Lee in view of Lim discloses the microelectronic structure of claim 14, however Lee and Lim do not disclose the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and
wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain.
Suh discloses the first metal plug (first 190 from the left corner of Fig. 25B, paragraph 0106) is located adjacent to the second semiconductor alloy liner (first 164B from the left corner of Fig. 25B, paragraph 0106), wherein a portion of second semiconductor alloy liner is located between the first metal plug (first 190 from the left corner of Fig. 25B) and the first source/drain (first 162A from the left corner of Fig. 25B, paragraph 0055); and
wherein the second metal plug (fourth 190 from the left corner of Fig. 25B, paragraph 0106) located adjacent to the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), wherein a portion of second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located between the second metal plug (fourth 190 from the left corner of Fig. 25B) and the second source/drain (first 164A from the left corner of Fig. 25B, paragraph 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Lim to form the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain, as taught by Suh, since a metal silicide layer lowers the contact resistance between a metal plug and a source/drain.
Regarding claim 16, Lee in view of Lim and Suh discloses the microelectronic structure of claim 15, however Lee does not disclose a dielectric pillar located between the first metal plug and the second metal plug.
Lim discloses a dielectric pillar 200a (Fig. 24, paragraph 0036) located between the first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117) and the second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form a dielectric pillar located between the first metal plug and the second metal plug, as taught by Lim, since the isolation structure 200a (Lim, Fig. 24, paragraph 0061) may be disposed between adjacent source/drain regions 150 (Lim, Fig. 24, paragraph 0061) to prevent diffusion of impurities included in the adjacent source/drain regions 150 (Lim, Fig. 24, paragraph 0061).
Regarding claim 17, Lee further discloses the microelectronic structure of claim 16, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 is vertically above a lower portion of leftmost 250 below 227) of the first metal plug (first 250 from the left corner of Fig. 28, paragraph 0148) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 is vertically above a lower portion of rightmost 250 below 227) of the second metal plug (fourth 250 from the left corner of Fig. 28, paragraph 0148).
Regarding claim 18, Lee further discloses the microelectronic structure of claim 17, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 28) is located between the first metal plug (first 250 from the left corner of Fig. 28) and the first source/drain contact (250 vertically on left 221 in Fig. 28), and wherein the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 28) is located between the second source/drain (right 221 in Fig. 22B) and the second source/drain contact (250 vertically on right 221 in Fig. 28).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2018/0337176) (hereafter Lee), in view of Huang et al. (US 2021/0098307) (hereafter Huang).
Regarding claim 19, Lee discloses a method comprising:
forming a first nanosheet transistor (transistor with left 221 in Fig. 10C; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a first source/drain (left 221 in Fig. 10C, paragraph 0132);
forming a second nanosheet transistor (transistor with right 221 in Fig. 10C; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a second source/drain (right 221 in Fig. 10C, paragraph 0132);
forming a first semiconductor alloy liner 227 (Fig. 19, paragraph 0126) on top of the first source/drain (left 221 in Fig. 19) and the second source/drain (right 221 in Fig. 19); and
laterally etching (see Fig. 13 and paragraph 0113) the first source/drain (left 221 in Fig. 13) and the second source/drain (right 221 in Fig. 13), wherein the laterally etching extends outwards from the first trench 244 (Fig. 13, paragraph 0113), wherein after the lateral etching process each of the first source/drain (left 221 in Fig. 13) and the second source/drain (right 221 in Fig. 13) have an asymmetrical profile when cut through the first (left 221 in Fig. 13) and second source/drain (right 221 in Fig. 13).
Lee does not disclose forming a shared source/drain contact, wherein the shared source/drain contact extends over both the first source/drain and the second source/drain;
forming a first trench, wherein the first trench divides the shared source/drain contact in to a first source/drain contact and a second source/drain contact, wherein the first trench exposes the first source/drain and the second source/drain.
Huang discloses forming a shared source/drain contact 232 (Fig. 2E-2, paragraph 0069), wherein the shared source/drain contact 232 (Fig. 2E-2) extends over both the first source/drain (leftmost 150 in Fig. 2E-2, paragraph 0051) and the second source/drain (rightmost 150 in Fig. 2E-2, paragraph 0051);
forming a first trench 232t (Fig. 2F-2, paragraph 0073), wherein the first trench 232t (Fig. 2F-2) divides the shared source/drain contact 232a (Fig. 2F-2) in to a first source/drain contact (middle 232a in Fig. 2F-2) and a second source/drain contact (rightmost 232a in Fig. 2F-2), wherein the first trench 232t (Fig. 2F-2) exposes the first source/drain (leftmost 150 in Fig. 2F-2) and the second source/drain (rightmost 150 in Fig. 2F-2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to include forming a shared source/drain contact, wherein the shared source/drain contact extends over both the first source/drain and the second source/drain; forming a first trench, wherein the first trench divides the shared source/drain contact in to a first source/drain contact and a second source/drain contact, wherein the first trench exposes the first source/drain and the second source/drain, as taught by Huang, since the contact structures 232a (Huang, Fig. 2H-2, paragraph 0084) are formed before the formation of the dielectric layer 250 (Huang, Fig. 2H-2, paragraph 0084) such that the formation of the contact structures 232a (Huang, Fig. 2H-2, paragraph 0084) is not affected by the dielectric layer 250 (Huang, Fig. 2H-2, paragraph 0084) and the yield of the contact structures 232a (Huang, Fig. 2H-2, paragraph 0084) is improved by the sequence of the processes for forming the contact structures 232a (Huang, Fig. 2H-2, paragraph 0084) and the dielectric layer 250 (Huang, Fig. 2H-2, paragraph 0084).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huang as applied to claim 19 above, and further in view of Koh et al. (US 2019/0157269) (hereafter Koh) and Jun et al. (US 2018/0261596) (hereafter Jun).
Regarding claim 20, Lee in view of Huang discloses the method of claim 19, however Lee and Huang do not disclose forming a second semiconductor alloy liner in a first cavity formed in the first source/drain from the lateral etching process;
forming the second semiconductor alloy liner in a second cavity formed in the second source/drain from the lateral etching process;
filling the first trench, the first cavity, and the second cavity with a metal fill;
forming a second trench to separate a first metal plug and a second metal plug, wherein the first metal plug is located adjacent to the first source/drain and the second metal plug is located adjacent to the second source/drain; and
forming a dielectric pillar by filling the second trench with a dielectric material.
Koh discloses forming a second semiconductor alloy liner (128A and 128B in Fig. 15A, paragraph 0045) in a first cavity (opening in 104A of Fig. 14A) formed in the first source/drain 104A (Fig. 15A, paragraph 0034) from the lateral etching process (see Fig. 14A and paragraph 0044);
forming the second semiconductor alloy liner (128A and 128B in Fig. 15A) in a second cavity (opening in 104B of Fig. 14A) formed in the second source/drain 104B (Fig. 15A, paragraph 0034) from the lateral etching process (see Fig. 14A and paragraph 0044);
filling the first trench (116A and 116B in Fig. 16A), the first cavity (opening in 104A of Fig. 14A), and the second cavity (opening in 104B of Fig. 14A) with a metal fill 130 (Fig. 16A, paragraph 0046);
wherein the first metal plug (left 130 in Fig. 15A) is located adjacent to the first source/drain 104A (Fig. 15A) and the second metal plug (right 130 in Fig. 15A) is located adjacent to the second source/drain 104B (Fig. 15A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Huang to include forming a second semiconductor alloy liner in a first cavity formed in the first source/drain from the lateral etching process; forming the second semiconductor alloy liner in a second cavity formed in the second source/drain from the lateral etching process; filling the first trench, the first cavity, and the second cavity with a metal fill; and wherein the first metal plug is located adjacent to the first source/drain and the second metal plug is located adjacent to the second source/drain, as taught by Koh, since the greater etching depth into the S/D features 104A (Koh, Fig. 14A, paragraph 0043) generally leads to increased interfacial area for S/D contacts and therefore reduced S/D contact resistance.
Lee, Huang, and Koh do not disclose forming a second trench to separate a first metal plug and a second metal plug; and
forming a dielectric pillar by filling the second trench with a dielectric material.
Jun discloses forming a second trench (FS1 in Fig. 7K, paragraph 0071) to separate a first metal plug (second CA1 in Fig. 7K, paragraph 0085) and a second metal plug (third CA1 in Fig. 7K, paragraph 0085); and
forming a dielectric pillar 128 (Fig. 7R, paragraph 0106) by filling the second trench (FS1 in Fig. 7K) with a dielectric material (see paragraph 0106, wherein “fin isolation insulating film 128”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Huang and Koh to include forming a second trench to separate a first metal plug and a second metal plug; and forming a dielectric pillar by filling the second trench with a dielectric material, as taught by Jun, since the fin isolation insulating unit 120A (Jun, Fig. 7R, paragraph 0088) is formed on the plurality of fin-type active regions FA (Jun, Fig. 7R, paragraph 0088), after the plurality of gate lines GL (Jun, Fig. 7R, paragraph 0088) and the lower source/drain contact CA1 (Jun, Fig. 7R, paragraph 0088) are formed over the one of the plurality of fin-type active regions FA (Jun, Fig. 7R, paragraph 0088), a stress concentration of a compressive stress, for example, on the plurality of fin-type active regions FA (Jun, Fig. 7R, paragraph 0088) around the fin isolation insulating unit 120A (Jun, Fig. 7R, paragraph 0088) may be suppressed such that problems (Jun, paragraph 0088) due to electrical deterioration, such as a problem in which threshold voltages of transistors adjacent to the fin isolation region FS (Jun, Fig. 7R, paragraph 0088) among a plurality of transistors formed on the plurality of fin-type active regions FA (Jun, Fig. 7R, paragraph 0088) vary depending upon distances from the fin isolation insulating unit 120A (Jun, Fig. 7R, paragraph 0088), may be solved.
Response to Arguments
1. Applicant's arguments filed 1/9/2026 have been fully considered.
2. The applicant argues (REMARKS, third paragraph in page 8) that “Lim discloses that a cavity is formed in the top of the source/drain, where the cavity is filled in with a contact 180. Lim discloses a source/drain contact 180, but does not disclose a metal plug as the Office Action asserts. The cited references do not disclose or suggest "a first nanosheet transistor includes a first source/drain, wherein first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; and a second nanosheet transistor includes a second source/drain, wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the side source/drain, wherein the second cavity is filled by a second metal plug." Therefore, the rejection of claim 1 should be withdrawn.” However, Lim discloses first source/drain (first 150 from the left corner of Fig. 24, paragraph 0033) includes a first cavity (first H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the first cavity (first H from the left corner in Fig. 23) is located on a vertical side (lateral surface of first 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the first source/drain (first 150 from the left corner of Fig. 23), wherein the first cavity (first H from the left corner in Fig. 23) is filled by a first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117); and wherein second source/drain (third 150 from the left corner of Fig. 24, paragraph 0033) includes a second cavity (third H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the second cavity (third H from the left corner in Fig. 23) is located on a vertical side (lateral surface of third 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the second source/drain (third 150 from the left corner of Fig. 24), wherein the second cavity (third H from the left corner in Fig. 23) is filled by a second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
3. The applicant argues (REMARKS, fifth paragraph in page 8) that “Independent claim 9 have been similarly amended as claim 1, and for at least the forgoing reason they are distinguishable over the cited reference and withdrawal of the foregoing rejections is requested.” However, Lim discloses first source/drain (first 150 from the left corner of Fig. 24, paragraph 0033) includes a first cavity (first H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the first cavity (first H from the left corner in Fig. 23) is located on a vertical side (lateral surface of first 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the first source/drain (first 150 from the left corner of Fig. 23), wherein the first cavity (first H from the left corner in Fig. 23) is filled by a first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117); and wherein second source/drain (third 150 from the left corner of Fig. 24, paragraph 0033) includes a second cavity (third H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the second cavity (third H from the left corner in Fig. 23) is located on a vertical side (lateral surface of third 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the second source/drain (third 150 from the left corner of Fig. 24), wherein the second cavity (third H from the left corner in Fig. 23) is filled by a second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813