DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 6/1/2026 is acknowledged.
Applicant amended claims 1, 8, 9, and 17; and cancelled claims 7, 16, 19, and 20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8-15, 17, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "the first side and the side are located on opposite sides of the dielectric pillar” (Claim 1, Lines 11-12 ; and Claim 9, Lines 12-13). It is unclear the term, “the side”, is “a first side" (Claim 1, Line 10), “a second side” (Claim 1, Line 11), or new side. Claims 2-6 and 8 depending from claim 1 and claims 10-15, 17, and 18 depending from claim 9 inherit its deficiencies. Examiner interprets "the first side and the side are located on opposite sides of the dielectric pillar” to mean “the first side and the second side are located on opposite sides of the dielectric pillar”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 17 and 18 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 17 recites the limitation "The microelectronic structure of claim 17”, The claim 17 depends on itself. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 18 depending from claim 17 inherits its deficiencies. Examiner interprets "The microelectronic structure of claim 17” to mean “The microelectronic structure of claim 15”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2018/0337176) (hereafter Lee), in view of Lim et al. (US 2021/0036121) (hereafter Lim), in further view of Min et al. (US 2018/0138174) (hereafter Min)
Regarding claim 1, Lee discloses a microelectronic structure comprising:
a first nanosheet transistor (transistor with left 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a first source/drain (left 221 in Fig. 22B, paragraph 0132); and
a second nanosheet transistor (transistor with right 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a second source/drain (right 221 in Fig. 22B, paragraph 0132);
wherein the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) are adjacent to each other, wherein each of the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) have an asymmetrical profile (see Fig. 22B and paragraph 0132, wherein “the second conductivity type S/D structures 221 may have a slightly asymmetric cross section”) when cut through the first (left 221 in Fig. 22B) and second source/drain (right 221 in Fig. 22B).
Lee does not disclose first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug;
wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug; and
a dielectric pillar located between the first source/drain and the second source/drain.
Lim discloses first source/drain (first 150 from the left corner of Fig. 24, paragraph 0033) includes a first cavity (first H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the first cavity (first H from the left corner in Fig. 23) is located on a vertical side (lateral surface of first 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the first source/drain (first 150 from the left corner of Fig. 23), wherein the first cavity (first H from the left corner in Fig. 23) is filled by a first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117); and
wherein second source/drain (third 150 from the left corner of Fig. 24, paragraph 0033) includes a second cavity (third H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the second cavity (third H from the left corner in Fig. 23) is located on a vertical side (lateral surface of third 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the second source/drain (third 150 from the left corner of Fig. 24), wherein the second cavity (third H from the left corner in Fig. 23) is filled by a second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117); and
a dielectric pillar 200a (Fig. 24, paragraph 0036) located between the first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117) and the second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; and wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug; and a dielectric pillar located between the first source/drain and the second source/drain, as taught by Lim, since the contact plug 180 (Lim, Fig. 24, paragraph 0052) may penetrate through the upper insulating layer 195 (Lim, Fig. 24, paragraph 0052), the source/drain regions 150 (Lim, Fig. 24, paragraph 0052), and the lower insulating law 190 (Lim, Fig. 24, paragraph 0052), and may apply an electrical signal to the source/drain region 150 (Lim, Fig. 24, paragraph 0052).
Lee and Lim do not disclose the first metal plug is in direct contact with a first side of the dielectric pillar, wherein the second metal plug is in direct contact with a second side of the dielectric pillar, wherein the first side and the side are located on opposite sides of the dielectric pillar.
Min discloses the first metal plug 165a (Fig. 2, paragraph 0059) is in direct contact with a first side (left sidewall of 133 in Fig. 2) of the dielectric pillar (133, 175, 173, and 117 in Fig. 2), wherein the second metal plug 165b (Fig. 2, paragraph 0059) is in direct contact with a second side (right sidewall of 133 in Fig. 2) of the dielectric pillar (133, 175, 173, and 117 in Fig. 2), wherein the first side (left sidewall of 133 in Fig. 2) and the side (right sidewall of 133 in Fig. 2) are located on opposite sides of the dielectric pillar (133, 175, 173, and 117 in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Lim to form the first metal plug is in direct contact with a first side of the dielectric pillar, wherein the second metal plug is in direct contact with a second side of the dielectric pillar, wherein the first side and the side are located on opposite sides of the dielectric pillar, as taught by Min, since some example embodiments can encourage the first contact 165a (Min, Fig. 2, paragraph 0068) and the second contact 165b (Min, Fig. 2, paragraph 0068) to be formed into a complete shape while keeping the first spacer 117a (Min, Fig. 2, paragraph 0068) and the second spacer 117 (Min, Fig. 2, paragraph 0068) at proper heights, and minimize stress caused by the device isolating film 175 (Min, Fig. 2, paragraph 0068) on the channel region, thereby considerably enhancing performance of the semiconductor device.
Regarding claim 2, Lee further discloses the microelectronic structure of claim 1, further comprising: a first semiconductor alloy liner (227 contacting 221 in Fig. 22B, paragraph 0126) located on top of the first source/drain (left 221 in Fig. 22B) and on top of the second source/drain (right 221 in Fig. 22B).
Regarding claim 3, Lee further discloses the microelectronic structure of claim 2, further comprising: a second semiconductor alloy liner (227 contacting 220 in Fig. 22B, paragraph 0126) located adjacent a sidewall of the first source/drain (left 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located adjacent to a sidewall of the second source/drain (right 221 in Fig. 22B).
Regarding claim 4, Lee further discloses the microelectronic structure of claim 3, further comprising: a first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) located adjacent to the first source/drain (left 221 in Fig. 22B); a second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) located adjacent to the second source/drain (right 221 in Fig. 22B); wherein each the first and second overlap sections are formed by a portion of the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) overlapping each other.
Regarding claim 5, Lee further discloses the microelectronic structure of claim 4, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), and wherein the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B).
Regarding claim 9, Lee discloses a microelectronic structure comprising:
a first nanosheet transistor (transistor with left 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a first source/drain (left 221 in Fig. 22B, paragraph 0132); and
a second nanosheet transistor (transistor with right 221 in Fig. 22B; and see paragraph 0139, wherein “a gate-all-around FET, in which the channels of the FET are nano-wires”) includes a second source/drain (right 221 in Fig. 22B, paragraph 0132); and
a first source/drain contact (250 vertically on left 221 in Fig. 22B, paragraph 0128) and a second source/drain contact (250 vertically on right 221 in Fig. 22B, paragraph 0128);
wherein the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) are adjacent to each other, wherein each of the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) have an asymmetrical profile (see Fig. 22B and paragraph 0132, wherein “the second conductivity type S/D structures 221 may have a slightly asymmetric cross section”) when cut through the first (left 221 in Fig. 22B) and second source/drain (right 221 in Fig. 22B), wherein the first source/drain (left 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B) combined have a substantially symmetrical profile when cut through the first (left 221 in Fig. 22B) and second source/drain (right 221 in Fig. 22B).
Lee does not disclose first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug;
wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug; and
a dielectric pillar located between the first source/drain and the second source/drain.
Lim discloses first source/drain (first 150 from the left corner of Fig. 24, paragraph 0033) includes a first cavity (first H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the first cavity (first H from the left corner in Fig. 23) is located on a vertical side (lateral surface of first 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the first source/drain (first 150 from the left corner of Fig. 23), wherein the first cavity (first H from the left corner in Fig. 23) is filled by a first metal plug (first 180 from the left corner of Fig. 24, paragraph 0117);
wherein second source/drain (third 150 from the left corner of Fig. 24, paragraph 0033) includes a second cavity (third H from the left corner in Fig. 23, paragraph 0116), wherein an opening of the second cavity (third H from the left corner in Fig. 23) is located on a vertical side (lateral surface of third 150 from the left corner of Fig. 23 contacting 143 in Fig. 23) of the second source/drain (third 150 from the left corner of Fig. 24), wherein the second cavity (third H from the left corner in Fig. 23) is filled by a second metal plug (third 180 from the left corner of Fig. 24, paragraph 0117); and
a dielectric pillar located between the first source/drain and the second source/drain.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form first source/drain includes a first cavity, wherein an opening of the first cavity is located on a vertical side of the first source/drain, wherein the first cavity is filled by a first metal plug; wherein second source/drain includes a second cavity, wherein an opening of the second cavity is located on a vertical side of the second source/drain, wherein the second cavity is filled by a second metal plug; and a dielectric pillar located between the first source/drain and the second source/drain, as taught by Lim, since the contact plug 180 (Lim, Fig. 24, paragraph 0052) may penetrate through the upper insulating layer 195 (Lim, Fig. 24, paragraph 0052), the source/drain regions 150 (Lim, Fig. 24, paragraph 0052), and the lower insulating law 190 (Lim, Fig. 24, paragraph 0052), and may apply an electrical signal to the source/drain region 150 (Lim, Fig. 24, paragraph 0052).
Lee and Lim do not disclose the first metal plug is in direct contact with a first side of the dielectric pillar, wherein the second metal plug is in direct contact with a second side of the dielectric pillar, wherein the first side and the side are located on opposite sides of the dielectric pillar.
Min discloses the first metal plug 165a (Fig. 2, paragraph 0059) is in direct contact with a first side (left sidewall of 133 in Fig. 2) of the dielectric pillar (133, 175, 173, and 117 in Fig. 2), wherein the second metal plug 165b (Fig. 2, paragraph 0059) is in direct contact with a second side (right sidewall of 133 in Fig. 2) of the dielectric pillar (133, 175, 173, and 117 in Fig. 2), wherein the first side (left sidewall of 133 in Fig. 2) and the side (right sidewall of 133 in Fig. 2) are located on opposite sides of the dielectric pillar (133, 175, 173, and 117 in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Lim to form the first metal plug is in direct contact with a first side of the dielectric pillar, wherein the second metal plug is in direct contact with a second side of the dielectric pillar, wherein the first side and the side are located on opposite sides of the dielectric pillar, as taught by Min, since some example embodiments can encourage the first contact 165a (Min, Fig. 2, paragraph 0068) and the second contact 165b (Min, Fig. 2, paragraph 0068) to be formed into a complete shape while keeping the first spacer 117a (Min, Fig. 2, paragraph 0068) and the second spacer 117 (Min, Fig. 2, paragraph 0068) at proper heights, and minimize stress caused by the device isolating film 175 (Min, Fig. 2, paragraph 0068) on the channel region, thereby considerably enhancing performance of the semiconductor device.
Regarding claim 10, Lee further discloses the microelectronic structure of claim 9, further comprising: a first semiconductor alloy liner (227 contacting 221 in Fig. 22B, paragraph 0126) located on top of the first source/drain (left 221 in Fig. 22B) and on top of the second source/drain (right 221 in Fig. 22B).
Regarding claim 11, Lee further discloses the microelectronic structure of claim 10, wherein the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) is located between the first source/drain contact (250 vertically on left 221 in Fig. 22B) and the first source/drain (left 221 in Fig. 22B), wherein the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) is located between the second source/drain contact (250 vertically on right 221 in Fig. 22B) and the second source/drain (right 221 in Fig. 22B).
Regarding claim 12, Lee further discloses the microelectronic structure of claim I1, further comprising: a second semiconductor alloy liner (227 contacting 220 in Fig. 22B, paragraph 0126) located adjacent a sidewall of the first source/drain (left 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located adjacent to a sidewall of the second source/drain (right 221 in Fig. 22B).
Regarding claim 13, Lee further discloses the microelectronic structure of claim 12, further comprising: a first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) located adjacent to the first source/drain (left 221 in Fig. 22B); a second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) located adjacent to the second source/drain (right 221 in Fig. 22B); wherein each the first and second overlaps sections are formed by a portion of the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second semiconductor alloy liner (227 contacting 220 in Fig. 22B) overlapping each other.
Regarding claim 14, Lee further discloses the microelectronic structure of claim 13, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), and wherein the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the first semiconductor alloy liner (227 contacting 221 in Fig. 22B) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 22B) is thicker than the second semiconductor alloy liner (227 contacting 220 in Fig. 22B).
Claims 6, 8, 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Lim as applied to claims 5 and 14 above, and further in view of Suh et al. (US 2017/0365604) (hereafter Suh).
Regarding claim 6, Lee in view of Lim discloses the microelectronic structure of claim 5, however Lee and Lim do not disclose the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and
wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain.
Suh discloses the first metal plug (first 190 from the left corner of Fig. 25B, paragraph 0106) is located adjacent to the second semiconductor alloy liner (first 164B from the left corner of Fig. 25B, paragraph 0106), wherein a portion of second semiconductor alloy liner is located between the first metal plug (first 190 from the left corner of Fig. 25B) and the first source/drain (first 162A from the left corner of Fig. 25B, paragraph 0055); and
wherein the second metal plug (fourth 190 from the left corner of Fig. 25B, paragraph 0106) located adjacent to the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), wherein a portion of second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located between the second metal plug (fourth 190 from the left corner of Fig. 25B) and the second source/drain (first 164A from the left corner of Fig. 25B, paragraph 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Lim to form the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain, as taught by Suh, since a metal silicide layer lowers the contact resistance between a metal plug and a source/drain.
Regarding claim 8, Lee further discloses the microelectronic structure of claim 5, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 is vertically above a lower portion of leftmost 250 below 227) of the first metal plug (first 250 from the left corner of Fig. 28, paragraph 0148) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 is vertically above a lower portion of rightmost 250 below 227) of the second metal plug (fourth 250 from the left corner of Fig. 28, paragraph 0148).
Regarding claim 15, Lee in view of Lim discloses the microelectronic structure of claim 14, however Lee and Lim do not disclose the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and
wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain.
Suh discloses the first metal plug (first 190 from the left corner of Fig. 25B, paragraph 0106) is located adjacent to the second semiconductor alloy liner (first 164B from the left corner of Fig. 25B, paragraph 0106), wherein a portion of second semiconductor alloy liner is located between the first metal plug (first 190 from the left corner of Fig. 25B) and the first source/drain (first 162A from the left corner of Fig. 25B, paragraph 0055); and
wherein the second metal plug (fourth 190 from the left corner of Fig. 25B, paragraph 0106) located adjacent to the second semiconductor alloy liner (227 contacting 220 in Fig. 22B), wherein a portion of second semiconductor alloy liner (227 contacting 220 in Fig. 22B) is located between the second metal plug (fourth 190 from the left corner of Fig. 25B) and the second source/drain (first 164A from the left corner of Fig. 25B, paragraph 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee in view of Lim to form the first metal plug is located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the first metal plug and the first source/drain; and wherein the second metal plug located adjacent to the second semiconductor alloy liner, wherein a portion of second semiconductor alloy liner is located between the second metal plug and the second source/drain, as taught by Suh, since a metal silicide layer lowers the contact resistance between a metal plug and a source/drain.
Regarding claim 17, Lee further discloses the microelectronic structure of claim 17, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 is vertically above a lower portion of leftmost 250 below 227) of the first metal plug (first 250 from the left corner of Fig. 28, paragraph 0148) and the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 28) is located on top (see Fig. 28, wherein horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 is vertically above a lower portion of rightmost 250 below 227) of the second metal plug (fourth 250 from the left corner of Fig. 28, paragraph 0148).
Regarding claim 18, Lee further discloses the microelectronic structure of claim 17, wherein the first overlap section (horizontally overlap section between 227 contacting left 221 and 227 contacting left 220 in Fig. 28) is located between the first metal plug (first 250 from the left corner of Fig. 28) and the first source/drain contact (250 vertically on left 221 in Fig. 28), and wherein the second overlap section (horizontally overlap section between 227 contacting right 221 and 227 contacting right 220 in Fig. 28) is located between the second source/drain (right 221 in Fig. 22B) and the second source/drain contact (250 vertically on right 221 in Fig. 28).
Response to Arguments
1. Applicant's arguments filed 6/1/2026 have been fully considered.
2. Applicant's arguments with respect to claims 1-6, 8-15, 17, and 18 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights