DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I and Species A with claims 1-3 and 7-17 readable thereon in the reply filed on July 1, 2026 is acknowledged. As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Objections
Claim 17 is objected to because of the following informalities:
Claim 17 includes “integrated circuity ” which is a typographical error of “integrated circuitry”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-8, 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US20150357293A1 (“Tomita”).
RE: 1, Tomita discloses A semiconductor die (semiconductor chip SC in FIG. 1, [0067]), comprising:
a substrate (semiconductor chip SC including substrate SB and element formation region, excluding the guard ring GR, [0063]-[0069]) comprising integrated circuitry (PX, ADC, PGA,TG, VSCAN, Bridge, LVDS, [0065]); and
a guard ring (GR, [0066]) surrounding the integrated circuitry,
wherein the guard ring comprises a plurality of traces (In FIG. 26: GRP, including GRL1, GRL2, GRR1, GRR2, [0151]-[0152]; GR includes a plurality of guard ring conductive layers GRP1 to GRP8, [0100]) arranged in a pattern of lines (GRL1, GRR1) and rungs (GRL2, GRR2),
wherein the lines extend around the integrated circuitry (FIG. 26 shows lines GRL1, GRR1 extend around the element formation region which includes the integrated circuitry, [0065]), and
wherein the rungs extend crosswise between at least some of the lines (FIG. 26 shows the rungs GRL2, GRR2 extend crosswise between at least some of the lines GRL1, GRR1).
RE: Claim 2, Tomita discloses The semiconductor die of Claim 1, wherein:
the lines are substantially parallel to each other (FIG. 26 shows the top and bottom lines of GRL1, GRR1 are substantially parallel to each other, and the left and right lines of GRL1, GRR1 are substantially parallel to each other); and
the rungs are substantially orthogonal to the lines (FIG. 26 shows the rungs GRL2, GRR2 are substantially orthogonal to the top and bottom lines GRL1, GRR1).
RE: Claim 3, Tomita discloses The semiconductor die of Claim 1, wherein the rungs are positioned in a stitch zone of the guard ring (guard ring conductive layer GRP in the present embodiment (for example, guard ring conductive layers GRP2 to GRP6 shown in FIG. 4) is formed through divided exposure. Therefore, this guard ring conductive layer GRP has first pattern portion GRL (a portion on the left in the figure) of the guard ring conductive layer formed through exposure with the use of the first photomask and second pattern portion GRR (a portion on the right in the figure) of the guard ring conductive layer formed through exposure with the use of the second photomask, [0150], see FIG. 26);
The instant application discloses on a chip stitched across multiple reticle fields, a guard ring is printed by multiple reticles/masks, each patterned with a different portion of the guard ring, which are exposed sequentially and joined at the stitch, [0022];
In Tomita, as the portions of the guard ring GRL and GRR are formed by different photomasks and joined at region P2 in FIG. 26, [0039]-[0040], under a broad reasonable interpretation, Tomita discloses in FIG. 26 the rungs GRL2, GRR2 are positioned in a stitch zone which is where the patterns GRL and GRR are joined).
RE: Claim 7, Tomita discloses The semiconductor die of Claim 1, wherein the guard ring extends along a perimeter of the substrate (FIG. 1 shows the guard ring GR extends along a perimeter of the substrate SC).
RE: Claim 8, Tomita discloses semiconductor die of Claim 1, wherein the guard ring has a substantially rectangular or square shape (FIG. 1 shows the guard ring GR has a substantially rectangular shape).
RE: Claim 11, Tomita discloses The semiconductor die of Claim 1, wherein the plurality of traces comprise metal (Guard ring GR is constituted of multiple conductive layers CL, [0074]; conductive layers CL is formed, for example, of a material including Cu (copper), [0070]).
RE: Claim 12, Tomita discloses The semiconductor die of Claim 11, wherein the metal comprises copper, manganese, titanium, gold, silver, palladium, nickel, aluminum, tantalum, cobalt, or iron (Guard ring GR is constituted of multiple conductive layers CL, [0074]; conductive layers CL is formed, for example, of a material including Cu (copper), [0070]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomita.
RE: Claim 9, Tomita does not explicitly disclose The semiconductor die of Claim 1, wherein the guard ring has a size larger than 26 millimeters by 33 millimeters.
However, Tomita discloses The semiconductor device in the present embodiment may be, for example, a 35-mm full-size sensor. The semiconductor device in the present embodiment may implement, for example, a pixel portion alone of a 35-mm full-size sensor or a control circuit portion alone of a 35-mm full-size sensor, [0166]; Accordingly, as the guard ring GR surrounds the pixel portion PX in FIG. 1, the guard ring GR would have at least one dimension of 35mm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make another dimension of the guard ring GR 35mm as this would be the result of routine optimization since the length and width dimensions of a guard ring are considered result effective variables which achieve a recognized result of accommodating sensors, and one of ordinary skill would have understood that if one dimension (e.g., length) of the guard ring is 35mm, setting the other dimension of the guard ring (e.g., width) to 35mm would better accommodate a 35-mm full size sensor; Accordingly, one of ordinary skill would have formulated the claimed guard ring size range of larger than 26 millimeters by 33 millimeters with a reasonable expectation of success, see MPEP 2144.
Further, the Federal Circuit has held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device, MPEP 2144; In the instant case, a guard ring with the claimed relative dimensions larger than 26 millimeters by 33 millimeters would not perform differently than the device in Tomita; Accordingly, the claimed device is not patentably distinct from the device in Tomita).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomita as applied to claim 1 above, and further in view of US 20180226364 A1 (“Kim”).
RE: Claim 10, Tomita does not explicitly disclose The semiconductor die of Claim 1, wherein the guard ring is a hermetic guard ring, wherein the hermetic guard ring is in contact with the substrate.
However, Tomita discloses guard ring GR plays a role to prevent entry of water (moisture) from an outer peripheral side into the element formation region, [0066].
In the same field of endeavor, Kim discloses at least one of the first metal guard ring or the second metal guard ring 514 or 516 provides a hermetic seal for the metallization structure 508, [0041].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the guard ring GR to be a hermetic guard ring as taught by Kim in order to better protect the element formation region from moisture or air in the surrounding environment. As modified, the hermetic guard ring GR contacts the substrate SB as shown in FIG. 4 Tomita.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomita as applied to claim 1, further in view of US20220115426A1 (“Son”).
RE: Claim 13, Tomita does not explicitly disclose The semiconductor die of Claim 1, wherein the semiconductor die is electrically coupled to a package substrate.
In the same field of endeavor, Son discloses in FIG. 1A:
wherein a semiconductor die (120, [0021]) is electrically coupled to a package substrate (110, [0021]; FIG. 1A shows the die 120 is electrically coupled to package substrate 110 through bonding wires 130).
Son further discloses:
the stress reducing layer 170 may include substantially the same material as the dam 160. Accordingly, in the image sensor package 100 of some example embodiments, defects (e.g., cracks) may be greatly reduced in the bonding wires 130 by reducing stress applied to the bonding wires 130. As a result, an image sensor package having improved reliability may be implemented, [0039].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically couple the semiconductor die SC to a package substrate as taught by Son in order to improve reliability as further taught by Son.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Tomita.
RE: Claim 14, Son discloses An electronic device (100), comprising:
a circuit board (110 is a printed circuit board, [0019]); and
an integrated circuit (circuitry of 120 including chip body 122, sensor circuitry 124, and a wiring layer, [0026]) electrically coupled to the circuit board (The chip pads 126 are electrically connected to the wiring layer of the image sensor chip 120, [0028]; The chip pads 126 are electrically connected to the upper substrate pads 113 of the package substrate 110, [0029]),
wherein the integrated circuit comprises:
a substrate (substrate of 122, [0026]);
integrated circuitry on the substrate (sensor circuitry 124 and a wiring layer on substrate of 122, [0026]).
Son does not explicitly disclose:
a guard ring surrounding the integrated circuitry,
wherein the guard ring comprises a plurality of traces arranged in a pattern of lines and rungs,
wherein the lines extend around the integrated circuitry, and
wherein the rungs extend across at least some of the lines.
In a similar field of endeavor, Tomita discloses in FIGs. 1, 26:
a guard ring (GR, [0066]) surrounding integrated circuitry (PX, ADC, PGA,TG, VSCAN, Bridge, LVDS, [0065]; In the element formation region, various elements formed from conductive layer CL are formed, [0071]),
wherein the guard ring comprises a plurality of traces (In FIG. 26: GRP, including GRL1, GRL2, GRR1, GRR2, [0151]-[0152]; GR includes a plurality of guard ring conductive layers GRP1 to GRP8, [0100]) arranged in a pattern of lines (GRL1, GRR1) and rungs (GRL2, GRR2),
wherein the lines extend around the integrated circuitry (FIG. 26 shows lines GRL1, GRR1 extend around the element formation region which includes the integrated circuitry, [0065]), and
wherein the rungs extend across at least some of the lines (FIG. 26 shows the rungs GRL2, GRR2 extend across at least some of the lines GRL1, GRR1).
Tomita discloses guard ring GR plays a role to prevent entry of water (moisture) from an outer peripheral side into the element formation region on an inner peripheral side of the element formation region, [0066].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a guard ring surrounding the integrated circuitry as taught by Tomita in order to prevent entry of water or moisture therein.
RE: Claim 15, Son in view of Tomita discloses The electronic device of Claim 14, wherein:
the lines are substantially parallel to each other (Tomita FIG. 26 shows the top and bottom lines of GRL1, GRR1 are substantially parallel to each other, and the left and right lines of GRL1, GRR1 are substantially parallel to each other); and
the rungs are substantially orthogonal to the lines (Tomita FIG. 26 shows the rungs GRL2, GRR2 are substantially orthogonal to the top and bottom lines GRL1, GRR1).
RE: Claim 16, Son in view of Tomita discloses The electronic device of Claim 14, wherein the rungs are positioned in a stitch zone of the guard ring (Tomita discloses guard ring conductive layer GRP in the present embodiment (for example, guard ring conductive layers GRP2 to GRP6 shown in FIG. 4) is formed through divided exposure. Therefore, this guard ring conductive layer GRP has first pattern portion GRL (a portion on the left in the figure) of the guard ring conductive layer formed through exposure with the use of the first photomask and second pattern portion GRR (a portion on the right in the figure) of the guard ring conductive layer formed through exposure with the use of the second photomask, [0150], see FIG. 26;
The instant application discloses on a chip stitched across multiple reticle fields, a guard ring is printed by multiple reticles/masks, each patterned with a different portion of the guard ring, which are exposed sequentially and joined at the stitch, [0022];
In Tomita, as the portions of the guard ring GRL and GRR are formed by different photomasks and joined at region P2 in FIG. 26, [0039]-[0040], under a broad reasonable interpretation, Tomita discloses in FIG. 26 the rungs GRL2, GRR2 are positioned in a stitch zone which is where the patterns GRL and GRR are joined).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Tomita as applied to claim 14, further in view of US 20100315541A1 (“Egawa”).
RE: Claim 17, Son in view of Tomita does not explicitly disclose The electronic device of Claim 14, wherein the integrated circuity comprises processing circuitry, memory circuitry, or communication circuitry.
In the same field of endeavor, Egawa discloses The sensor chip 1 includes a sensor unit 11, a line memory 12, a resolution restoration circuit 13, a signal processing circuit 18, a system timing generation (SG) circuit 15, a command decoder 16 and a serial interface 17, [0047].
Egawa further discloses since a signal level that is approximately double a single level of signal G can be obtained by acquiring a resolution signal from the transparent pixel (W), an increase in noise can be suppressed, and the resolution characteristics MTF can be improved, [0081].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuitry 124 of the sensor chip to include a line memory and/or a signal processing circuit 18 as taught by Egawa in order to improve resolution characteristics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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