DETAILED ACTION
This correspondence is in response to the communications received 03/07/2026. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to the title overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Response to Arguments
Applicant's arguments filed 03/07/2026 have been fully considered but they are not persuasive.
Applicant asserts on page 11 of the Remarks that the amendment to claim 1 is supported by the specification. Specifically, that paragraphs [0024], [0025], and [0027] disclose that the first and second transistors may be IGZO transistors and that this would then imply the second and third conductive layers to comprise a semiconductor material.
However, as discussed in the previous Office Action, this functionality as a semiconductor material is contradicted by the inclusion of the word conductive in the name of each element. Describing the second and third conductive layers as “conductive” while simultaneously claiming that each layer also comprise one or more semiconductor materials results in the written description failing to describe how the claimed features map to the transistors of the schematic given the dual nature of the above conductive layers. In order for the second and third conductive layers to comprise a semiconductor material, they would no longer be conductive, as per the very definition of the word semiconductor.
Further, there does not appear to be a direct connection between the disclosed IGZO transistors and the second and third conductive layers. This is further muddied by paragraph [0024] which states that the second conductive layer also functions as a third terminal of the first transistor, which would indicate that the conducive layers are indeed conductive and would not serve as channel forming materials. Thus, the rejection is maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 9 and the claims that depend therefrom are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a second conductive layer disposed along a sidewall of the opening; … [and] a third conductive layer”. Figs. 1A and 1B as well as paragraph [0024] of the specification indicate that a portion of the second conductive layer 112 and the third conductive layer 118 form the channel regions of the first and second transistors respectively. The characterization of these conductive layers as channel layers requires additional description. As both layers are denoted as conductive, it is unclear how they provide the switching functionality required for the channel material. The claimed subject matter points to two transistors first presented in claim 7. These transistors are the only method presented to explain the relationship between the claimed features. Then when looking to the figures and the specification to relate the claimed features and the transistors, the written description fails at a basic level to describe how the claimed features map to the transistors of the schematic given the dual nature of the above conductive layers.
Claim 1 recites “wherein the second conductive layer and the third conductive layer each comprise one or more semiconductor materials and are configured to serve as channel regions of respective transistors”. However, the specification only appears to state “The second conductive layer 112 can be formed of a conductive material”, paragraph [0037], and “The third conductive layer 118 can be formed of a conductive material”, paragraph [0041]. Further, the specification does not appear to describe any elements to be of specific semiconductor materials other than disclosing that the transistors of the DRAM cell may be IGZO transistors, however this done without relating the IGZO to any given element. Thus, the requirement that “wherein the second conductive layer and the third conductive layer each comprise one or more semiconductor materials and are configured to serve as channel regions of respective transistors” incorporates new matter into the claims, and therefore fails to comply with the written description requirement.
Claim 9 recites “the portion of the second conductive layer corresponding to the corresponding first conductive layer forms a channel and a third terminal of the first transistor”. The use of a single material, the second conductive layer, as both a channel and a terminal is not widely known in the art and requires additional support. As discussed above, it is not clear how a conductive material can function as a channel. Furthermore, the use of the second conductive material as a terminal reinforces its conductive nature. Thus, further support is necessary to describe how the second conductive layer can be used as both a channel and a terminal.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor structure (10), having a device defining region (D), the device defining region including a first portion (P1) and a second portion (P2) separated from each other (see Fig. 1A), the semiconductor structure comprising:
a stack (104) comprising a plurality of first conductive layers (106) and a plurality of first dielectric layers (108) disposed alternately (see Fig. 1B), the stack having an opening (O) through the stack in the device defining region (see Fig. 1A and [0017]);
a second conductive layer (112) disposed along a sidewall of the opening (see Fig. 1A);
a first conductive pillar (114) disposed in the opening in the first portion of the device defining region (see Fig. 1A);
a third conductive layer (118) disposed in the opening along an edge of the second portion of the device defining region (see Fig. 1A); and
a second conductive pillar (120) and a third conductive pillar (122) disposed in the second portion and separated from each other (see Fig. 1A);
wherein the second conductive layer and the third conductive layer each comprise one or more semiconductor materials and are configured to serve as channel regions of respective transistors.
Allowable Subject Matter
Claim 1 would be potentially allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor structure as recited in the claims of the instant application.
Regarding claim 1, the prior art of Tomishima (US 20210151437 A1) discloses a 2T gain cell but fails to disclose the specific claims of the instant application e.g. “a stack comprising a plurality of first conductive layers and a plurality of first dielectric layers disposed alternately”.
Claims 2-13 would be potentially allowable if rewritten to overcome the rejections under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 2-13 are allowable by virtue of their dependence on claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893