DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-4, 6-8, and 13-20 in the reply filed on 10/29/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-8, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rubin et al. (US pub 20200035603).
With respect to claim 1, Rubin et al. teach a semiconductor package, comprising (see figs. 1-13, particularly fig. 1 and associated text):
a lower structure 110;
a first semiconductor chip 140 on the lower structure, the first semiconductor chip comprising a hot spot (bottom area of 140);
a second semiconductor chip 142 horizontally spaced apart from the first semiconductor chip on the lower structure; and
a connection chip 120 in the lower structure and connecting the first and second semiconductor chips to each other, wherein the hot spot vertically overlaps the connection chip.
With respect to claim 2, Rubin et al. teach the first semiconductor chip comprises a first side surface (right) adjacent the second semiconductor chip, and a second side surface (left) which is opposite to the first side surface, and the hot spot is closer to the first side surface than to the second side surface. See fig. 1 and associated text.
With respect to claim 3, Rubin et al. teach the connection chip is exposed to an outside of the lower structure at a top surface of the lower structure. See fig. 1 and associated text.
With respect to claim 4, Rubin et al. teach the lower structure comprises: an insulating layer 110 including a recessed portion (area where 120 occupies) in a top surface thereof; upper substrate pads (connectors right above 110) at the top surface of the insulating layer; and lower substrate pads (connectors right under 110) at a bottom surface of the insulating layer. See fig. 1 and associated text.
With respect to claim 6, Rubin et al. teach comprising a sub-semiconductor package 144 horizontally spaced apart from the first and second semiconductor chips on the lower structure. See fig. 1 and associated text.
With respect to claim 7, Rubin et al. teach a molding portion 162 or 150 at least partially covering the first and second semiconductor chips and the sub-semiconductor package. See fig. 1 and associated text.
With respect to claim 8, Rubin et al. teach a molding portion 162 or 150 on the lower structure and the first and second semiconductor chips. See fig. 1 and associated text.
With respect to claim 13, Rubin et al. teach the hot spot is an intellectual property (IP) block including at least one of HBM DRAM or a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU). See fig. 1 and associated text.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhai et al. (US pat 10943869).
With respect to claim 14, Zhai et al. teach a semiconductor package, comprising (see figs. 1-13, particularly figs. 8 and 9 and associated text):
a lower structure 140,160;
a first semiconductor chip 130 on the lower structure, the first semiconductor chip comprising a hot spot (bottom area of 130);
a second semiconductor chip 132 horizontally spaced apart from the first semiconductor chip on the lower structure;
a connection chip 110 in the lower structure and connecting the first semiconductor chip to the second semiconductor chip;
an adhesive layer 146 between the connection chip and the lower structure; and
a molding portion 172 on the lower structure and the first and second semiconductor chips,
wherein the hot spot is an intellectual property (IP) block including at least one of HBM DRAM or a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU) (see text description of fig. 6),
the connection chip is vertically aligned with the hot spot,
a top surface of the connection chip is exposed to an outside of the lower structure at a top surface of the lower structure,
a top surface of at least one of the first and second semiconductor chips is exposed to an outside of the molding portion at a top surface of the molding portion (see fig. 9),
the connection chip has a first thickness, and at least one of the first and second semiconductor chips has a second thickness larger than the first thickness (see fig. 8).
With respect to claim 15, Zhai et al. teach the first semiconductor chip comprises a first side surface (right) adjacent the second semiconductor chip and an opposite second side surface (left) facing away from the second semiconductor chip, and the hot spot is closer to the first side surface than to the second side surface. See figs. 8 and 9 and associated text.
Claim(s) 18, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rubin et al. (US pub 20200035603).
With respect to claim 18, Rubin et al. teach a semiconductor package, comprising (see figs. 1-13, particularly fig. 1 and associated text):
a lower structure 110 comprising a recessed portion (area where 120 occupies);
a first semiconductor chip 140 and a second semiconductor chip 142 on the lower structure;
a connection chip 120 in the recessed portion of the lower structure and connecting the first and second semiconductor chips;
a sub-package 144 horizontally spaced apart from the first and second semiconductor chips on the lower structure; and
a molding portion 150 or 162 on the lower structure, the first and second semiconductor chips, and the sub-package,
wherein the first semiconductor chip comprises a hot spot (bottom part of 140) therein, and
the hot spot and at least a portion of the second semiconductor chip overlap the connection chip in a vertical direction.
With respect to claim 19, Rubin et al. teach the hot spot is an intellectual property (IP) block including at least one of HBM DRAM or a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU). See fig. 1 and associated text.
With respect to claim 19, Rubin et al. teach the first semiconductor chip comprises a first side surface (right), which is adjacent and faces the second semiconductor chip, and a second side surface (left), which is opposite to the first side surface and faces away from the second semiconductor chip, and the hot spot is closer to the first side surface than to the second side surface. See fig. 1 and associated text.
Allowable Subject Matter
Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having first and second chips over a structure having an embedded bridging chip that are connected to first and second chips as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897