DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-7) in the reply filed on 9/30/2025 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER THAT INCLUDES ALUMINUM
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Gould (US 5047833), hereinafter Gould.
Regarding claim 1, Gould (US 5047833) (refer to Figure 4, also see associated Figures 1-3) teaches a semiconductor device (10, Col. 3, lines 24-42) comprising:
a first conductive layer (comprising 42; i.e. 42, with overlapping part of 41 under it - see Figures 3-4, described as “tri-metal 42” in Col. 4, lines 28-50);
a second conductive layer (41, i.e. part of 41 where there is no 42 over 41, described as “aluminum layer 41” in Col. 4, lines 17-27, noting that 81 is bonded to 41 – see Figure 4); and
a dielectric layer (51, described as "photo-polyimide layer 51" in Col. 5, lines 10-18) having a first opening (described as an opening to open “window for the main electrode pad 11 in FIG. 3" in Col. 4, lines 56-62; best seen in Figure 3) and a second opening (described as an opening to open “window for gate pad 12 in FIG. 3" in Col. 4, lines 56-62; best seen in Figure 3), the first opening (corresponding to 11) exposing a surface of the first conductive layer (comprising 42), the second opening (corresponding to 12) exposing a surface of the second conductive layer (41).
wherein a material of the surface of the second conductive layer (41, Col. 4, lines 17-27) exposed from the second opening is different from a material (material of 42, described as “tri-metal 42 consisting of layers of titanium, palladium and silver” in Col. 4, lines 28-50) of the surface of the first conductive layer exposed from the first opening, and includes aluminum.
Gould does not specifically state that the second opening (corresponding to 12) has “an opening area smaller than” an opening area of the first opening (corresponding to 11). However, Gould discloses that "main electrode area in pad 11" (Col. 5, lines 34-37) and also describes 80 as "relatively large heat conductive lead 80" with "gate is not a high current carrying structure" and "a simple gated lead 81" can be bonded to "gate bonding pad" - see Col. 5, lines 57- Col. 6, line 3). Further, in Figures 3 and 4, the opening area corresponding to 11 (unlike the opening area corresponding to 12) extends on both sides of the central broken edge parts, also suggesting that opening area corresponding to 11 is larger than that corresponding to 12. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gould so that the second opening (corresponding to 12) has “an opening area smaller than” an opening area of the first opening (corresponding to 11). The ordinary artisan would have been motivated to modify Gould for at least the purpose of providing a larger opening area for the main electrode area pad 11 that enables connection to a "relatively large heat conductive lead 80" that can carry higher current than the smaller gate lead, which thus needs a smaller bonding pad opening area (see Gould, Col. 5, lines 57- Col. 6, line 3).
Regarding claim 3, Gould teaches the semiconductor device according to claim 1, wherein the first conductive layer (comprising 42; i.e. 42, with overlapping part of 41 under it - see Figures 3-4, described as “tri-metal 42” in Col. 4, lines 28-50) includes:
a first layer (41) made of a material including aluminum (Col. 4, lines 28-33);
a second layer made of a material including nickel (“nickel layer” described for 42 in Col. 4, lines 43-47) and arranged on the first layer (41); and
a third layer made of a material including gold and arranged on the second layer (see “gold layer” described for 42 in Col. 4, lines 43-47).
Regarding claim 4, Gould teaches the semiconductor device according to claim 3, wherein the third layer (i.e. “gold layer” described for 42 in Col. 4, lines 43-47) is in contact with (as evidenced by “gold layer” is “then formed atop the nickel” described in Col. 4, lines 43-47) the second layer (i.e. (“nickel layer” described for 42 in Col. 4, lines 43-47).
Regarding claim 5, Gould teaches the semiconductor device according to claim 1, comprising:
a semiconductor substrate (20, described as “substrate 20” of a “power MOSFET” in Col. 3, lines 57-66); and
a first region (region of 42) arranged in the semiconductor substrate, wherein the first conductive layer (comprising 42) is electrically connected to the first region (region of 42).
Gould does not directly state that the first region is “an emitter region or a source region”. However, Gould recognizes a problem in the prior art in that thin aluminum conventionally used as a source contact and source contact pad in a power MOSFET or as the cathode contact and contact pad in an IGBT-type device tends to have relatively high lateral resistance (Col. 1, lines 33-38), and describes overcoming the above limitation by employing a larger/thicker pad (11, described as “main electrode pad 11” in Col. 4, lines 56-62) with which a "relatively large heat conductive lead 80" can be used to achieve relatively low resistance (see Gould, Col. 5, lines 57- Col. 6, line 3).
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gould so that the main electrode pad 11 corresponds to a source; i.e. the first region is a source region. The ordinary artisan would have been motivated to modify Gould for at least the purpose of a design wherein the source region electrode is connected to a "relatively large heat conductive lead 80" that can carry higher current by virtue of having lower electrical resistance (see Gould, Col. 5, lines 57- Col. 6, line 3).
Regarding claim 6, Gould teaches the semiconductor device according to claim 5, comprising:
a gate electrode (12, described as “gate pad 12” in Col. 4, lines 58-61); and
a second region (region of drain) arranged in the semiconductor substrate, the second region being a collector region or a drain region (drain is taught – see Col. 3, lines 49-56 teach that Gould’s device is a “MOSGATE” device; and in Col. 1, lines 10-24, it is taught that MOSGATE devices have not only a “source” but also a “drain”), wherein the second conductive layer (41) is electrically connected to any one of the first region, the gate electrode and the second region (41 is electrically connected to gate electrode corresponding to 12 – see Figure 4 and also see Col. 4, lines 58-61, which describes 12 as “gate pad 12”).
Regarding claim 7, Gould teaches the semiconductor device according to claim 1, wherein the dielectric layer (51) is an organic dielectric layer (51, described as "photo-polyimide layer 51" in Col. 5, lines 10-18, noting that polyimide is an organic dielectric material).
Claim 2 rejected under 35 U.S.C. 103 as being unpatentable over Gould in view of Tonegawa (US 20180138136), hereinafter Tonegawa.
Regarding claim 2, Gould teaches the semiconductor device according to claim 1, comprising:
a solder (70, described as " solder mass 70" in Col. 5, lines 43-59; see Figure 4) connected to the surface of the first conductive layer (42) exposed from the first opening (opening corresponding to 11);
a thick conductor (80, described as “lead 80” in Col. 5, lines 57-66; see Figure 4) electrically connected to the first conductive layer (42) with the solder (70) interposed (see Figure 4) between the first conductive layer (42) and the thick conductor (80); and
a bonding wire (81, shown in Figure 4 and described as "simple gate lead 81" in Col. 5, lines 67 - Col. 6, line 3) directly connected to the surface of the second conductive layer (41) exposed from the second opening (opening corresponding to 12).
Gould does not state that the shape of the thick conductor (80) is such that it is a “plate clip conductor”. However, Gould teaches that the thick conductor (80) is a relatively large heat conductive lead 80 that can carry higher current than the smaller gate lead (see Gould, Col. 5, lines 57- Col. 6, line 3). Further, Tonegawa (US 20180138136) teaches a similar semiconductor device that can carry “large current flows” (para 64) further teaching that a plate clip shaped conductor (described as “metal plate MP” in para 86, with it’s plate clip shape best seen in Figures 5 and 9) is known to be suitable for carrying high current due to it’s lower resistance (para 86; also see para 3, especially last sentence). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gould so that the shape of the thick conductor (80) is suitable for a low resistance connection, such as using a “plate clip conductor”. The ordinary artisan would have been motivated to modify Gould for at least the purpose of using a shape/size conductor with large width and dimensions that result in lower electrical resistance, thus enabling larger current to flow easily.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892