DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-15 in the reply filed on 08/08/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 & 7-15 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Tseng et al. (US Pub. 2021/0359003).
Regarding claim 1, Tseng teaches a method of forming a resistive memory device, the method comprising:
providing a patterned film stack containing a lower electrode layer 116, a dielectric filament layer 206 on the lower electrode layer 116, and an upper electrode layer 1108/120 on the dielectric filament layer 206 (Fig. 10-11);
depositing a conformal cap layer 1202 on the patterned film stack (Fig. 12);
dry etching the conformal cap layer 1202 to form a sidewall spacer 122 on sidewalls of the patterned film stack, where a top of the sidewall spacer 122 is recessed to below a top of the upper electrode layer 1108 by the dry etching (Fig. 12-13 & Para [0056]);
encapsulating the patterned film stack in an isolation layer 107c (Fig. 15); and
etching the isolation layer 107c to expose the upper electrode layer 1108/120 without exposing the sidewall spacer 122 (Fig. 16).
Regarding claim 2, Tseng teaches the method of claim 1, further comprising: following the etching, depositing a metal electrode layer (406 & 408) on the upper electrode layer 120, where the metal electrode layer is not in direct physical contact with the sidewall spacer 122 (Fig. 21).
Regarding claim 3, Tseng teaches the method of claim 1, wherein the dry etching removes the conformal cap layer 1202 from the top surface of the upper electrode layer (Fig. 12-13).
Regarding claim 7, Tseng teaches the method of claim 1, wherein etching the isolation layer includes a planarization process (Fig. 16 & Para [0059]).
Regarding claim 8, Tseng teaches the method of claim 1, wherein etching the isolation layer includes etching a via pattern in the isolation layer (Fig. 4)
Regarding claim 9, Tseng teaches the method of claim 1, wherein the dielectric filament layer includes a metal oxide (Para [0028]).
Regarding claim 10, Tseng teaches the method of claim 9, wherein the metal oxide contains HfOx, ZrOx,TaOx, TiOx, AlOx, or a laminate or mixture thereof (Para [0028-0029]).
Regarding claim 11, Tseng teaches the method of claim 1, wherein the lower electrode layer contains TaN, TiN, W, or a laminate thereof(Para [0026]).
Regarding claim 12, Tseng teaches the method of claim 1, wherein the upper electrode layer contains TaN, TiN, W, or a laminate thereof (Para [0026]).
Regarding claim 13, Tseng teaches the method of claim 1, wherein the conformal cap layer and the sidewall spacer include SiN (Para [0055]).
Regarding claim 14, Tseng teaches the method of claim 1, wherein the isolation layer includes an interlayer dielectric (ILD) (Fig. 15-16).
Regarding claim 15, Tseng teaches the method of claim 1, wherein the dielectric filament layer 206 is in direct physical contact with the lower electrode layer 116, and the upper electrode layer 120 is in direct physical contact with the dielectric filament layer 206(e.g. Fig. 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tseng as applied to claim 1 above, and in further view of Ye et al. (US Patent 5,756,400).
Regarding claim 4, Tseng is silent on the method of claim 1, wherein the dry etching is performed under vacuum conditions without exposing the patterned film stack to oxygen-containing gaseous species. However, Ye teaches wherein dry etching is performed under vacuum conditions without exposing the patterned film stack to oxygen-containing gaseous species. This has the benefits of mitigating potential oxidation of conductive/metal layers (e.g. electrodes). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Tseng with the dry etching process, as taught by Ye, so as to mitigate potential oxidation of electrodes.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tseng and Ye as applied to claim 4 above, and in further view of Hsiao et al. (US Patent 6,074,566).
Regarding claim 5, though the combination of Tseng and Ye is silent on the method of claim 4, wherein the dry etching includes reactive ion etching (RIE). However, RIE is among the most widely known dry etching processes in the semiconductor art. For instance, Hsiao teaches RIE due to its high precision and contamination control characteristics. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Tseng and Ye with the RIE process, as taught by Hsiao, so as to obtain an improved semiconductor device.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Tseng as applied to claim 1 above, and in further view of Kong et al. (US Pub. 2023/0099303).
Regarding claim 6, Tseng is silent on the method of claim 1, wherein an upper part of the sidewalls is exposed during the dry etching. However, Kong teaches a method of forming a semiconductor device, wherein an upper part of a sidewalls is exposed during the dry etching (Fig. 6-7 and Para [0061]). This has the advantages of allowing for formation of a subsequent conductive layer 220 with a larger width than a width of the upper electrode layer 175 (see Fig. 6-7). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Tseng with the sidewall spacer, as taught by Kong, so as to allow for the formation of a subsequent conductive layer.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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