Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yu et al. (US Pat. Pub. 2021/0225756).
Regarding claim 8, Yu teaches semiconductor device comprising a high-voltage isolation capacitor and a mixed-signal integrated circuit [fig. 1, high voltage isolation capacitor 104, mixed signal integrated circuit 106], wherein the high-voltage isolation capacitor comprises:
bottom electrodes, each spaced apart from another, disposed on a substrate [fig. 1, 150];
top electrodes disposed on corresponding ones of the bottom electrodes [fig. 1, 152];
an inter-metal dielectric layer disposed between the bottom electrodes and the top electrodes [fig. 1, 130]; and
a single low bandgap dielectric layer disposed between the bottom electrodes and the top electrodes [fig. 1, 134],
wherein the single low bandgap dielectric layer is absent in the mixed-signal integrated circuit [fig. 1, 134 is absent in circuit area 106].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6, 7, 11-14, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 8 above, and further in view of West et al. (US Pat. Pub. 2016/0172434).
Regarding claim 1, Yu teaches semiconductor device comprising a high-voltage isolation capacitor and a mixed-signal integrated circuit [fig. 1, high voltage isolation capacitor 104, mixed signal integrated circuit 106], wherein the high-voltage isolation capacitor comprises:
bottom electrodes, each spaced apart from another, disposed on a substrate [fig. 1, 150];
top electrodes disposed on corresponding ones of the bottom electrodes [fig. 1, 152];
an inter-metal dielectric layer disposed between the bottom electrodes and the top electrodes [fig. 1, 130]; and
a low bandgap dielectric layer disposed on the inter-metal dielectric layer [fig. 1, 134],
wherein the low bandgap dielectric layer is disposed below corresponding ones of the top electrodes, and the low bandgap dielectric layers are absent in the mixed-signal integrated circuit [fig. 1, 134 is below each 152 and absent in circuit area 106].
While Yu teaches a low bandgap dielectric layer, they fail to teach more than one low bandgap dielectric layer.
However, West teaches a high voltage isolation capacitor with a mixed signal integrated circuit in which multiple layers are used as the low bandgap dielectric layers [fig. 1, capacitor region 104, circuit region 106, low bandgap dielectric layers 142 and 144].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of West into the method of Yu by forming the low bandgap dielectric layer as a plurality of layers. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of providing improved reliability by reducing an electric field at corners of the high voltage node [West, paragraph [0021]].
Regarding claim 2, Yu in view of West discloses the semiconductor device of claim 1, wherein the mixed-signal integrated circuit comprises:
a bottom metal line disposed adjacent the bottom electrodes [Yu, fig. 1, M1 in region 106];
an inter-metal line disposed on the bottom metal line [Yu, fig. 1, M2 in region 106 above M1];
a via connected to the inter-metal line [Yu, fig. 1, V1 between M1 and M2]; and
a top metal line connected with the via [Yu, fig. 1, Mn connected to Vn-1 connected to V2, M2, V1, M1],
wherein the low bandgap dielectric layers are absent below the top metal line [Yu, fig. 1, 134 is not present below Mn].
Regarding claim 3, Yu in view of West teaches the semiconductor device of claim 1, further comprising a passivation layer disposed in direct contact with the low bandgap dielectric layers and the top electrodes [Yu, fig. 1, 160].
Regarding claim 6, Yu in view of West discloses the semiconductor device of claim 1, wherein each of the low bandgap dielectric layers comprises:
A first sub-low bandgap dielectric layer having a first thickness [West, paragraph [0018] 144 can be 200-600nm]; and
A second sub-low bandgap dielectric layer having a second thickness greater than the first thickness [West, paragraph [0018] 142 can be 200-600nm, if 144 is 200nm, and 142 is 600nm, that would anticipate this limitation].
Regarding claim 7, Yu in view of West teaches the semiconductor device of claim 1, wherein each of the low bandgap dielectric layers has a bandgap lower than a bandgap of the inter-metal dielectric layer [West, paragraph [0018] 142/144 has a lower bandgap than intermetal dielectric stack 136].
Regarding claim 11, While Yu teaches a low bandgap dielectric layer, they fail to teach a first and second sub low bandgap dielectric layer making said low bandgap dielectric layer.
However, West teaches a high voltage isolation capacitor with a mixed signal integrated circuit in which multiple sub layers are used to make up the low bandgap dielectric layer [fig. 1, capacitor region 104, circuit region 106, low bandgap dielectric layers 142 and 144].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of West into the method of Yu by forming the low bandgap dielectric layer as a plurality of layers. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of providing improved reliability by reducing an electric field at corners of the high voltage node [West, paragraph [0021]].
Regarding claim 12, Yu discloses a semiconductor device, comprising:
a mixed-signal integrated circuit region [fig. 1, 106]; and
a high-voltage isolation capacitor region [fig. 1, 104], comprising:
bottom electrodes, each spaced apart from another, disposed on a substrate [fig. 1, 150];
top electrodes disposed on corresponding ones of the bottom electrodes [fig. 1, 152];
an inter-metal dielectric layer disposed between the bottom electrodes and the top electrodes [fig. 1, 130]; and
a low bandgap dielectric layer, disposed between corresponding ones of the top electrodes and the inter-metal dielectric layer [fig. 1, 134],
wherein the mixed-signal integrated circuit region comprises a top metal line disposed directly on the inter-metal dielectric layer [fig. 1, Mn directly on 122 of 130].
While Yu teaches a low bandgap dielectric layer, they fail to teach more than one layer making said low bandgap dielectric layers, each of the layers disposed between the top electrode and the inter-metal dielectric.
However, West teaches a high voltage isolation capacitor with a mixed signal integrated circuit in which multiple sub layers are used to make up the low bandgap dielectric layers [fig. 1, capacitor region 104, circuit region 106, low bandgap dielectric layers 142 and 144].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of West into the method of Yu by forming the low bandgap dielectric layer as a plurality of layers. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of providing improved reliability by reducing an electric field at corners of the high voltage node [West, paragraph [0021]].
Regarding claim 13, Yu in view of West discloses the semiconductor device of claim 1, wherein the mixed-signal integrated circuit comprises:
a bottom metal line disposed adjacent the bottom electrodes [Yu, fig. 1, M1 in region 106];
an inter-metal line disposed on the bottom metal line [Yu, fig. 1, M2 in region 106 above M1];
a via connected to the inter-metal line [Yu, fig. 1, V1 between M1 and M2]; and
a top metal line connected with the via [Yu, fig. 1, Mn connected to Vn-1 connected to V2, M2, V1, M1].
Regarding claim 14, Yu in view of West teaches the semiconductor device of claim 12, further comprising a passivation layer disposed in direct contact with the low bandgap dielectric layers and the top electrodes [Yu, fig. 1, 160].
Regarding claim 17, Yu in view of West discloses the semiconductor device of claim 12, wherein each of the low bandgap dielectric layers comprises:
A first sub-low bandgap dielectric layer having a first thickness [West, paragraph [0018] 144 can be 200-600nm]; and
A second sub-low bandgap dielectric layer having a second thickness greater than the first thickness [West, paragraph [0018] 142 can be 200-600nm, if 144 is 200nm, and 142 is 600nm, that would anticipate this limitation].
Regarding claim 18, Yu in view of West teaches the semiconductor device of claim 12, wherein each of the low bandgap dielectric layers has a bandgap lower than a bandgap of the inter-metal dielectric layer [West, paragraph [0018] 142/144 has a lower bandgap than intermetal dielectric stack 136].
Allowable Subject Matter
Claims 4, 5, 9, 10, 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JOHN M PARKER/Examiner, Art Unit 2899