Prosecution Insights
Last updated: April 19, 2026
Application No. 18/188,965

METAL-INSULATOR-METAL (MIM) CAPACITOR INTERCONNECT FOR HIGH-QUALITY (Q) INDUCTOR-CAPACITOR (LC) FILTER

Non-Final OA §103
Filed
Mar 23, 2023
Examiner
ASSOUMAN, HERVE-LOUIS Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
95%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
590 granted / 648 resolved
+23.0% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
42 currently pending
Career history
690
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
54.3%
+14.3% vs TC avg
§102
21.2%
-18.8% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 648 resolved cases

Office Action

§103
Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5-12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2019/0356294 A1) in view of Berdy et al. (US 9,807,882 B1). Regarding independent claim 1: Park teaches (e.g., Fig. 6) a device, comprising: a passive substrate ([0050]: 608) having a first metallization layer ([0050]-[0051]: 603/612) on a first surface of the passive substrate, the first metallization layer comprising a first passive component ([0050]: 603) and a first plate portion ([0051]: 612); an insulator layer ([0051]: 614) coupled to the first plate portion of the first metallization layer; a first conductive interconnect ([0051]: 618) coupled to the insulator layer to form a second passive component ([0051]: capacitor portion 609 may be a metal (612)-insulator (614)-metal (618) (MIM) capacitor) coupled to the first passive component (inductor 603); Park does not expressly teach a laminate substrate coupled to the first conductive interconnect. Berdy teaches (e.g., Fig. 3) a device comprising a laminate substrate (Col. 7, Lines 61-67 and Col. 8, Lines 1-5: #310/302) coupled to a conductive interconnect (Col. 8, Lines 4-18: #350/332/340). Note that Fig. 2 shows that passive devices layer 232 includes inductor and capacitor (Col. 6, Lines 60-37: inductors (L) and capacitors (C)). It would have been obvious to a person of ordinary skill at the time of the effective filing date to include in the device of Park, the laminate substrate coupled to the first conductive interconnect, as taught by Berdy, for the benefits of increasing the device density and integrating more device for more power and functionalities. Regarding claim 2: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the second passive component comprises: a metal-insulator-metal (MIM) capacitor (Park: [0051]: capacitor portion 609 may be a metal (612)-insulator (614)-metal (618) (MIM) capacitor), comprising: the first plate portion of the first metallization layer; (Park: [0051]: capacitor portion 609 includes first plate portion of the first metallization layer (612)) the insulator layer (Park: [0051]: capacitor portion 609 includes insulator (614)) directly on the first plate portion of the first metallization layer (Park: [0051]: (612)); and the first conductive interconnect (Park: [0051]: (618)) having a first surface directly (Park: upper surface) on the insulator layer; Par as modified by Berdy teach that a second surface (Park: bottom surface) coupled to a conductive trace on the laminate substrate (Berdy: Col. 7, Lines 61-67 and Col. 8, Lines 1-5: #310/302). Regarding claim 5: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the second passive component comprises a metal-insulator-metal (MIM) capacitor (Park: [0051]: capacitor portion 609 may be a metal (612)-insulator (614)-metal (618) (MIM) capacitor) and the first passive component comprises a 2D inductor (Park: inductor 609 is a 2D although directly stated for Fig. 6; see [0041], [0047]-[0048]). Regarding claim 6: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the first conductive interconnect comprises a copper (Cu) pillar (Park: [0028] and [0034]). Regarding claim 7: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the first conductive interconnect comprises a copper (Cu) via (Park: [0028] and [0032]). Regarding claim 8: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the laminate substrate comprises a printed circuit board (PCB) having a PCB trace (Berdy: Col. 7, Lines 61-67 and Col. 8, Lines 1-5: #310/302) coupled to the first conductive interconnect. Regarding claim 9: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the passive substrate comprises glass (Park: [0051]: passive substrate 608 comprises glass). Regarding claim 10: Park and Berdy teach the claim limitation of the device of claim 1, on which this claim depends, in which the device comprises a radio frequency (RF) inductor-capacitor (LC) filter (Park: [0009], [0028] and [0049]). Regarding claim 11: Park and Berdy teach the claim limitation of the device of claim 10, on which this claim depends, in which the RF LC filter is incorporated in a radio frequency front-end (RFFE) module (Park: [0009], [0028] and [0049]: RF LC filter is incorporated in a radio frequency front-end (RFFE) module expresses an intended use). Applicant is reminded that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim Regarding independent claim 12: Park teaches (e.g., Fig. 6) a method for fabricating a radio frequency (RF) device, comprising: forming a first metallization layer ([0050]-[0051]: 603/612) on a first surface of a passive substrate ([0050]: 608), the first metallization layer comprising a first passive component ([0050]: 603) and a first portion ([0051]: 612); depositing an insulator layer ([0051]: 614) on the first plate portion of the first metallization layer; forming a first conductive interconnect ([0051]: 618) coupled to the insulator layer to form a second passive component ([0051]: capacitor portion 609 may be a metal (612)-insulator (614)-metal (618) (MIM) capacitor) coupled to the first passive component (inductor 603). Park does not expressly teach plating and coupling a laminate substrate to the first conductive interconnect. Berdy teaches (e.g., Fig. 3) a method comprising plating (Col. 4, Lines 40-44) and coupling a laminate substrate (Col. 7, Lines 61-67 and Col. 8, Lines 1-5: #310/302) coupled to a conductive interconnect (Col. 8, Lines 4-18: #350/332/340). Note that Fig. 2 shows that passive devices layer 232 includes inductor and capacitor (Col. 6, Lines 60-37: inductors (L) and capacitors (C)). It would have been obvious to a person of ordinary skill at the time of the effective filing date to include in the method of Park, the method of plating and coupling a laminate substrate to the first conductive interconnect, as taught by Berdy, for the benefits of increasing the device density and integrating more device for more power and functionalities. Regarding claim 18: Park and Berdy teach the claim limitation of the method of claim 12, on which the claim depends, in which the passive substrate comprises glass (Park: [0051]: passive substrate 608 comprises glass). Regarding claim 19: Park and Berdy teach the claim limitation of the method of claim 12, on which the claim depends, in which the RF device comprises an RF inductor-capacitor (LC) filter (Park: [0009], [0028] and [0049]). Regarding claim 20: Park and Berdy teach the claim limitation of the method of claim 19, on which the claim depends, in which the RF LC filter is incorporated in a radio frequency front-end (RFFE) module (Park: [0009], [0028] and [0049]: RF LC filter is incorporated in a radio frequency front-end (RFFE) module expresses an intended use). Applicant is reminded that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Allowable Subject Matter Claims 3-4 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a device comprising “further comprising a second conductive interconnect having a first surface directly coupled to the first conductive interconnect, and a second surface coupled to the conductive trace on the laminate substrate”. Regarding claim 4: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a device comprising: “the insulator layer directly on a portion of a first surface of the second metallization layer, opposite the second conductive interconnect; and the first conductive interconnect having a first surface directly on the insulator layer and a second surface coupled to a conductive trace on the laminate substrate”. Regarding claim 13: a method for fabricating a radio frequency (RF) device, comprising: “forming via openings in interlayer dielectric (ILD) layers on the passive substrate to expose the insulator layer as well as a second plate portion of the first metallization layer; and forming a first via on the insulator layer, and a second via on the second plate portion of the first metallization layer. Claims 14-17 depend from claim 13, and therefore, are allowable for the same reason as claim 13. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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Prosecution Timeline

Mar 23, 2023
Application Filed
Aug 23, 2025
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
95%
With Interview (+4.1%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 648 resolved cases by this examiner. Grant probability derived from career allow rate.

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