DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of II in the reply filed on 3/11/2026 is acknowledged. The traversal is on the ground(s) that the process claim 21 cannot be used to make another materially different product and the device in claim 1 cannot be made by another material different process than the process of claim 21.
After thoroughly consideration, Examiner agrees with Applicant’s argument on claim 21. Claim 21 will be examined together with other claims. However, claims 22-23 remain withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 12-13, 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “wherein the first portion second side and the second portion second side extend along a third axis in the first direction”. Claim 3 is dependent on claim 1. But the terms “first portion second side” and “second portion second side” are defined in claim 2, not claim 1. So it is unclear whether claim 3 is dependent on claim 1 or claim 2. For the purpose of examination, it is interpreted to be dependent on claim 2.
Claim 12 recites “a third gate disposed along the fourth axis in the second direction on the diffusion region adjacent to the first gate second side”. Claim 12 is dependent on claim 10, which defines the fourth axis “adjacent to the first gate first side”. Since first gate first side is on opposite side as the first gate second side, it is unclear how the “fourth axis” can be on both sides of the first gate. For the purpose of examination, the phrase “along the fourth axis in the second direction” is interpreted as “parallel to the fourth axis in the second direction”.
Claim 13 is dependent on claim 12 and inherits the same indefiniteness issue.
Claim 24 recites “a substrate” in lines 2 and 4. It is unclear whether the “substrate” in line 4 is the same or different than the “substrate” defined in line 2. For the purpose of examination, it is interpreted to be the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 19-21, 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stolmeijer et al. (US 5654915).
Regarding claim 1, Stolmeijer teaches a row cell circuit (6T cell Fig. 7 of Stolmeijer), comprising:
a diffusion region (active layer 51 in Fig. 7 of Stolmeijer) on a substrate (substrate of the cell), the diffusion region comprising a first diffusion region portion (portion of 51 immediately above the gate 26g as viewed in Fig. 7; this is the source/drain region of the transistor 26 as described in column 6 lines 57-65 of Stolmeijer) and a second diffusion region portion (portion of 51 below gate 26g and above gate 22g as viewed in Fig. 7), each disposed along a first axis (axis of bitline 35) in a first direction (up-down direction), wherein:
the first diffusion region portion and the second diffusion region portion intersect along a second axis (axis of the gate 26g) in a second direction (left-right direction in Fig. 7) orthogonal to the first direction;
the first diffusion region portion has a first width (width of the S/D region of transistor 26) in the second direction; and the second diffusion region portion has a second width greater than the first width in the second direction (as shown in Fig. 7, the wider width of the S/D region of transistor 22 is greater than the width of the upper S/D region of the transistor 26); and
a first gate (26g) disposed along the second axis on the diffusion region, wherein the first gate comprises a first gate first side (upper side of 26g) on the first diffusion region portion and a first gate second side (lower side of 26g) on the second diffusion region portion.
Regarding claim 2, Stolmeijer teaches all limitations of the row cell circuit of claim 1, and also teaches wherein: the first diffusion region portion comprises a first portion first side (right side of first portion, as viewed in Fig. 7 of Stolmeijer) and a first portion second side (left side of first portion), each orthogonal to the first gate first side (as shown in Fig. 7 of Stolmeijer); and the second diffusion region portion comprises a second portion first side (right side of second portion) and a second portion second side (left side of second portion), each orthogonal to the first gate second side (as shown in Fig. 7 of Stolmeijer).
Regarding claim 3, Stolmeijer teaches all limitations of the row cell circuit of claim 1, and also teaches wherein the first portion second side and the second portion second side extend along a third axis (axis of left edge of active region 51 in Fig. 7 of Stolmeijer) in the first direction (as shown in Fig. 7 of Stolmeijer).
Regarding claim 4, S-tolmeijer teaches all limitations of the row cell circuit of claim 2, and also teaches wherein the second diffusion region portion further comprises a second portion end (lower S/D region of transistor 26 in Fig. 27 of Stolmeijer) disposed along the second axis, wherein the second portion end of the second diffusion region portion is orthogonal to the first portion first side of the first diffusion region portion (as defined in claim 1 above, the second axis is that of the gate 26g which is orthogonal to the right side of the first portion).
Regarding claim 5, Stolmeijer teaches all limitations of the row cell circuit of claim 4, and also teaches wherein the second portion first side is orthogonal to the second portion end (as defined in claims 1 and 4 above, the second axis is that of the gate 26g which is orthogonal to the left side of the first portion).
Regarding claim 6, Stolmeijer teaches all limitations of the row cell circuit of claim 1, and also teaches wherein the first gate comprises a dummy gate (the term “dummy” gate is either intended use of the gate or functional property of the gate. Intended use carries no patentable weight while functional property only requires that the gate is capable of being a dummy gate, which it certainly is capable of).
Regarding claim 19, Stolmeijer teaches all limitations of the row cell circuit of claim 1 integrated into an integrated circuit (IC) (as stated in Abstract of Stolmeijer).
Regarding claim 20, Stolmeijer teaches all limitations of the row cell circuit of claim 1, and also integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer (as described in the Background of the Invention in column 1); a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Regarding claim 21, Stolmeijer teaches a method of fabricating a row cell circuit, comprising:
forming a diffusion region (active layer 51 in Fig. 7 of Stolmeijer) on a substrate (substrate of the cell), the diffusion region comprising a first diffusion region portion (portion of 51 immediately above the gate 26g as viewed in Fig. 7; this is the source/drain region of the transistor 26 as described in column 6 lines 57-65 of Stolmeijer) and a second diffusion region portion (portion of 51 below gate 26g and above gate 22g as viewed in Fig. 7), each disposed along a first axis (axis of bitline 35) in a first direction (up-down direction), wherein forming the diffusion region on the substrate further comprises:
forming the first diffusion region portion and the second diffusion region portion intersecting along a second axis (axis of the gate 26g) in a second direction (left-right direction in Fig. 7) orthogonal to the first direction;
forming the first diffusion region portion having a first width (width of the S/D region of transistor 26) in the second direction; and
forming the second diffusion region portion having a second width (as shown in Fig. 7, the wider width of the S/D region of transistor 22 is greater than the width of the upper S/D region of the transistor 26) greater than the first width in the second direction; and
forming a first gate (26g) along the second axis on the diffusion region, wherein the first gate comprises a first gate first side (upper side of 26g) on the first diffusion region portion and a first gate second side (lower side of 26g) on the second diffusion region portion.
Regarding claim 24, Stolmeijer teaches an integrated circuit (IC) comprising:
a logic circuit (the memory circuit comprising the 6T cells in Fig. 5a/b and Fig. 7 of Stolmeijer) disposed on a substrate (substrate of the cell), the logic circuit comprising a plurality of row cell circuits (rows of 6T cells in Fig. 5a/b), each row cell circuit (cell in Fig. 7) comprising:
a diffusion region (active layer 51 in Fig. 7 of Stolmeijer) on a substrate (please see the 112b rejection above), the diffusion region comprising a first diffusion region portion (portion of 51 immediately above the gate 26g as viewed in Fig. 7; this is the source/drain region of the transistor 26 as described in column 6 lines 57-65 of Stolmeijer) and a second diffusion region portion (portion of 51 below gate 26g and above gate 22g as viewed in Fig. 7), each disposed along a first axis (axis going through the left edge of the active region 51) in a first direction (up-down direction in Fig. 7), wherein:
the first diffusion region portion and the second diffusion region portion intersect along a second axis (axis of the gate 26g) in a second direction (left-right direction) orthogonal to the first direction;
the first diffusion region portion has a first width (width of the S/D region of transistor 26) in the second direction; and
the second diffusion region portion has a second width greater than the first width in the second direction (as shown in Fig. 7, the wider width of the S/D region of transistor 22 is greater than the width of the upper S/D region of the transistor 26); and
a first gate (26g) disposed along the second axis on the diffusion region, wherein the first gate comprises a first gate first side (upper side of 26g) on the first diffusion region portion and a first gate second side (lower side of 26g) on the second diffusion region portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Stolmeijer, and further in view of Guha et al. (US 2019/0393352 A1).
Regarding claim 7, Stolmeijer teaches all limitations of the row cell circuit of claim 6, but does not teach further comprising a nanosheet disposed within the first gate and above the diffusion region in a vertical direction orthogonal to the first direction and the second direction.
Guha teaches a nanowire device (Fig. 5 of Guha) wherein the silicon channel region are made of nanosheets (512A/B in Fig. 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel regions of the transistors nanosheets, as disclosed by Guha, in order to increase gate-channel interface and device density.
As incorporated, the active region 50/51 of Stolmeijer would be formed as nanosheets and have the same width pattern as the initial regions 50/51 shown in Fig. 7 of Stolmeijer.
Regarding claim 8, Stolmeijer in view of Guha teaches all limitations of the row cell circuit of claim 7, and also teaches wherein the nanosheet comprises: a first nanosheet portion (channel of transistor 26 of Stolmeijer) having the first width (as combined in claim 7 above); a second nanosheet portion (channel of transistor 22 of Stolmeijer) having the second width (as combined in claim 7 above); and a right-angle corner (corner shown in Fig. 7 of Stolmeijer in the region between two gates 26g and 22g) between the first nanosheet portion and the second nanosheet portion.
Regarding claim 9, Stolmeijer in view of Guha teaches all limitations of the row cell circuit of claim 7, and also teaches wherein the nanosheet comprises a same material as the diffusion region (the nanosheets are made of silicon, as stated in [0049] of Guha).
Regarding claim 18, Stolmeijer teaches all limitations of the row cell circuit of claim 2, but does not teach wherein the first portion first side, the first portion second side, the second portion first side, and the second portion second side comprise surfaces extending in a vertical direction orthogonal to the first direction and the second direction.
Guha teaches a nanowire device (Fig. 5 of Guha) wherein the silicon channel region are made of nanosheets (512A/B in Fig. 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel regions of the transistors nanosheets, as disclosed by Guha, in order to increase gate-channel interface and device density.
As incorporated, the active region 50/51 of Stolmeijer would be formed as nanosheets and have the same width pattern as the initial regions 50/51 shown in Fig. 7 of Stolmeijer. The sidewalls of these nanosheets are surfaces that are orthogonal to the first and second directions.
Claims 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Stolmeijer, as applied to claim 2 above, and further in view of Blatchford et al. (US 2013/0069081 A1) and Guha.
Regarding claim 10, Stolmeijer teaches all limitations of the row cell circuit of claim 2, but does not teach the row cell circuit further comprising: a second gate disposed along a fourth axis in the second direction on the diffusion region adjacent to the first gate first side, wherein the second gate comprises a second gate first side and a second gate second side; and a first nanosheet disposed between the second gate first side and the second gate second side.
Blatchford teaches a device structure (Fig. 2B of Blatchford). The device comprises: a first active gate (middle two gates in Fig. 2B of Blatchford); a dummy gate (30, as labeled in Fig. 1) on ends of active region and surrounding the active gates to improve patterning of the gates (see [0003] of Blatchford).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed dummy gates at the boundary of active regions of Stolmeijer in order to improve patterning of the gates (see [0003] of Blatchford).
As incorporated, one dummy gate 30 of Blatchford would be formed above the gate 26g as viewed in Fig. 7 of Stolmeijer, i.e. adjacent to the first gate first side. This dummy gate 30 of Blatchford also covers the end of the first diffusion region portion above the gate 26g. In other words, the end of the first diffusion region portion of transistor 26 would be between the upper side of the second gate (defined as second gate first side) and the lower side of the second gate (defined as second gate second side).
But Stolmeijer in view of Blatchford does not teach that the row cell circuit comprising: a first nanosheet disposed between the second gate first side and the second gate second side.
Guha teaches a nanowire device (Fig. 5 of Guha) wherein the silicon channel region are made of nanosheets (512A/B in Fig. 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel regions of the transistors nanosheets, as disclosed by Guha, in order to increase gate-channel interface and device density.
As incorporated, the active region of Stolmeijer would be formed as nanosheets and have the same width pattern as the initial regions shown in Fig. 7 of Stolmeijer. An end of the first nanosheet also disposed between the first and second sides of the second gate.
Regarding claim 11, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 10, and also teaches wherein the nanosheet has the first width in the second direction (as combined in claim 10 and shown in Fig. 7 of Stolmeijer).
Regarding claim 12, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 10, and further comprising: a third gate (22g in Fig. 7 of Stolmeijer) disposed along the fourth axis (please see interpretation in 112b rejection above) in the second direction on the diffusion region adjacent to the first gate second side, the third gate comprising: a third gate first side (upper side of gate 22g); a third gate second side (lower side of gate 22g); and a second nanosheet (wider nanosheets as incorporated in claim 10 above) disposed between the third gate first side and the third gate second side.
Regarding claim 13, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 12, and also teaches wherein the second nanosheet has the second width in the second direction (as combined in claim 10 above).
Regarding claim 14, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 10, and also teaches wherein:
the first diffusion region portion extends between the first gate first side and the second gate second side (as combined in claim 10, the upper source/drain region of the transistor 26 as viewed in Fig. 7 of Stolmeijer is between the upper side of the gate 26g and the dummy gate 30); and
the first portion first side and the first portion second side are each orthogonal to the first gate first side and the second gate second side (as incorporated in claim 10).
Regarding claim 15, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 10, and further comprising a first source/drain region (the S/D region of gate 26g in Fig. 7 of Stolmeijer) disposed between the first gate and the second gate on the first diffusion region portion, the first source/drain region electrically coupled to the first nanosheet (as combined in claim 10).
Regarding claim 16, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 12, and also teaches wherein: the second diffusion region portion extends between the first gate second side and the third gate first side (as defined in claim 1 above); and the second portion first side and the second portion second side are each orthogonal to the first gate second side and the third gate first side (as combined in claim 12).
Regarding claim 17, Stolmeijer-Blatchford-Guha teaches all limitations of the row cell circuit of claim 12, and further comprising a second source/drain region (as taught in claim 1 above) disposed between the first gate second side and the third gate first side on the second diffusion region portion, the second source/drain region electrically coupled to the second nanosheet (as combined in claim 12 above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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