CTFR 18/189,185 CTFR 99016 DETAILED ACTION Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on 12/24/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification Amendment to Specification filed on 01/21/2026 has been considered and entered. Response to Amendment Amendments to Claim(s) 1, 11, 13, and 15 have been considered for examination based on their merits. The original Claim(s) 2-10, 14, and 16-21 have been considered. The Claim(s) 22-25 have been previously withdrawn by the Applicant. Currently Amended but previously withdrawn Claim 22 has not been considered for further Examination in this Office Action. Claim 12 is canceled. Response to Arguments 07-38-02 AIA Applicant’s arguments, see Remarks, pages 10-12 , filed 01/21/2026 , with respect to the rejection(s) of claim(s) 1, 3, and 15, under 35. U.S.C. 102(a)(1) and claim(s) 1-21 , under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of YINIAN and CHENG . Regarding Independent Claim(s) 1 and 15. Applicant argues (see Remarks, page 11), that TSAI and YOUNG both individually and in combination does not disclose or suggest all of the amended features to claim(s) 1 and 5. The Examiner agrees with the arguments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of YINIAN and CHENG. For instance, YINIAN teaches a semiconductor structure (Fig. 1, 10, wafer) , comprising: wherein at least two of the plurality of mandrel structures (Fig. 1, 30) are separated by a distance in a range of 50 nanometers to 2000 nanometers (Fig. 1, the width of a mandrel, W1 = 5-20 nm; The spacing between adjacent mandrels ~ (2.5-4) times the width, W1; (i.e.) 2.5 x 20 nm – 4 x 20 nm = 50 nm – 80 nm [0021]) . CHENG teaches a semiconductor structure (Fi. 15, patterning structure, [0006]) , comprising: wherein at least one of the plurality of mandrel structures (Fig. 15, 106) includes: a first side (annotated Figure 15) including a first graded semiconductor material (Fig. 15, 108, undoped spacers; formed from an undoped semiconductor material, [0028]) a second side (annotated Figure 15) including a second graded semiconductor material (Fig. 15, 1502, doped spacers; boron doped undoped spacers, 108 or boron doped undoped semiconductor material, [0049]) , and a sidewall spacer (annotated Figure 15) vertically separating the first side (annotated Figure 15) from the second side (annotated Figure 15) . PNG media_image1.png 603 826 media_image1.png Greyscale Regarding Claim(s) 2-11, and 13-21. The claims 2-11, and 13-21 depends on the independent claim(s) 1 and 15, and therefore follows the similar discussions mentioned above . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-3, 5-11, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tzung-Yi Tsai et al, (hereinafter TSAI), US 20190067020 A1, (prior art used in the previous Office Action), in view of Michael Y. Young et al, (hereinafter YOUNG), US 20220057710 A1 (prior art used in the previous Office Action), Su Yinian et al, (hereinafter YINIAN), CN 113948452 A, and Kangguo Cheng, (hereinafter CHENG), US 20210090889 A1 . Regarding Claim 1 , TSAI teaches a semiconductor structure (Fig. 4, 200, semiconductor device) , comprising: a plurality of mandrel structures (Fig. 4, 304, mandrels patterned from 302, mandrel layer, [0025]) disposed above and in contact with a substrate (Fig. 4, 202) . TSAI does not explicitly disclose a semiconductor structure, comprising: each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees, and a template structure for an imprint mask formed by the plurality of mandrel structures. YOUNG teaches a semiconductor structure (Fig. 3, 300 PDMS stamp) , comprising: each of the plurality of mandrel structures (Fig. 3, 300, slanted fin grating stamp, [0040]) extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees (annotated Figure 3, step 8) , and a template structure for an imprint mask formed by the plurality of mandrel structures (Fig. 3, step 8, the imprint substrate now has imprinted pattern on its surface, [0040]) . PNG media_image2.png 707 755 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified TSAI to incorporate the teachings of YOUNG, such that the semiconductor structure, further comprising: each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees, and a template structure for an imprint mask formed by the plurality of mandrel structures. The slanted fin grating features save materials’ cost by avoiding residual thickness layer RTL necessary for imprinting while enhancing the accuracy of the placement of details from the PDMS stamp (YOUNG, Figs. 6-11, [0003]) . TSAI as modified by YOUNG does not explicitly disclose a semiconductor structure, comprising: wherein at least two of the plurality of mandrel structures are separated by a distance in a range of 50 nanometers to 2000 nanometers. YINIAN teaches a semiconductor structure (Fig. 1, 10, wafer) , comprising: wherein at least two of the plurality of mandrel structures (Fig. 1, 30) are separated by a distance in a range of 50 nanometers to 2000 nanometers (Fig. 1, the width of a mandrel, W1 = 5-20 nm; The spacing between adjacent mandrels ~ (2.5-4) times the width, W1; (i.e.) 2.5 x 20 nm – 4 x 20 nm = 50 nm – 80 nm [0021]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have TSAI as modified by YOUNG to incorporate the teachings of YINIAN, such that a semiconductor structure, comprising: wherein at least two of the plurality of mandrel structures are separated by a distance in a range of 50 nanometers to 2000 nanometers, so that as the device dimension decrease metal lines and vias also becomes smaller to form functional miniaturized circuits (YINIAN, [0002]) . TSAI as modified by YOUNG and YINIAN does not explicitly disclose a semiconductor structure, comprising: wherein at least one of the plurality of mandrel structures includes: a first side including a first graded semiconductor material, a second side including a second graded semiconductor material, and a sidewall spacer vertically separating the first side from the second side. CHENG teaches a semiconductor structure (Fig. 15, patterning structure, [0006]) , comprising: wherein at least one of the plurality of mandrel structures (Fig. 15, 106) includes: a first side (annotated Figure 15) including a first graded semiconductor material (Fig. 15, 108, undoped spacers; formed from an undoped semiconductor material, [0028]) a second side (annotated Figure 15) including a second graded semiconductor material (Fig. 15, 1502, doped spacers; boron doped undoped spacers, 108 or boron doped undoped semiconductor material, [0049]) , and a sidewall spacer (annotated Figure 15) vertically separating the first side (annotated Figure 15) from the second side (annotated Figure 15) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have TSAI as modified by YOUNG and YINIAN to incorporate the teachings of CHENG, such that a semiconductor structure, comprising: wherein at least one of the plurality of mandrel structures includes: a first side including a first graded semiconductor material, a second side including a second graded semiconductor material, and a sidewall spacer vertically separating the first side from the second side, so that selective removal or providing for the etch selectivity of the undoped versus doped spacer is conveniently facilitated during the patterning process of the semiconductor structure (CHENG, [0036], [0045]) . PNG media_image1.png 603 826 media_image1.png Greyscale Regarding Claim 2 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 1. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , further comprising: a layer of a conformal dielectric material (Fig. 4, 402, a material layer, may include amorphous silicon, silicon oxide, silicon oxynitrde, etc., [0025-0026]) covering the plurality of mandrel structures (Fig. 4, 304, mandrels, [0025]) , the layer of conformal dielectric material providing stability and uniformity (Fig. 4, the thickness of the material layer, 402 is about 2 nm, [0026]) to the plurality of mandrel structures (the width of the mandrels, 304 is substantially uniform, [0022]) . Regarding Claim 3 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 1. YOUNG further teaches the semiconductor structure (Fig. 3, 300 PDMS stamp) , wherein each of the plurality of mandrel structures has a similar inclination angle (Fig. 3, 300, slanted fin grating stamp, [0040]) with respect to the substrate (Fig. 3, step 8, the imprint substrate now has imprinted pattern on its surface, [0040]) . Regarding Claim 5 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 1. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein each of the plurality of mandrel structures (Fig. 4, 304, mandrels, [0025]) includes a semiconductor material (Fig. 4, 402, a material layer, may include amorphous silicon, [0025-0026]) . Regarding Claim 6 TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 5. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein the semiconductor material (Fig. 4, 304, mandrels includes a 402, a material layer, may include amorphous silicon, [0025-0026]) includes boron-doped silicon (amorphous silicon (a-Si) doped with boron, [0028]) . Regarding Claim 7 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 5. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein a width of each of the plurality of mandrel structures is determined by a depth of an angled ion implantation (Fig. 6, the mandrels, 304 in the 206 have a larger width than the mandrels, 304 in the 204 region by at least the extra thickness of the doped material layer, 402, selectively etched by other etching methods; the impurity, 501 may be doped into the material layer, 402 through an implantation process, [0027-0030]) . Regarding Claim 8 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 5. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein the semiconductor material (Fig. 4, 304, mandrels includes a 402, a material layer, may include amorphous silicon, [0025-0026]) includes an epitaxially grown material (Fig. 6, 208, epitaxial semiconductor layer; the doped material layer, the pattern in the mandrels 304 covered materials layer, 402 is transferred to the epitaxial semiconductor layer, 208 to define the fins [0030]) . Regarding Claim 9 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 8. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein the epitaxially grown material (Fig. 6, 208, epitaxial semiconductor layer, [0030]) includes silicon-germanium ([0034]; a fin for a p-type FinFET may include silicon germanium (SiGe), [0009]) . Regarding Claim 10 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 8. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein the epitaxially grown material includes silicon (a fin for an n-type FinFET may include silicon (Si), [0009]) . Regarding Claim 11 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 8. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , wherein a width of each of the plurality of mandrel structures is determined by a width of the epitaxially grown material (Fig. 7, W1/W2, width of 304/210, mandrel/patterned hard mask structure, [0032]) . Regarding Claim 15 , TSAI teaches a method of forming a semiconductor structure (Figs. 1A-1B, method of forming a semiconductor device, [0005]) , comprising: forming a plurality of mandrel structures (Fig. 4, 304, mandrels patterned from 302, mandrel layer, [0025]) disposed above and in contact with a substrate (Fig. 4, 202) . TSAI does not explicitly disclose a method of forming a semiconductor structure, comprising: each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees, the plurality of mandrel structures providing a template structure for an imprint mask formed by the plurality of mandrel structures. YOUNG teaches a method of forming a semiconductor structure (Fig. 2, 200, fabrication method for a PDMS stamp) , comprising: each of the plurality of mandrel structures (Fig. 3, 300, slanted fin grating stamp, [0040]) extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees (annotated Figure 3, step 8) , the plurality of mandrel structures providing a template structure for an imprint mask (Fig. 3, step 8, the imprint substrate now has imprinted pattern on its surface, [0040]) . PNG media_image2.png 707 755 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified TSAI to incorporate the teachings of YOUNG, such that a method of forming a semiconductor structure, comprising: each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees, the plurality of mandrel structures providing a template structure for an imprint mask formed by the plurality of mandrel structures. The slanted fin grating features save materials’ cost by avoiding residual thickness layer RTL necessary for imprinting while enhancing the accuracy of the placement of details from the PDMS stamp (YOUNG, Figs. 6-11, [0003]) . TSAI as modified by YOUNG does not explicitly disclose a method of forming a semiconductor structure, comprising: wherein at least two of the plurality of mandrel structures are separated by a distance in a range of 50 nanometers to 2000 nanometers. YINIAN teaches a method of forming a semiconductor structure (Fig. 21, 200, process flow) , comprising: wherein at least two of the plurality of mandrel structures (Fig. 1, 30) are separated by a distance in a range of 50 nanometers to 2000 nanometers (Fig. 1, the width of a mandrel, W1 = 5-20 nm; The spacing between adjacent mandrels ~ (2.5-4) times the width, W1; (i.e.) 2.5 x 20 nm – 4 x 20 nm = 50 nm – 80 nm [0021]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have TSAI as modified by YOUNG to incorporate the teachings of YINIAN, such that a method of forming a semiconductor structure, comprising: wherein at least two of the plurality of mandrel structures are separated by a distance in a range of 50 nanometers to 2000 nanometers, so that as the device dimension decrease metal lines and vias also becomes smaller to form functional miniaturized circuits (YINIAN, [0002]) . TSAI as modified by YOUNG and YINIAN does not explicitly disclose a method of forming a semiconductor structure, comprising: wherein at least one of the plurality of mandrel structures includes: a first side including a first graded semiconductor material, a second side including a second graded semiconductor material, and a sidewall spacer vertically separating the first side from the second side. CHENG teaches a method of forming a semiconductor structure (Fig. 15, patterning method, [0005]) , comprising: wherein at least one of the plurality of mandrel structures (Fig. 15, 106) includes: a first side (annotated Figure 15) including a first graded semiconductor material (Fig. 15, 108, undoped spacers; formed from an undoped semiconductor material, [0028]) a second side (annotated Figure 15) including a second graded semiconductor material (Fig. 15, 1502, doped spacers; boron doped undoped spacers, 108 or boron doped undoped semiconductor material, [0049]) , and a sidewall spacer (annotated Figure 15) vertically separating the first side (annotated Figure 15) from the second side (annotated Figure 15) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have TSAI as modified by YOUNG and YINIAN to incorporate the teachings of CHENG, such that a method of forming a semiconductor structure, comprising: wherein at least one of the plurality of mandrel structures includes: a first side including a first graded semiconductor material, a second side including a second graded semiconductor material, and a sidewall spacer vertically separating the first side from the second side, so that selective removal or providing for the etch selectivity of the undoped versus doped spacer is conveniently facilitated during the patterning process of the semiconductor structure (CHENG, [0036], [0045]) . PNG media_image1.png 603 826 media_image1.png Greyscale Regarding Claim 16 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the method of claim 15. TSAI further teaches the semiconductor structure (Fig. 4, 200, semiconductor device) , further comprising: forming a layer of a conformal dielectric material (Fig. 4, 402, a material layer, may include amorphous silicon, silicon oxide, silicon oxynitrde, etc., [0025-0026]) covering the plurality of mandrel structures (Fig. 4, 304, mandrels, [0025]) , the layer of conformal dielectric material providing stability and uniformity (Fig. 4, the thickness of the material layer, 402 is about 2 nm, [0026]) to the plurality of mandrel structures (the width of the mandrels, 304 is substantially uniform, [0022]) . Regarding Claim 17 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the method of claim 15. YOUNG further teaches the method (Fig. 2, 200, fabrication method for a PDMS stamp) of claim 1, wherein each of the plurality of mandrel structures has a similar inclination angle (Fig. 3, 300, slanted fin grating stamp, [0040]) with respect to the substrate (Fig. 3, step 8, the imprint substrate now has imprinted pattern on its surface, [0040]) . Claim(s) 4 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable TSAI, in view of YOUNG, YINIAN and CHENG as applied to claim(s) 1-3, 5-11, and 15-17 above, and further in view of Kuei-Lun Lin et al, (hereinafter LIN), US 20220246433 A1. Regarding Claim 4 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 1. TSAI as modified by YOUNG, YINIAN and CHENG does not explicitly disclose teaches the semiconductor structure, wherein each of the plurality of mandrel structures has a different inclination angle with respect to the substrate. LIN teaches the semiconductor structure (Fig. 1, FinFET) , wherein each of the plurality of mandrel (Figs. 2/18A, 54/68, mandrels/channel region in 50P/50N, type region, [0019]) structures has a different inclination angle with respect to the substrate (Figs. 15A/18A, 68, channel region; upper portion of the fins, 62 form angle Theta1 with the sidewalls of the lower portion of the fins, 62, [0048]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified TSAI as modified by YOUNG, YINIAN and CHENG to incorporate the teachings of LIN, such that the semiconductor structure, wherein each of the plurality of mandrel structures has a different inclination angle with respect to the substrate, so that to fabricate semiconductor devices with minimal size features that allow more components to be integrated into a given area or simply to increase the integration density (LIN, [0001]) . Regarding Claim 18 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the method of claim 15. TSAI as modified by YOUNG, YINIAN and CHENG does not explicitly disclose teaches the method, wherein each of the plurality of mandrel structures has a different inclination angle with respect to the substrate. LIN teaches the method (Figs. 10A-22B, manufacturing of FinFETs, [0006]) , wherein each of the plurality of mandrel (Figs. 2/18A, 54/68, mandrels/channel region in 50P/50N, type region, [0019]) structures has a different inclination angle with respect to the substrate (Figs. 15A/18A, 68, channel region; upper portion of the fins, 62 form angle Theta1 with the sidewalls of the lower portion of the fins, 62, [0048]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified TSAI as modified by YOUNG, YINIAN and CHENG to incorporate the teachings of LIN, such that the semiconductor structure, wherein each of the plurality of mandrel structures has a different inclination angle with respect to the substrate, so that to fabricate semiconductor devices with minimal size features that allow more components to be integrated into a given area or simply to increase the integration density (LIN, [0001]) . 07-22-aia AIA Claim (s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSAI, in view of YOUNG, YINIAN and CHENG as applied to claim (s) 1-3, 5-11, and 15-17 above, and further in view of Brent Alan Anderson et al, (hereinafter ANDERSON), US 20210249351 A1 . Regarding Claim 13 , TSAI as modified by YOUNG, YINIAN and CHENG teaches the semiconductor structure of claim 1. Though CHENG teaches the undoped and doped spacer materials include undoped amorphous Si or polycrystalline Si, or boron doped Si, [0028], TSAI as modified by YOUNG, YINIAN and CHENG does not explicitly disclose the semiconductor structure, wherein the first graded semiconductor material includes a graded silicon-germanium layer, wherein a germanium concentration in the graded silicon-germanium layer is higher at a top end of the graded silicon- germanium layer and lower at a bottom end of the graded silicon-germanium layer. ANDERSON teaches the semiconductor structure (Fig. 1, Integrated chips, [0008]) , wherein the first graded semiconductor material (Fig. 8, 402, first lines, [0039]) includes a graded silicon-germanium layer (conductive material as given in [0039] may be alternatively be formed from a doped semiconductor materials such as, doped polysilicon as given in [0030], further the compounds listed e.g. SiGe includes Si x Ge 1-x , where x is less than or equal to 1 as given in [0047]) , wherein a germanium concentration in the graded silicon-germanium layer is higher at a top end of the graded silicon- germanium layer and lower at a bottom end of the graded silicon-germanium layer (Fig. 8, the first lines, 402 will have a smaller width at the bottom than at the top, therefore the graded SiGe with Ge concentration will be obviously higher at the top end and lower at the bottom end of 402) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified TSAI as modified by YOUNG, YINIAN and CHENG to incorporate the teachings of ANDERSON, such that the semiconductor structure, wherein the first graded semiconductor material includes a graded silicon-germanium layer, wherein a germanium concentration in the graded silicon-germanium layer is higher at a top end of the graded silicon- germanium layer and lower at a bottom end of the graded silicon-germanium layer, so that the above mentioned materials may be selectively etchable with respect to the functionality and reducing the expense in fabricating the semiconductor devices (ANDERSON, [0002], [0053]) . Regarding Claim 14 , TSAI as modified by YOUNG, YINIAN, CHENG and ANDERSON teaches the semiconductor structure of claim 13. ANDERSON further teaches the semiconductor structure (Fig. 1, Integrated chips, [0008]) , wherein the second graded semiconductor material (Fig. 8, 802, second lines, [0039]) includes another graded silicon-germanium layer (conductive material as given in [0039] may be alternatively be formed from a doped semiconductor materials such as, doped polysilicon as given in [0030], further the compounds listed e.g. SiGe includes Si x Ge 1-x , where x is less than or equal to 1 as given in [0047]) having an inverse gradient, wherein the germanium concentration in the another graded silicon-germanium layer is lower at a top end of the another graded silicon-germanium layer and higher at a bottom end of the another graded silicon-germanium layer (Fig. 8, the second lines, 802 will have a smaller width at the top than at the bottom, therefore the graded SiGe with Ge concentration will be obviously higher at the bottom end and lower at the top end of 402) . 07-22-aia AIA Claim (s) 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSAI, in view of YOUNG, YINIAN and CHENG as applied to claim (s) 1-3, 5-11, and 15-17 above, and further in view of Tsu-Jae Liu et al, (hereinafter LIU), US 20180130668 A1 . Regarding Claim 19 , TSAI as modified by YOUNG, YINIAN, and CHENG teaches the method of claim 15. TSAI further teaches the method (Figs. 1A-1B, method of forming a semiconductor device, [0005], [0041-0043]) of claim 15, wherein forming the plurality of mandrel structures (Fig. 4, 304, mandrels patterned from 302, mandrel layer, [0025]) above the substrate (Fig. 4, 202) comprises: forming a mask layer above a silicon-containing layer of the substrate (Fig. 1A, 104, form mandrels (304) above the hard mask layer (210) in the first and second regions; above the Si substrate, (202), [0015], [0021]) ; using a first tapered etching process (the lateral etching rate of the hard mask, 210 in presence of dielectric layer, 702, resulting in a larger tapering profiles of the sidewalls, [0032]) , patterning the silicon-containing layer to achieve a plurality of sections of the silicon-containing layer with an inverse tapered profile (Fig. 1A, 112, etch the hard mask layer using the mandrels as an etching mask, [0031-0032]) ; conducting an angled ion implantation process on a first side of each section of the silicon-containing layer to form a doped region along the first side of each section of the silicon- containing layer (Fig. 1A, 108, implant a dopant to the material layer in the second region, [0027]) ; and selectively removing the silicon-containing layer from the substrate, wherein remaining doped regions provide the plurality of mandrel structures (Fig. 1A, 110, selectively etch the material layer in the first region; Fig. 1B, 116, etch the semiconductor layer and the epitaxial layer using the etched hard mask layer as an etching mask, thereby forming fins in the first and second regions; Fig. 1B, 126, form a final FinFET device) . TSAI as modified by YOUNG, YINIAN, and CHENG does not explicitly disclose the method, wherein the implantation process is an angled ion implantation process. LIU teaches the method (Figs. 1A-1D, 10, sub-lithographic patterning method) , wherein the implantation process is an angled ion implantation process (Fig. 2C, 42, ion implantation is performed at a positive tilt angle and also at a negative tile angle, [0022]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified TSAI as modified by YOUNG, YINIAN, and CHENG to incorporate the teachings of LIU, such that the method, wherein the implantation process is an angled ion implantation process, so that the ion implantation with different tilt angle to selectively damage regions of the hard making layer, leaving the central region between the photoresist features undamaged due to the shadowing effect (LIU, [0022]) . Regarding Claim 20 , TSAI as modified by YOUNG, YINIAN, CHENG and LIU teaches the method of claim 19. TSAI further teaches the method (Figs. 1A-1B, method of forming a semiconductor device, [0005], [0041-0043]) , the doped region includes boron-doped silicon (Fig. 4, 304, mandrels includes a 402, a material layer, may include amorphous silicon; amorphous silicon (a-Si) doped with boron, [0028], [0025-0026]) . Regarding Claim 21 , TSAI as modified by YOUNG, YINIAN, CHENG and LIU teaches the method of claim 19. TSAI further teaches the method (Figs. 1A-1B, method of forming a semiconductor device, [0005], [0041-0043]) , wherein a width of each of the plurality of mandrel structures is determined by a depth of an angled ion implantation (Fig. 6, the mandrels, 304 in the 206 have a larger width than the mandrels, 304 in the 204 region by at least the extra thickness of the doped material layer, 402, selectively etched by other etching methods; the impurity, 501 may be doped into the material layer, 402 through an implantation process, [0027-0030]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20190355625 A1 – Figure 8 STATEMENT OF RELEVANCE – Mandrel structure with first surface includes material 1, the second surface includes material 2, and are separated by the mandrel sidewall. US 20180197738 A1 – Figure 7A STATEMENT OF RELEVANCE – The dielectric spacer separates the non-mandrel surface and the mandrel surface of the semiconductor structure. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817 /MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/189,185 Page 2 Art Unit: 2817 Application/Control Number: 18/189,185 Page 3 Art Unit: 2817 Application/Control Number: 18/189,185 Page 4 Art Unit: 2817 Application/Control Number: 18/189,185 Page 5 Art Unit: 2817 Application/Control Number: 18/189,185 Page 6 Art Unit: 2817 Application/Control Number: 18/189,185 Page 7 Art Unit: 2817 Application/Control Number: 18/189,185 Page 8 Art Unit: 2817 Application/Control Number: 18/189,185 Page 9 Art Unit: 2817 Application/Control Number: 18/189,185 Page 10 Art Unit: 2817 Application/Control Number: 18/189,185 Page 11 Art Unit: 2817 Application/Control Number: 18/189,185 Page 12 Art Unit: 2817 Application/Control Number: 18/189,185 Page 13 Art Unit: 2817 Application/Control Number: 18/189,185 Page 14 Art Unit: 2817 Application/Control Number: 18/189,185 Page 15 Art Unit: 2817 Application/Control Number: 18/189,185 Page 16 Art Unit: 2817 Application/Control Number: 18/189,185 Page 17 Art Unit: 2817 Application/Control Number: 18/189,185 Page 18 Art Unit: 2817 Application/Control Number: 18/189,185 Page 19 Art Unit: 2817 Application/Control Number: 18/189,185 Page 20 Art Unit: 2817 Application/Control Number: 18/189,185 Page 21 Art Unit: 2817 Application/Control Number: 18/189,185 Page 22 Art Unit: 2817 Application/Control Number: 18/189,185 Page 23 Art Unit: 2817 Application/Control Number: 18/189,185 Page 24 Art Unit: 2817
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