Prosecution Insights
Last updated: July 17, 2026
Application No. 18/189,910

INTEGRATED DEVICE COMPRISING A PAIR OF INDUCTORS WITH LOW OR NO MUTUAL INDUCTANCE

Non-Final OA §102§103§112
Filed
Mar 24, 2023
Examiner
LIU, BENJAMIN T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
2 (Non-Final)
75%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
533 granted / 710 resolved
+7.1% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
744
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.3%
+46.3% vs TC avg
§102
11.5%
-28.5% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Response to Arguments Applicant’s arguments with respect to claims 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Regarding claims 1 and 16, applicant argues on page 12 of the arguments that Kawano does not disclose that the first spiral does not directly touch the second spiral because as labeled in annotated fig. 8A of Kawano on page 12 of the arguments, “inductors touch each other”. However, the top and bottom 200 of fig. 8A of Kawano are connect through the interconnect 230. Thus, the top and bottom 200 of fig. 8A of Kawano do not directly touch each other. Claims 1 and 16 remain rejected. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1 line 4, it is indefinite as to whether the “die interconnection” refers to the “die interconnection portion” in claim 1 line 3 or something else. For purpose of examination the former interpretation will be used. Claim 1 recites the limitation "die interconnection" in 4. There is insufficient antecedent basis for this limitation in the claim. Claims 2-15 do not resolve the deficiencies of claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-10 and 12-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawano et al. (US 2012/0075050) (“Kawano”). With regard to claim 1, figs 6 and 8A of Kawano discloses an integrated device comprising: a die substrate 100; and a die interconnection portion (200, 300) coupled to the die substrate 100, wherein the die interconnection (200, 300) comprises a first inductor 200 comprising: a first spiral (bottom 200, fig. 8A) comprising a first origin (202 of bottom 200, fig. 8A) and a first tail (204 of bottom 200, fig. 8a); and a second spiral (bottom 220, fig. 8A) comprising a second origin (202 of top 200, fig. 8A) and a second tail (top 200, fig. 8A); and one or more inductor interconnects 142 coupled to (i) the first origin (202 of bottom 200, fig. 8A) of the first spiral (bottom 200, fig. 8A) and (ii) the second origin (202 of top 200, fig. 8A) of the second spiral (top 200, fig. 8A), wherein the first spiral (bottom 200, fig. 8A) does not directly touch 230 the second spiral (top 200, fig. 8A); wherein the first tail (204 of bottom 200, fig. 8A) of the first spiral (bottom 200, fig. 8A) winds in a first rotational direction (clockwise), and wherein the second tail (204 of top 200, fig. 8A) of the second spiral winds (top 200, fig. 8A) in a second rotational direction (counter clockwise) that is opposite to the first rotational direction (clockwise), and a second inductor 300 vertically overlapping with the first spiral (bottom 200, fig. 8A) and the second spiral (top 200, fig. 8A) of the first inductor 200. With regard to claim 2, figs 6 and 8A of Kawano discloses that the first spiral (bottom 200, fig. 8A) and the second spiral (top 200, fig. 8A) form a figure 8-shaped inductor 200. With regard to claim 3, figs 6 and 8A of Kawano discloses that at least a portion of the one or more inductor interconnects 142 is located on a different metal layer (142 above 200, fig. 6) from the first spiral (top 200, fig. 8A) and the second spiral (top 200, fig. 8A). With regard to claim 4, figs 6 and 8A of Kawano discloses that the one or more inductor interconnects 142 comprise: a first inductor via (“via plug”, par [0070]) coupled to the first origin (202 of bottom 200, fig. 8A) of the first spiral (bottom 200, fig. 8A); a second inductor via (“via plug”, par [0070]) coupled to the second original (202 of top 200, fig. 8A) of the second spiral (top 200, fig. 8A); and an inductor trace 142 coupled to the first inductor via and the second inductor via (“via plug”, par [0070]). With regard to claim 5, figs. 6 and 8A of Kawano discloses that the first spiral (top 200, fig. 8A) is located on a same metal layer of the integrated device as the second spiral (bottom 200, fig. 8A). With regard to claim 6, figs. 6 and 8A of Kawano discloses that the first inductor 200 and the second inductor 300 are located in the die interconnection portion, and wherein the first inductor 200 is located on a different metal layer (200 below 300 in fig. 6) of the integrated device than the second inductor 300. With regard to claim 7, figs. 6 and 8A of Kawano discloses that the first rotational direction is a clockwise direction (bottom 200 rotates clockwise, fig. 8A), and wherein the second rotational direction (top 200 rotates counter clockwise, fig 8A) is a counter clockwise direction. With regard to claim 8, figs. 6 and 8A of Kawano discloses the first rotational direction (top 200, fig. 8A) is a counter clockwise direction (top 200 rotates counter clockwise), and wherein the second rotational direction (bottom 200, fig. 8A) is a clockwise direction (bottom 200 rotates clockwise). With regard to claim 9, figs. 6 and 8A-8B of Kawano disclose that the first inductor (bottom 200 in fig. 8a) is coupled (“generates a received signal corresponding to the transmitted signal “, par [0012]) to the second inductor 300 in shunt and/or in series 300. With regard to claim 10, figs. 6 and 8A-8B of Kawano discloses that the second inductor 300 includes a second spiral inductor (top 300, fig. 8A). With regard to claim 12, figs. 6 and 8A-8B of Kawano discloses that the second inductor 300 is located in the die interconnection portion (300, 200), and wherein the second inductor 300 is located above the first inductor 200. With regard to claim 13, fig. 24 of Kawano discloses that the second inductor 300 is located below the first inductor 200. With regard to claim 14, fig. 6 and 8A-8B of Kawano discloses a metallization portion, wherein the second inductor 300 is located in the metallization portion, and wherein the first inductor 200 is located on a different metal layer (200 below 300, fig. 6) of the integrated device than the second inductor 300. With regard to claim 15, fig. 6 and 8A-8B of Kawano discloses that the first spiral (bottom 200, fig. 8A) comprises at least one first interconnect (bottom 200, fig. 8A), and wherein the second spiral (top 200, fig. 8A) comprises at least one second interconnect (top 200, fig. 8A). With regard to claim 16, figs. 6 and 8A-8B of Kawano discloses a device comprising: a first inductor (300, 200) comprising: a first spiral (bottom 200, fig. 8A) comprising a first origin (202 of bottom 200, fig. 8A) and a first tail (204 of bottom 200, fig. 8A); and a second spiral (top 200, fig. 8A) comprising a second origin (202 of bottom 200, fig. 8A) and a second tail (204 of bottom 200, fig. 8A), wherein the first spiral (top 200, fig. 8A) and the second spiral (bottom 200, fig. 8A) form a figure 8-shaped inductor 200; and one or more inductor interconnects 142 coupled to the first spiral (top 200, fig. 8A) and the second spiral, wherein the first spiral (bottom 200, fig. 8A) does not directly touch the second spiral (top 200, fig. 8A); wherein the first tail (204 of bottom 200, fig. 8A) of the first spiral (bottom 200, fig. 8A) winds in a first rotational direction (clockwise), and wherein the second tail (204 of top 200, fig. 8A) of the second spiral (top 200, fig. 8A) winds in a second rotational direction (counter clockwise) that is opposite to the first rotational direction (clockwise); and a second inductor 300 vertically overlapping with the first spiral (bottom 200, fig. 8A) and the second spiral (top 200, fig. 8A) of the first inductor 200. With regard to claim 17, figs. 6 and 8A-8B of Kawano discloses that the device comprises an integrated device that includes a plurality of die interconnects (300, 200), wherein the first inductor 200 is formed based on a first plurality of die interconnects 200 from the plurality of die interconnects of the integrated device (300, 200), and wherein the second inductor 300 is formed based on a second plurality of die interconnects 300 from the plurality of die interconnects of the integrated device (300, 200). With regard to claim 18, figs. 6 and 8A-8B of Kawano discloses that the device comprises: an integrated device that includes a plurality of die interconnects (300, 200), and a substrate 112 comprising a plurality of interconnects 200, wherein the first inductor 200 is formed based on die interconnects (300, 200) from the plurality of die interconnects of the integrated device (300, 200) , and wherein the second inductor 300 is formed based on interconnects 300 from the plurality of interconnects 300 of the substrate 120. With regard to claim 19, figs. 6 and 8A-8B of Kawano discloses the device comprises: an integrated device that includes a plurality of die interconnects (300, 200), and a substrate 120 comprising a plurality of interconnects (300, 200), wherein the first inductor (300, 200) is formed based on interconnects from the plurality of interconnects of the substrate 120, and wherein the second inductor 300 is formed based on die interconnects from the plurality of die interconnects (300, 200) of the integrated device (300, 200). With regard to claim 20, figs. 6 and 8A-8B of Kawano discloses the device comprises: an integrated device that includes a plurality of die interconnects , and a metallization portion comprising a plurality of metallization interconnects, wherein the first inductor 200 is formed based on die interconnects from the plurality of die interconnects of the integrated device (300, 200), and wherein the second inductor 300 is formed based on metallization interconnects from the plurality of metallization interconnects of the metallization portion (300, 200). With regard to claim 21, figs. 6 and 8A-8B of Kawano discloses the device comprises: an integrated device that includes a plurality of die interconnects (300, 200), and a metallization portion comprising a plurality of metallization interconnects (300, 200), wherein the first inductor 200 is formed based on metallization interconnects from the plurality of metallization interconnects of the metallization portion (300, 200), and wherein the second inductor 300 is formed based on die interconnects from the plurality of die interconnects of the integrated device (300, 200). With regard to claim 22, figs. 6 and 8A-8B of Kawano discloses that at least a portion of the one or more inductor interconnects 142 is located on a different metal layer (142 above 200, fig. 6) than the first spiral (bottom 200, fig. 8A) and the second spiral (top 200, fig. 8A). With regard to claim 23, figs. 6 and 8A-8B of Kawano discloses that one or more inductor interconnects (via plug and 142) comprise: a first inductor via (“via plug”, par [0070]) coupled to the first origin (202 of bottom 200, fig. 8A) of the first spiral (bottom 200, fig. 8A); a second inductor via (“via plug”, par [0070]) coupled to the second original (202 of top 200, fig. 8A) of the second spiral (top 200, fig. 8A); and an inductor trace 142 coupled to the first inductor via and the second inductor via (“via plug”, par [0070]). With regard to claim 24, figs. 6 and 8A-8B of Kawano discloses that the first inductor 200 is located on a different metal layer (200 below 300, fig. 6)than the second inductor 300. With regard to claim 25, figs. 6 and 8A-8B of Kawano discloses that the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device (“transmitting the electrical signal”, par [0009]), a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kawano et al. (US 2012/0075050) (“Kawano”) in view of Carpentier (US 6,608,364). With regard to claim 11, Kawano does not disclose that the first inductor and the second inductor are configured as a transformer. However, fig. 1 of Carpentier discloses that the first inductor 3 and the second inductor 2 are configured as a transformer (“transformer 1”, col. 3 ll. 28). Therefore, it would have been obvious to one of ordinary skill in the art to form the inductors of Kawano as the transformers as taught in Carpentier in order to provide a transformer that supplies two signals of equal magnitude but with a phase of 180.degree. See co. 3 ll. 26-28 of Carpentier. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Mar 24, 2023
Application Filed
Oct 16, 2025
Non-Final Rejection mailed — §102, §103, §112
Jan 15, 2026
Response Filed
Apr 30, 2026
Final Rejection mailed — §102, §103, §112
Jun 30, 2026
Response after Non-Final Action

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Prosecution Projections

2-3
Expected OA Rounds
75%
Grant Probability
87%
With Interview (+11.9%)
2y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

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