DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marimuthu et al. (US pat 8263439).
With respect to claim 14, Marimuthu et al. teach a package comprising (see figs. 1-9i, particularly fig. 8i and associated text):
a substrate comprising:
(i) a first cored substrate portion comprising:
a first core layer 440 comprising a first cavity (space where 434 occupies);
a first integrated device 434 located in the first cavity of the first core layer, wherein the first integrated device comprises a first front side (bottom) and a first back side (top); and
a first dielectric layer 454 at least partially encapsulating the first integrated device; and
(ii) a second cored substrate portion comprising:
a second core layer 404 comprising a second cavity (space where 402 occupies);
a second integrated device 402 located in the second cavity of the second core layer, wherein the second integrated device comprises a second front side (top) and a second back side (bottom); and
wherein the second back side of the second integrated device faces in a direction toward the first back side of the first integrated device; and
a second dielectric layer 418 at least partially encapsulating the second integrated device; and
a third integrated device 460 coupled to the substrate through a plurality of solder interconnects 464.
With respect to claim 15, Marimuthu et al. teach a plurality of through substrate vias 444, 414 (outer) extending through the first cored substrate portion and the second cored substrate portion. See fig. 8i and associated text.
With respect to claim 16, Marimuthu et al. teach the first cored substrate portion comprises a first plurality of interconnects 444 (inner),436, and wherein the second cored substrate portion comprises a second plurality of interconnects 414 (inner), 430. See fig. 8i and associated text.
With respect to claim 17, Marimuthu et al. teach the first plurality of interconnects comprises: a first plurality of core interconnects 444 (inner) located in the first core layer; and a third plurality of interconnects 436 located at least in the first dielectric layer, and wherein the second plurality of interconnects comprises: a second plurality of core interconnects 414 (inner) located in the second core layer; and a fourth plurality of interconnects 410 located at least in the second dielectric layer. See fig. 8i and associated text.
With respect to claim 18, Marimuthu et al. teach the first plurality of interconnects are configured to be electrically coupled to the second plurality of interconnects through the plurality of through substrate vias 444,414 (outer), wherein the first back side of the first integrated device faces in a first direction, and wherein the second back side of the second integrated device faces in a second direction that is opposite to the first direction. See fig. 8i and associated text.
With respect to claim 19, Marimuthu et al. teach a first metallization portion 458 coupled to the first cored substrate portion; and a second metallization portion 422 coupled to the second cored substrate portion. See fig. 8i and associated text.
With respect to claim 20, Marimuthu et al. teach the first cored substrate portion is coupled to the second cored substrate portion through a third dielectric layer, wherein the first back side of the first integrated device faces in a direction toward the second back side of the second integrated device. See fig. 8i and associated text and col. 15, lines 15-20.
With respect to claim 21, Marimuthu et al. teach a third core layer located between the first core layer and the second core layer. See fig. 8i and associated text and col. 5, lines 40-55 (col. 5, lines 40-455 teaches multiple cored substrates).
With respect to claim 22, Marimuthu et al. teach the first cored substrate portion is coupled to the third core layer through a first dielectric layer, and wherein the second cored substrate portion is coupled to the third core layer through a second dielectric layer. See fig. 8i and associated text and col. 5, lines 40-55 and col. 15, lines 15-20.
With respect to claim 23, Marimuthu et al. teach a plurality of through substrate vias extending through the first cored substrate portion, the third core layer and the second cored substrate portion (fig. 8i teaches each cored substate having through via and col. 5, lines 40-455 teaches multiple cored substrates). See fig. 8i and associated text and col. 5, lines 40-55.
With respect to claim 24, Marimuthu et al. teach the first cored substrate portion comprises a first plurality of interconnects, and wherein the second cored substrate portion comprises a second plurality of interconnects. See fig. 8i and associated text.
With respect to claim 25, Marimuthu et al. teach a third plurality of interconnects 452 located between the first cored substrate portion and the second cored substrate portion. See fig. 8i and associated text.
With respect to claim 26, Marimuthu et al. teach a fourth integrated device coupled to the substrate through a second plurality of solder interconnects, wherein the first integrated device is a first chiplet, wherein the second integrated device is a second chiplet, wherein the third integrated device is a third chiplet, and wherein the fourth integrated device is a fourth chiplet. See fig. 8i and associated text and col. 5, lines 40-55 (col. 5, lines 40-455 teaches multiple cored substrates).
Response to Arguments
Applicant's arguments filed 2/26/26 have been fully considered but they are not persuasive. See the above rejections.
In response to the applicant’s arguments on pages 10-12 of the amendment dated 2/26/26, it is submitted that there are no structural differences in arbitrarily calling the back and front sides of a device, they’re merely opposite sides of the device. Further, claim language is to be given broadest interpretation during examination. Further, limitations from outside of claims are not given patentable weight in patentability determination of claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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