DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 18 June 2026.
Applicant's election with traverse of Species A in the reply filed on 18 June 2026 is acknowledged. The traversal is on the ground that Species A and B are not mutually exclusive. This has been found persuasive, and the species restriction is withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamaru et al (EP 1071130 A2, hereinafter “Tamaru”).
Regarding Claim 1 - Tamaru discloses a method for forming an integrated circuit (semiconductor device [0006]), the method comprising: forming a substrate comprising an interior region and an edge region surrounding an outer perimeter of the interior region of a chip (Semiconductor device [0006] with peripheral edge [0031]); and forming a seal ring in the edge region (Seal ring S1211 and auxiliary ring S1212 considered as the seal ring [0031] and Fig. 13), the seal ring comprising a plurality of metal-insulator-metal (MIM) capacitors (Seal ring S1211 and auxiliary ring S1212 forming seal ring capacitor [0119] and Fig. 13); wherein each of the MIM capacitors comprises two or more plates and one or more dielectric layers, wherein each dielectric layer is positioned between an adjacent pair of the two or more plates (S1211 and S1212 form two plated, separated by insulating film C1200 [0119] and annotated Fig. 13); and wherein a portion of the two or more plates extends over an interconnect in the interior region of the substrate (Input and Output lines shown under VSS and VDD, which are extensions of the capacitor plates, Fig. 13).
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Regarding Claim 2 - Tamaru further discloses the method of claim 1, wherein each of the MIM capacitors is configured both as a decoupling capacitor and as a crack stop (Seal ring S1211 + S1212 functions as crack stop, as is commonly understood in the industry, and the capacitor thus formed can be called a decoupling capacitor (e.g. a countermeasure for power source noise [0006])).
Regarding Claim 3 - Tamaru discloses the method of claim 1, wherein the seal ring further comprises an outer wall and an inner wall (Annotated Fig. 13).
Regarding Claim 4 - Tamaru discloses the method of claim 3, wherein each of the MIM capacitors is positioned between the outer wall and the inner wall (Annotated Fig. 13).
Regarding Claim 5 - Tamaru discloses the method of claim 1, wherein each of the MIM capacitors is electrically coupled to a last metal wiring level of the interconnect (VSS and VDD are in the top level interconnect, same as the bond pads BP, Fig. 13).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898