Prosecution Insights
Last updated: August 17, 2026
Application No. 18/190,234

THREE-DIMENSIONAL METAL-INSULATOR-METAL CAPACITOR EMBEDDED IN SEAL STRUCTURE

Non-Final OA §102
Filed
Mar 27, 2023
Priority
Dec 06, 2021 — divisional of 12/549,347
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
4 granted / 6 resolved
-1.3% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
46 currently pending
Career history
62
Total Applications
across all art units

Statute-Specific Performance

§103
60.3%
+20.3% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 6 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 6-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 18 June 2026. Applicant's election with traverse of Species A in the reply filed on 18 June 2026 is acknowledged. The traversal is on the ground that Species A and B are not mutually exclusive. This has been found persuasive, and the species restriction is withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamaru et al (EP 1071130 A2, hereinafter “Tamaru”). Regarding Claim 1 - Tamaru discloses a method for forming an integrated circuit (semiconductor device [0006]), the method comprising: forming a substrate comprising an interior region and an edge region surrounding an outer perimeter of the interior region of a chip (Semiconductor device [0006] with peripheral edge [0031]); and forming a seal ring in the edge region (Seal ring S1211 and auxiliary ring S1212 considered as the seal ring [0031] and Fig. 13), the seal ring comprising a plurality of metal-insulator-metal (MIM) capacitors (Seal ring S1211 and auxiliary ring S1212 forming seal ring capacitor [0119] and Fig. 13); wherein each of the MIM capacitors comprises two or more plates and one or more dielectric layers, wherein each dielectric layer is positioned between an adjacent pair of the two or more plates (S1211 and S1212 form two plated, separated by insulating film C1200 [0119] and annotated Fig. 13); and wherein a portion of the two or more plates extends over an interconnect in the interior region of the substrate (Input and Output lines shown under VSS and VDD, which are extensions of the capacitor plates, Fig. 13). PNG media_image1.png 959 488 media_image1.png Greyscale Regarding Claim 2 - Tamaru further discloses the method of claim 1, wherein each of the MIM capacitors is configured both as a decoupling capacitor and as a crack stop (Seal ring S1211 + S1212 functions as crack stop, as is commonly understood in the industry, and the capacitor thus formed can be called a decoupling capacitor (e.g. a countermeasure for power source noise [0006])). Regarding Claim 3 - Tamaru discloses the method of claim 1, wherein the seal ring further comprises an outer wall and an inner wall (Annotated Fig. 13). Regarding Claim 4 - Tamaru discloses the method of claim 3, wherein each of the MIM capacitors is positioned between the outer wall and the inner wall (Annotated Fig. 13). Regarding Claim 5 - Tamaru discloses the method of claim 1, wherein each of the MIM capacitors is electrically coupled to a last metal wiring level of the interconnect (VSS and VDD are in the top level interconnect, same as the bond pads BP, Fig. 13). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Mar 27, 2023
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12697688
SEMICONDUCTOR DEVICE MANUFACTURING DEVICE AND MANUFACTURING METHOD
3y 5m to grant Granted Aug 04, 2026
Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+100.0%)
3y 6m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 6 resolved cases by this examiner. Grant probability derived from career allowance rate.

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