DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/21/2026 has been entered.
Response to Amendment
Applicant amended the independent claims and there were no arguments pointing out disagreements with the examiner’s contentions or the references applied against the claims, explaining how the claims avoid the references or distinguish from them.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0004247 A1 Huang et al. (herein “Huang”).
Regarding independent claim 1, Huang discloses in Figs. 1A and 7A, a method of manufacturing an optical device (para [0003]), the method comprising:
patterning a first material to form channels as part of a grating coupler (34) (para [0022]; each grating coupler has multiple channels, a.k.a. light paths);
depositing a dielectric material (40) over the grating coupler (34);
forming an opening (52) at least partially through the dielectric material over the grating coupler (34) (para [0026]);
filling the opening with a fill material (71; Fig. 7A); and
forming a first redistribution layer (paras [0020, 0061]); and
encapsulating the grating coupler (34) and a through via (52A, 52B) with an encapsulant (74), wherein after the encapsulating the through via (52A, 52B) extends through the encapsulant (74), and wherein the encapsulant surrounds the through via and the grating coupler (shown in Fig. 1E, wherein throughout the figures, encapsulant 74 is shown on top of and surrounding the through vias and grating couplers; Fig. 10, step 208).
Huang is silent as to forming a first redistribution layer over the fill material. However, Huang discusses redistribution layers on dielectric layers (20) (paras [0020, 0061]). Huang shows possession of the knowledge of including a redistribution layer with a dielectric layer. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a redistribution layer with dielectric layer such as dielectric layers 40 or 42, so as to increase the efficiency and enhance the performance of the optical device.
Regarding claims 2, 3, and 9, Huang discloses in Figs. 1A and 7A, forming a through via on a carrier substrate, wherein the forming the first redistribution layer forms the first redistribution layer over the through via (14) (paras [0019-0020, 0023-0024]), and forming a second redistribution layer (22) on an opposite side of the grating coupler (34) from the first redistribution layer (paras [0020, 0056, 0061]).
Regarding claims 4, 5, 18, and 19, Huang is silent as to specifically forming the opening forms the opening to have a first width adjacent to the grating coupler of between about 20 µm and about 30 µm and forming the opening forms the opening to have a second width of between about 30 µm and about 40 µm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to a first width adjacent to the grating coupler of between about 20 µm and about 30 µm and forming the opening forms the opening to have a second width of between about 30 µm and about 40 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Optimizing the width ensures functionality of the device being manufactured.
Regarding claims 6, 10, and 16, Huang discloses in Fig. 1G, attaching/bonding a first electronic integrated circuit to the first redistribution layer (para [0028]).
Regarding independent claim 7, Huang discloses in Figs. 1A, 1E, and 7A, a method of manufacturing a semiconductor device (para [0003]), the method comprising:
forming a photonic integrated circuit (28) with a grating coupler (34) adjacent to a first side, the grating coupler comprising a plurality of channels (each grating coupler has multiple channels, a.k.a. light paths);
depositing one or more dielectric materials (40, 42) over the grating coupler (34);
replacing at least a portion of the one or more dielectric materials with a fill material (71; Fig. 7A);
encapsulating the photonic integrated circuit with a through via (52A, 52B) with an encapsulant (74), wherein the encapsulant comprises a single continuous material throughout the encapsulant (paras [0030, 0038-0039]); and
planarizing the encapsulant with the fill material and the through via (para [0047]; wherein Fig. 1E of Huang shows the encapsulant 74 planarized with vias 52A, 52B, similar to Applicant’s Fig. 3 where encapsulant 109 is planarized with vias 107).
Regarding claim 7, Huang is silent as to the encapsulant being in physical contact with the photonic integrated circuit. However, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to have the encapsulant either directly or indirectly contact the photonic integrated circuit, as needed, so long as the PIC is properly encapsulated and thus protected.
Regarding claim 8, Huang discloses in Fig. 1G, placing an optical fiber (84) over the grating coupler (34).
Regarding claim 11, Huang discloses in Fig. 1G, the encapsulating the photonic integrated circuit (28) further encapsulates an electronic integrated circuit (54) (para [0028]).
Regarding claims 12, 13, and 20, Huang is silent as to the fill material being an epoxy or siloxane. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to use epoxy or siloxane, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 125 USPQ 416. These materials are well known and readily available in the art with known properties.
Regarding claim 14, Huang discloses forming the through vias, the forming the through vias comprising: forming a seed layer on a substrate; placing and patterning a photoresist over the seed layer; plating a conductive material onto the seed layer through the photoresist; removing the photoresist; and removing a portion of the seed layer (paras [0020, 0022,0039-0042]).
Regarding independent claim 15, Huang discloses in Figs. 1A and 7A, a method of manufacturing an optical device (para [0003]), the method comprising:
forming a first substrate (12), the first substrate comprising:
an encapsulant (74), wherein the encapsulant comprises a single continuous material throughout the encapsulant;
a through via (52A, 52B) extending from a first side of the encapsulant to a second side of the encapsulant, the through via (52A, 52B) being laterally surrounded by the encapsulant (74) (shown in Fig. 1E);
a photonic integrated circuit (28) with a grating coupler (34); and
a fill material (71) planar with each of the encapsulant (74), the through via (14), and an external connector (50) of the photonic integrated circuit;
forming a first redistribution layer (22) on a first side of the first substrate (12).
Huang is silent as to forming a second redistribution layer on a second side of the first substrate. However, Huang discusses redistribution layers on dielectric layers (20) (paras [0020, 0061]). Huang shows possession of the knowledge of including a redistribution layer with a dielectric layer. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a redistribution layer with dielectric layer such as dielectric layers 40 or 42, so as to increase the efficiency and enhance the performance of the optical device.
Regarding claim 15, Huang is silent as to the encapsulant being in physical contact with the photonic integrated circuit. However, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to have the encapsulant either directly or indirectly contact the photonic integrated circuit, as needed, so long as the PIC is properly encapsulated and thus protected.
Regarding claim 17, Huang discloses in Fig. 1G, an electronic integrated circuit (54) (para [0028]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A EL-SHAMMAA whose telephone number is (571)272-2469. The examiner can normally be reached Mon-Fri, 9am-6pm (flexible schedule).
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/MARY A EL-SHAMMAA/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874