Prosecution Insights
Last updated: April 19, 2026
Application No. 18/190,763

FACTORY SYSTEM AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Non-Final OA §102§103
Filed
Mar 27, 2023
Examiner
KIM, PETER B
Art Unit
2882
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tsmc China Company Limited
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
776 granted / 938 resolved
+14.7% vs TC avg
Moderate +9% lift
Without
With
+9.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
34 currently pending
Career history
972
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
41.2%
+1.2% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 938 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I and cancellation of claims 16-20 in the reply filed on Jan. 9, 2026 is acknowledged. Information Disclosure Statement IDS filed on Feb. 2, 2024 lists a NPL document but did not include the date of the document on the IDS. The copyright year, which is the only date readily available on the document was added to the IDS. Claim Objections Claim 13 is objected to because of the following informalities: claim 13 is directed to providing a torque greater than about 0.64 Nm. 0.64 Nm is specific value and the term “about” make the value more general. Thus, it seems to use a general term “about” and use a specific, precise value. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Kim) (2010/0195066). Regarding claim 1, Kim discloses a method (Fig. 5A, 5B, 9), comprising: performing a coating process on a first one of wafers to form a photoresist layer using a coating tool (3000, 3410, Fig. 1, 2, para 0051, 0052, S128, Fig. 5A, para 0064); after performing the coating process, retrieving the first one of the wafers to a cassette (2000, Fig. 1) docked on the coating tool (3000, Fig. 1, para 0037, S190, Fig. 5B, para 0069); transferring the cassette from the coating tool to a load port (Fig. 1 and 4100 in Fig. 6) of an exposure tool (9000, Fig. 1, para 0037, “A wafer W is transferred between the coating unit 3000, the pre/post-exposure treatment unit 4000 by an automatic transfer unit 1000 or a worker. The wafer W is transferred in a state where it is received in a container (2000 in FIG. 2)”, para 0040, S212, Fig. 9, para 0100) external to the coating tool (Fig. 1); transferring the first one of the wafers from the cassette on the load port of the exposure tool to a wafer stage (inherent to 9000, Fig. 6) of the exposure tool (S214-S228, Fig. 9, para 0100, 0101); and performing an exposing process on the first one of the wafers to pattern the photoresist layer on the first one of the wafers (S230, Fig. 9, para 0101). Regarding claim 2, Kim discloses after performing the exposing process (S230), retrieving the first one of the wafers from the wafer stage of the exposure tool (9000) to the cassette (2000) on the load port (Fig. 1) of the exposure tool (S246, Fig. 9, para 0103); transferring the cassette from the exposure tool to a load port of a developing tool (para 0104, “container 2000 is carried to the developing unit 5000”, S312, Fig. 13A, para 0138); transferring the first one of the wafers from the cassette on the load port of the developing tool to a developing chamber in the developing tool (S314-S326, para 0138, 0139); and performing a developing process to the photoresist layer on the first one of the wafers (S328, para 0139). Regarding claim 11, Kim discloses a method (Fig. 9), comprising: performing an exposing process to a resist layer on a semiconductor substrate placed on a wafer stage (inherent) of an exposure apparatus (9000, Fig. 1, para 0082, S230, Fig. 9, para 0101); after performing the exposing process, transferring the semiconductor substrate from the wafer stage via an interface module (4210, Fig. 6) of the exposure apparatus to a front opening unified pod (FOUP) (para 0037) on a load port (Fig. 1 and 4100 in Fig. 6) of the exposure apparatus (Fig. 1, S232, S246, Fig. 9, para 0101, 0103); transferring the FOUP from the load port of the exposure apparatus to a load port of a developing apparatus external to the exposure apparatus (1000, Fig. 1, S312, Fig. 13A, para 0138); transferring the semiconductor substrate from the FOUP on the load port of the developing apparatus to a developing chamber in the developing apparatus (S314, S326, para 0138, 0139); and performing a developing process to the exposed resist layer on the semiconductor substrate (S328, para 0139). Regarding claim 12, Kim discloses wherein transferring the semiconductor substrate from the wafer stage via the interface module is performed by a gripper (4220) disposed in the interface module (Fig. 6, 7) having four degrees of freedom (para 0084, “index robot 4220 has a 4-shaft driving structure such that a hand 4221 directly handling the wafer W can move in the first, second, and third directions 12, 14, and 16 and rotate on a horizontal plane”). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) in view of Lee (2007/0166030). Regarding claims 3 and 4, Kim discloses the claimed invention as discussed above. However, Kim does not disclose wherein the developing process is performed for a longer time duration than the exposing process and wherein the coating process is performed for a longer time duration than the exposing process. Lee discloses a method for performing a coating process (117, Fig. 1, para 0025), an exposure process (150, Fig. 1, para 0030) and a development process (119, Fig. 1, para 0027). Lee discloses a speed regulator (170, Fig. 2, para 0037) for detecting and adjusting the duration of time for each processing. Although Lee does not disclose that the developing process and the coating process are both performed for a longer time duration than the exposing process, Lee discloses adjusting the execution speed of the coating process and the exposure process so that the coating process time is not shorter to the exposure process and the development process time is not shorter than the exposure process time (para 0029, 0034, 0037, 0038). Therefore, it would have been obvious to one of ordinary skill in the art to provide the means to adjust the various processing speed so that the developing process is longer than the exposure process to ensure that a sufficient time is used for developing to improve contrast and stability and to ensure that a sufficient time is used for coating to improve uniformity of coating and adhesion. Regarding claim 5, Kim does not disclose wherein the exposure tool is a dual-wafer-stage tool. Lee discloses wherein the exposure tool is a dual-wafer-stage tool (a stage at exposure tool 154 and a stage at pre-alignment unit 156). Therefore, it would have been obvious to one of ordinary skill in the art to provide a dual-wafer-stage tool, which is well known in the art, as the exposure tool in order to improve throughput. Claim(s) 6, 14, 21-23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) in view of Takano (6,580,958). Regarding claim 6, Kim does not disclose wherein the load port of the exposure tool is at a higher position than the wafer stage of the exposure tool. Takano discloses an exposure tool (Fig. 1 and 2) comprising a load port (230, Fig. 2) and a wafer stage (209) of the exposure tool (Fig. 2). Although Takano does not explicitly disclose that the load port is at a higher position than the wafer stage of the exposure tool, Fig. 2 shows that load port at a higher position than the wafer stage (col. 4, lines 19-23). While the drawings are not drawn to scale and do not define the precise proportions, the Fig. 2 does suggest that the load port is higher and the “wafer carrier elevator 230” also suggest that the height can be adjusted so that it is placed higher than the wafer stage. Therefore, it would have been obvious to one of ordinary skill in the art to provide the load port which is arranged at a higher position than the wafer stage in order for the transferring robot or arm to prevent any particles generated and for more efficient and compact handling. Regarding claim 14, Kim does not disclose introducing a gas flow from above the load port of the exposure apparatus toward the load port of the exposure apparatus by a gas blowing system installed on the interface module. Takano discloses a gas flow from above the load port of the exposure apparatus toward the load port of the exposure apparatus by a gas blowing system (Fig. 2, col. 4, lines 24-51) installed on the interface module (a part of the gas blowing module g is located over the interface module where wafer convey unit 231 is located, Fig. 2). Therefore, it would have been obvious to one of ordinary skill in the art to provide a gas blowing system above the load port in order to maintain a predetermined ambient temperature of the wafers in the FOUP. Regarding claim 21, Kim discloses a method (Fig. 1), comprising: positioning a wafer carrier (2000) at a load port (4100, Fig. 6, para 0082) of a lithography exposure apparatus (9000, para 0040), wherein the lithography exposure apparatus is separated from a coating apparatus (3000) and a developing apparatus (5000, Fig. 1); transferring a wafer (W) from the wafer carrier (2000) by a wafer transfer gripper (index robot 4220, 4221, Fig. 6, para 0083, 0084); placing the wafer onto the first wafer stage (inherent); exposing the wafer on the first wafer stage (inherent); and after completing exposure, transferring the wafer from the first wafer stage back to the wafer carrier by the wafer transfer gripper (index robot 4220, para 0103). However, Kim does not disclose moving the wafer transfer gripper from a first height corresponding to the load port to a second height lower than the first height and corresponding to a first wafer stage of the lithography exposure apparatus. Takano discloses an exposure tool (Fig. 1 and 2) comprising a load port (230, Fig. 2) and a wafer stage (209) of the exposure tool (Fig. 2). Although Takano does not explicitly disclose that the load port is at a higher position than the wafer stage of the exposure tool, Fig. 2 shows that load port at a higher position than the wafer stage (col. 4, lines 19-23). While the drawings are not drawn to scale and do not define the precise proportions, the Fig. 2 does suggest that the load port is higher and the “wafer carrier elevator 230” also suggest that the height can be adjusted so that it is placed higher than the wafer stage. Therefore, it would have been obvious to one of ordinary skill in the art to provide the load port which is arranged at a higher position than the wafer stage in order for the transferring robot or arm to prevent any particles generated and for more efficient and compact handling by the wafer transfer gripper (4220, 4221) to move the wafer from a first height corresponding to the load port to a second height lower than the first height and corresponding to a first wafer stage of the lithography exposure apparatus. Regarding claim 22, Kim discloses wherein the lithography exposure apparatus operates independently from the coating apparatus and the developing apparatus without sharing a common load port (Fig. 1 shows the exposure apparatus, the developing apparatus and the coating apparatus with separate load ports and not sharing a common load port, 5A, 5B, 9, 13A, 13B, show the method in which the exposure apparatus, the developing apparatus and the coating apparatus are operated independently). Regarding claim 23, Kim discloses wherein placing the wafer onto the first wafer stage comprises positioning the wafer onto one of the first wafer stage or a second wafer stage of the lithography exposure apparatus (inherently, the wafer would be place on the first wafer stage in the exposure apparatus 9000). Regarding claim 25, Kim discloses after exposing the wafer, transferring the wafer to the developing apparatus (Fig. 10, S312, S314, Fig. 13A, para 0138) that is arranged in a track different from a track of the lithography exposure apparatus (Fig. 1, 6, 9, 13A, 13B, developing apparatus and the exposure apparatus are arranged in different tracks in Fig. 1), and performing a developing process on the wafer in the developing apparatus (S328, Fig. 13A, para 0139). Claim(s) 7 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim). Regarding claim 7, Kim discloses wherein transferring the first one of the wafers from the cassette is performed by a transferring system, the transferring system (Fig. 6, 7) comprises: a railway extending along a first direction (4230, Fig. 6, para 0084); a lifter (4222) movably coupled to the railway (Fig. 6, 7), and a wafer gripper (4221). Although Kim does not disclose a rotor liftable by the lifter; a linear actuator rotatable by the rotor and movable along a second direction perpendicular to the first direction; and the wafer gripper on the linear actuator, Kim discloses that the gripper 4221 “can move in the first, second, and third directions 12, 14, and 16 and rotate on a horizontal plane” and the lifter 4222 “is provided to be expandable, contractible, and rotatable”. (Fig. 6, 7, para 0084). Therefore, it would have been obvious to one of ordinary skill in the art to provide a rotor liftable by the lifter; a linear actuator rotatable by the rotor and movable along a second direction perpendicular to the first direction; and the wafer gripper on the linear actuator in order to provide the movements disclosed in para 0084. Regarding claim 13, although Kim does not disclose wherein a movement of the gripper is driven by a linear motor providing a torque greater than about 0.64 Nm, Kim discloses in para 0084 the movement of the arm 4222 and hand 4221 carrying the wafer from cassette 2000 to exposure stage. It would have been obvious to one of ordinary skill in the art to provide a linear motor which produces enough torque for the gripper to grip the wafer and to transfer the wafer including providing a torque greater than 0.64 Nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) as applied to claim 7 above, and further in view of Ishizawa et al. (Ishizawa) (6,162,010). Regarding claims 8 and 9, the further difference between the modified Kim and the claimed invention is detecting a storage status of slots in the cassette using a metrology device positioned on the wafer gripper when the cassette is docked on the load port of the exposure tool; and determining whether the storage status of the slots in the cassette is acceptable and issuing a warning when the storage status of the slots is not acceptable. Ishizawa discloses a treatment system (100, Fig. 1) comprising load ports for cassette (112, 114, col. 6, lines 15-35). Ishizawa discloses detecting a storage status of slots in the cassette using a metrology device positioned on the wafer gripper (col. 10, lines 21-28, “an optical sensor, capable of detecting the presence of wafers W on the transport arm 118”) when the cassette is docked on the load port of the exposure tool; and determining whether the storage status of the slots in the cassette is acceptable (col. 9, line 58 – col. 10, line 20, col. 10, lines 29-40). Ishizawa also discloses issuing a warning when the storage status of the slots is not acceptable (col. 10, lines 15-20, “an operator… is notified that the recovery of the wafers W can not be carried out”). Therefore, it would have been obvious to one of ordinary skill in the art to further modify Kim by providing the metrology device of Ishizawa in order to ensure that the wafer can be efficiently retrieved for processing and returned after processing without causing damages to the wafer. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) as applied to claim 7 above, and further in view of Yazawa et al. (Yazawa) (WO 2015/037701, machine translation provided with Office Action, page number refers to the translation). Regarding claim 10, the further difference between the claimed invention and the modified Kim is determining whether a temperature of the wafer gripper reaches a predetermined temperature; and lowering the temperature of the wafer gripper when the temperature of the wafer gripper reaches the predetermined temperature. Yazawa discloses a wafer gripper (page 14, “transport object to be transported by the robot 1 may be…a semiconductor wafer or the like”) and determining whether a temperature of the wafer gripper reaches a predetermined temperature; and lowering the temperature of the wafer gripper when the temperature of the wafer gripper reaches the predetermined temperature (abstract, temperature sensor 80 for measuring temperature of each arm and colling arm sections on the basis of the detection results). Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) in view of Orishimo (2009/0005998). Regarding claim 15, Kim does not disclose exhibiting an operation status of the exposure apparatus from a signal tower installed on the interface module. Although Orishimo does not disclose a signal tower installed on the interface module, Orishimo discloses a display unit to exhibit an operation status of the exposure apparatus (para 0031). Therefore, it would have been obvious to one of ordinary skill in the art to provide a display or an indicator to exhibit an operation status of the exposure apparatus to the operator so that the operator can issue a command to the exposure apparatus as appropriate. Further, it would have been obvious to one of ordinary skill in the art to provide a signal tower or an indicator on another portion of the exposure tool such as the interface module to notify the operator since it has been held that rearranging parts of an invention involves only routine skill in the art. Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) in view of Takano as applied to claim 23 above, and further in view of Lee. The further difference between the claimed invention and the modified Kim is exposing the wafer on the first wafer stage while another wafer is positioned on the second wafer stage. Lee discloses a first wafer stage (at exposure unit 154) and a second wafer stage (at pre-alignment unit 156). Although Lee does not disclose exposing the wafer on the first wafer stage while another wafer is positioned on the second wafer stage, the examiner takes an office notice that exposing one wafer while performing pre-alignment on another wafer to improve throughput is well known in the art. Therefore, it would have been obvious to one of ordinary skill in the art to further modify Kim by providing a second wafer stage in order to improve throughput. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pavik et al. (Pavik) (2021/0402607) discloses wafer transfer robot for transferring wafer from a container (Fig. 1) and detecting abnormal operating condition (abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER B KIM whose telephone number is (571)272-2120. The examiner can normally be reached M-F 8:00 AM - 4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toan Ton can be reached at (571) 272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER B KIM/ Primary Examiner, Art Unit 2882 February 18, 2026
Read full office action

Prosecution Timeline

Mar 27, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+9.1%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 938 resolved cases by this examiner. Grant probability derived from career allow rate.

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