Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant’s Amendment filed on December 18, 2025 has been fully considered and entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15-18 and 20-24 are rejected under 35 U.S.C. 103(a) as being unpatentable over Liff et al. (US 2020/0227377 A1) in view of Kulkarni et al. (US 2021/0321526 A1), further in view of Yoo et al. (US 2019/0310433 A1).
Regarding claim 15, Liff discloses a package (1700 in Fig. 30) comprising: an interposer (1704); a first electronic chip (1720) disposed on the interposer; a circuit board (1702) having a first surface (1740) and a second surface (1742) opposite the first surface, wherein the interposer is coupled to the first surface of the circuit board; an IC package (1726) coupled to the second surface of the circuit board; and a connection (1706, 1708, 1710; paragraph 0141) of the IC package to the first electronic chip, wherein the connection traverses the circuit board and the photonic interposer.
Still regarding claim 15, Liff teaches the claimed invention except for a voltage regulator module (VRM). Kulkarni discloses a voltage regulator module VRM (118 in Fig. 2; paragraph 0039) coupled to an underside of a circuit board (106) configured to provide regulated power from the VRM to power operation (paragraph 0017 describes circuit board including additional components such as “voltage regulators or other power circuitry”; thus, a VRM would provide regulated power) of an electronic chip (114), using a connection which traverses the circuit board (the voltage regulator 118 positioned on the underside of the circuit board must send the voltage via a connection through the circuit board to the top surface). Since both of the inventions relate to chip devices, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to use a voltage regulator module as disclosed by Kulkarni in the device of Liff for the purpose of reducing resistive losses.
Still regarding claim 15, the proposed combination of Liff and Kulkarni teaches the claimed invention except for a photonic interposer. Yoo discloses a photonic package (Fig. 2A) comprising a photonic interposer (202) and an electronic chip (206) disposed on the photonic interposer. Since both of the inventions relate to chip devices, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to use a photonic interposer as disclosed by Yoo in the device of the proposed combination of Liff and Kulkarni for the purpose of providing optical as well as electrical capabilities, allowing for larger communication capacity.
Regarding claims 16, 17 and 22, Liff discloses a socket and a substrate (paragraph 0139 discloses the interposer structure 1736 including male and female portions of a socket; the male portion fits into the socket would naturally include some portion constituting a substrate), wherein the photonic interposer is disposed on the substrate and the substrate is disposed on the socket, wherein the connection further traverses the substrate and the socket, and wherein the socket is disposed on the circuit board in Fig. 30.
Regarding claims 18 and 25, Liff discloses that the IC package on the underside of the PCB can be any type of die or IC chip in paragraphs 0140-0143. The proposed combination of Liff, Kulkarni and Yoo teaches the claimed invention except for specifically stating a power bus. Further, power buses are well-known and commonly used in the art of integrated circuit devices, and as such, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to use a power bus configured to provide an input voltage to the voltage regulator module, which regulates the output voltage to the first electronic chip for the purpose of providing power to the chips in the package. Further, it would be obvious to have the power bus coupled to the second surface of the circuit board in order to conserve space and reduce the size of the package.
Regarding claim 20, Liff discloses the first electronic chip is in contact with the photonic interposer in Fig. 30.
Regarding claim 21, the proposed combination of Liff, Kulkarni and Yoo teaches the claimed invention except for specifically stating a lid and a cold plate. However, lids with cold plates are well-known and commonly used in the art of integrated circuits, and as such, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to use a lid covering the photonic interposer and a cold plate covering the lid, wherein the lid is in thermal contact with the first electronic chip in order to provide protection from the external environment and also to provide heat transfer.
Regarding claims 23 and 24, Liff discloses a second electronic chip (paragraph 0140 discloses multiple IC packages coupled to the interposer 1704). A second chip would naturally include a set second of components such as a second VRM and a second connection coupling the VRM to the second chip.
Claims 26-35 are rejected under 35 U.S.C. 103(a) as being unpatentable over Liff et al. (US 2020/0227377 A1) in view of Kulkarni et al. (US 2021/0321526 A1), further in view of Yoo et al. (US 2019/0310433 A1) and further in view of Harris et al. (US 2020/0284981 A1).
Regarding claim 26, the proposed combination of Liff, Kulkarni and Yoo teaches the claimed invention except for the interposer comprising a plurality of photonic tiles. Harris discloses a photonic interposer comprising a plurality of photonics tiles that are instantiations of a template photonic tile in Fig. 8A and paragraphs 0146-0147. Since all of the inventions relate to integrated circuit devices, one having ordinary skill in the art at the time of the invention would have found it obvious to use an interposer comprising a plurality of photonic tiles as disclosed by Harris in the package of the proposed combination of Liff, Kulkarni and Yoo for the purpose of forming an adaptable communications platform that can be configured based on the needs of a particular architecture.
Regarding claim 27, Harris in view of the rejection of claim 26, further discloses each of the plurality of photonics tiles comprises: a transceiver (700 in Figs. 6A-6C) comprising a transmitter and a receiver (paragraph 0132); electrical connections, coupled to the transceiver, configured to permit electrical communication between the transceiver and a first electronic chip (paragraphs 0087-0088); and an optical distribution network (104 in Fig. 3A; paragraph 0101) comprising a first set of bus waveguides optically coupled to the transceiver, a second set of bus waveguides (waveguides 111-114), and a plurality of programmable interconnections (paragraphs 0137-0138), each programmable interconnection being configured to selectively place a bus waveguide of the first set of bus waveguides in optical communication with a bus waveguide of the second set of bus waveguides, wherein each programmable interconnection comprises a waveguide crossing and an active coupler (105).
Regarding claim 28, Harris in view of the rejection of claim 26, further discloses a plurality of modulators, coupled to a first bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another; and a plurality of drop filters, coupled to a second bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another (paragraphs 0120, 0124, 0138, 0142).
Regarding claim 29, Harris further discloses the wavelength division multiplexing (WDM) schemes to increase bandwidth in paragraph 0124 and the optical distribution network including optical resonators in paragraph 0126. The proposed combination of Liff, Yoo and Harris teaches the claimed invention except for resonant modulators and resonant drop filters. However, resonant modulators and resonant drop filters are well-known and commonly used in the art of WDM devices, and as such, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to use resonant modulators and resonant drop filters for the purpose of increasing the number of communication channels and increasing bandwidth.
Regarding claim 30, Harris in view of the rejection of claim 26, further discloses a polarization splitter coupled to both the transmitter and the receiver; and a fiber coupler coupled to the polarization splitter in paragraphs 0124, 0127 and 0130.
Regarding claim 31, Harris in view of the rejection of claim 26, further discloses the plurality of photonics tiles are arranged two-dimensionally and form a plurality of columns of photonic tiles and a plurality of rows of photonic tiles in Figs. 3D, 5B and 6C.
Regarding claim 32, the proposed combination of Liff, Kulkarni, Yoo and Harris teaches the claimed invention except for specifically stating the size of each tile. However, it would have been obvious to one having ordinary skill in the art at the time of the invention to arrive at the claimed size, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claims 33 and 34, Harris in view of the rejection of claim 26, further discloses the photonic interposer comprises a transceiver and wherein the first electronic chip comprises a serializer-deserializer (SerDes) coupled to the transceiver (paragraphs 0148-0150). Further, it would be obvious to use a plurality of through silicon vias (TSV) coupling the SerDes with the transceiver in order to conserve space and reduce the size of the package.
Regarding claim 35, the proposed combination of Liff, Kulkarni, Yoo and Harris teaches the claimed invention except for a Universal Chiplet Interconnect Express (UCIe) interface coupled to the SerDes. However, numerous different interfaces, including a Universal Chiplet Interconnect Express (UCIe) interface are well-known and commonly used in the art of integrated circuit devices and as such, one having ordinary skill in the art at the time of the invention would have found it obvious to use a Universal Chiplet Interconnect Express (UCIe) interface for the purpose of increasing the versatility of the package.
Response to Arguments
Applicant's arguments, filed December 18, 2025, with respect to claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRIS H CHU whose telephone number is (571)272-8655. The examiner can normally be reached on Mon-Fri 9AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached on 571-272-239797. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Any inquiry of a general or clerical nature should be directed to the Technology Center 2800 receptionist at telephone number (571) 272-1562.
Chris H. Chu
/CHRIS H CHU/Primary Examiner, Art Unit 2874 March 13, 2026