DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/27/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/28/26 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under U.S.C. 103 as being unpatentable over Lee et al.; US 2019/0379204 A1; 01/2019 in view of Song et al.; US 2021/0175226 A1; 08/2020, Takasu; US 2009/0050967 A1; 08/2008, and Syue et al.; US 12622237 B2; 01/2023
Claim 1: Lee discloses an ESD protection circuit, comprising: an off transistor, which comprises: a semiconductor substrate ( Fig. 3 #200 ) of a first conductivity type (Fig. 3 P-sub ); a well region of the second conductivity type ( Fig. 3 #219a n-well ), formed in an upper portion of the semiconductor substrate ( as shown in Fig. 3 ); a drain region of a first conductivity type ( Fig. 3 #235a ), formed in an upper portion of the well region ( as shown in Fig. 3 ) and having an impurity concentration higher than an impurity concentration of the well region ( Fig. 3 #235a is shown as p+ ); a pair of source regions ( Fig. 3 #235b and #235d ) of the first conductivity type ( Fig. 3 #235b and #235d are P+ ), formed spaced apart ( as shown in Fig. 3 ) on both sides of the drain region ( Fig 3 #235a ) in the upper portion of the well region ( as shown in Fig. 2 ) and having an impurity concentration higher than the impurity concentration of the well region ( Fig. 3 #235b is P+ ); a gate insulating film ( Fig. 3 #225 ) formed on a surface of the semiconductor substrate ( Fig. 3 #200 ) between the drain region ( Fig. 3 #235a ) and each of the pair of the source regions ( Fig. 3 #235b and #235d ); a gate electrode ( Fig. 3 #230a ) formed on a surface of the gate insulating film (as shown in Fig. 3 ).
Lee does not appear to disclose a high-concentration region of the second conductivity type, formed in the upper portion of the well region to be in contact with at least the drain region near a corner portion of a channel region and having an impurity concentration higher than the impurity concentration of the well region, a peripheral wall portion, formed around the drain region, the pair of source regions, and the gate electrode to separate a region for forming the off transistor, wherein the peripheral wall portion is formed by implanting an impurity of the first conductivity type; and an insulating film, formed between an inner circumference of the peripheral wall portion and the drain region, and formed adjacent to an outer circumference of the peripheral wall portion.
However, Song discloses, a high-concentration region of the second conductivity type ( Fig. 1 #123 ), formed in the upper portion of the well region ( Fig. 1 second N-well region #122 ) to be in contact with at least the drain region ( Fig. 1 D1 ) near a corner portion of a channel region ( area under Fig. 1 gate dielectric layer #152 ) and having an impurity concentration higher than the impurity concentration of the well region ( [0032] the doping concentration of the first impurity region #123 may be greater than the doping concentration of the second N-well region #122 ).
Song does not appear to disclose a peripheral wall portion, formed around the drain region, the pair of source regions, and the gate electrode to separate a region for forming the off transistor, wherein the peripheral wall portion is formed by implanting an impurity of the second conductivity type; and an insulating film, formed between an inner circumference of the peripheral wall portion and the drain region, and formed adjacent to an outer circumference of the peripheral wall portion.
Takasu discloses a peripheral wall portion ( Fig. 1 #504 ), formed around the drain region ( Fig. 1 #503 ), the pair of source regions ( Fig. 1 #501), and the gate electrode ( Fig. 1 #502 ) to separate a region for forming the off transistor ( as shown in Fig. 1 ), and an insulating film ( [0020] A shallow trench structure is used for insulation from other elements, and a perimeter of the transistor is surrounded by a shallow trench isolation region #504 ), formed between an inner circumference of the peripheral wall portion and the drain region, and formed adjacent to an outer circumference of the peripheral wall portion ( a Shallow Trench Isolation (STI) includes an insulating film as its primary component).
Takasu does not appear to disclose wherein the peripheral wall portion is formed by implanting an impurity of the second conductivity type.
However, Syue teaches the peripheral wall portion ( Fig. 1A #52 ) is formed by implanting an impurity of the second conductivity type ( Col. 7 lines 9-11 P-well 44A and p-well 44B extend along the y-direction from p-doped region 52 to buried layer 30 );
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Syue with Lee, Song, and Takasu to implement a peripheral wall portion, formed around the drain region, the pair of source regions, and the gate electrode to separate a region for forming the off transistor, wherein the peripheral wall portion is formed by implanting an impurity of the second conductivity type; and an insulating film, formed between an inner circumference of the peripheral wall portion and the drain region, and formed adjacent to an outer circumference of the peripheral wall portion because these components provide isolation, protection, and controlled current flow during an electrostatic discharge event.
Claim 3: Lee, Song, Takasu, and Syue disclose the ESD protection circuit according to claim 1 ( as discussed above).
Neither Lee nor Takasu nor Syue appear to disclose the high-concentration region is formed in an entire area of the upper portion of the well region.
However, Song teaches the high-concentration region ( Fig. 1 #123) is formed in an entire area of the upper portion of the well region ( Fig. 1 #122 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Lee, Takasu, and Syue to implement the high-concentration region is formed in an entire area of the upper portion of the well region because this is a key design technique used to manage the trigger voltage, holding voltage, and overall robustness of the ESD device.
Claim 2 is rejected under U.S.C. 103 as being unpatentable over Lee et al.; US 2019/0379204 A1; 01/2019 in view of Song et al.; US 2021/0175226 A1; 08/2020, Takasu; US 2009/0050967 A1; 08/2008 and Syue et al.; US 12622237 B2; 01/2023 as it relates to claim 1 and further in view of Risaki; US 2017/0221878 A1; 07/2015
Claim 2: Lee, Song, Takasu, and Syue disclose the ESD protection circuit according to claim 1 (as discussed above).
Neither Lee nor Song nor Takasu nor Syue appear to disclose the high-concentration region is formed in an entire area of the channel.
However, Risaki teaches the high-concentration region is formed in an entire area of the channel ( Fig. 3 P+ region #22 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Risaki with Lee, Song, Takasu, and Syue to implement the high-concentration region is formed in an entire area of the channel because this approach promotes uniform current distribution.
Response to Amendment
The amendment filed 03/27/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: in Claim 1 "a well region of the first conductivity type," "a drain region of the second conductivity type," "a pair of source regions of the second conductivity type," "a high-concentration region of the first conductivity type," and "peripheral wall portion is formed by implanting an impurity of the first conductivity type" are not supported in the specification. For the well region, in paragraph [0010] “The ESD protection circuit 100 includes a drain region 6 in an upper portion A of a P-type well region 9 formed on a surface of an N-type semiconductor substrate 7” which is the second conductivity type. For the drain region, in paragraph [0006] “a drain region of the first conductivity type.” For the source regions, in paragraph [0006] “a source region of the first conductivity type.” For the high-concentration in the well region, in paragraph [0006] “a high-concentration region of the second conductivity type, formed in the upper portion of the well region to be in contact with at least the drain region.” For the peripheral wall portion, in paragraph [0011] “The peripheral wall portion 3 is formed by implanting a P-type impurity into a part of the upper portion A of the well region 9 to a high concentration” which is the second conductivity type.
Applicant is required to cancel the new matter in the reply to this Office Action.
Applicant’s arguments, see pages 4 - 10 of remarks, filed 03/27/2026, with respect to the rejection of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Syue.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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