Prosecution Insights
Last updated: July 17, 2026
Application No. 18/190,970

THERMAL PROCESSING CHAMBER STATE BASED ON THERMAL SENSOR READINGS

Non-Final OA §103
Filed
Mar 28, 2023
Examiner
LAZO, THOMAS E
Art Unit
3745
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Applied Materials Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1187 granted / 1369 resolved
+16.7% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
38 currently pending
Career history
1392
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.0%
+15.0% vs TC avg
§102
31.5%
-8.5% vs TC avg
§112
4.7%
-35.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1369 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 8-11, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sekiguchi et al. (JP2005307239A) in view of Tsutsui (20210166121). Sekiguchi et al. discloses (claim 1) a method of characterizing thermal processing chambers by causing a thermal processing chamber 133 to execute a process, wherein the process causes a temperature in the thermal processing chamber to vary during the process (heater 146 causes temperature to vary in chamber 133), causing temperature measurements to be recorded by one or more temperature sensors in the thermal processing chamber during the process (paragraph [0050] “…Data on the manufacturing status of the semiconductor substrates includes…substrate heater temperature…”); and determining whether the manufacturing device is normal based on the parameter changes such as the temperature changes of the substrate while forming the material film (see paragraphs [0034]-[0035], [0050]-[0052] and figures 1, 9). Sekiguchi et al. does not discloses deriving temperature rate-of-change data from the temperature measurements; providing the temperature rate-of-change data to a model that is configured to receive the temperature rate-of-change data as an input and provide an output that predicts how well a result of a thermal deposition process executed in the thermal processing chamber will match a target result, receiving the output from the model that predicts how well the result of the thermal deposition process will match a target result; and characterizing the thermal processing chamber based on the output from the model. Tsutsui teaches for a method of characterizing a semiconductor manufacturing process by a predicting device 160 and that there is (claim 1) deriving temperature rate-of-change data from the temperature measurements 140_n (paragraph [0202] “….temperature data…”, providing the temperature rate-of-change data to a model (paragraph [0045] “…(correct answer data, or ground truth data)…”) that is configured to receive the temperature rate-of-change data as an input and provide an output that predicts how well a result of a thermal deposition process executed in the thermal processing chamber will match a target result (paragraph [0045]) “…The quality indicator is information representing a result (quality) of the semiconductor manufacturing process…”), receiving the output from the model that predicts how well the result of the thermal deposition process will match a target result, and characterizing the thermal processing chamber based on the output from the model for the purposes of more accurately predicting replacement time for parts, maintenance timing, and/or process adjustments based on age/use of equipment. See Tsutsui paragraphs [0045]-[0050] and [0202]. Since Sekiguchi et al. and Tsutsui are both in the same field of endeavor the purpose disclosed by Tsutsui would have been recognized in the pertinent art of Sekiguchi et al. It would have been obvious at a time before the invention was effectively filed to a person having ordinary skill in the art to modify the method of Sekiguchi et al. to include the steps of deriving temperature rate-of-change data from the temperature measurements; providing the temperature rate-of-change data to a model that is configured to receive the temperature rate-of-change data as an input and provide an output that predicts how well a result of a thermal deposition process executed in the thermal processing chamber will match a target result, receiving the output from the model that predicts how well the result of the thermal deposition process will match a target result; and characterizing the thermal processing chamber based on the output from the model for the purposes of more accurately predicting replacement time for parts, maintenance timing, and/or process adjustments based on age/use of equipment. Regarding claim 2, Tsutsui further teaches before providing the temperature rate-of-change data to the model, training the model (Fig. 14, paragraphs [0045, [0135], training unit 161), wherein training the model comprises: receiving training temperature rate-of-change data (Fig. 14, S1401, time series data set) from a plurality of executions of the process executed by one or more thermal processing chambers A,B,C, receiving training results of the thermal deposition process measured from substrates on which the thermal deposition process was executed by the one or more thermal processing chambers (Fig. 14, S1401), generating training data based on the training temperature rate-of-change data that is labeled using the training results of the thermal deposition process; executing a supervised learning algorithm (machine learning) to train the model using the training data (Fig. 14, S1402). Regarding claim 3, Sekiguchi et al. further discloses that the one or more thermal processing chambers 133 and the thermal processing chamber are a same chamber 133; and characterizing the thermal processing chamber 133 comprises characterizing whether a current performance of the thermal processing chamber 133 matches previous performances of the thermal processing chamber (paragraphs [0027]-[0028], “…a data primary arrangement device is configured to monitor to determine whether the time from a first state to a preset second state of a first parameter of the manufacturing device is outside a first set range to detect a malfunction of the manufacturing device…”). Regarding claim 4, Tsutsui further teaches that the training temperature rate-of-change data and the training results are received prior to a preventive maintenance of the thermal processing chamber 133 wherein at least a portion of the thermal processing chamber is disassembled, at least one component of the thermal processing chamber is replaced (maintenance), and the thermal processing chamber is reassembled; and the thermal processing chamber is characterized based on the output from the model after the preventive maintenance is completed (paragraph [0132] and figure 13: the inference unit (162) can be applied to a chamber before maintenance and to the same chamber after the maintenance). Regarding claim 8, Sekiguchi et al. and Tsutsui further discloses a system comprising one or more processors (Sekiguchi et al. – 2, Tsutsui – (paragraph [0007]) and one or more memory devices comprising instructions (figure 4) that, when executed by the one or more processors, cause the one or more processors to perform operations comprising the method disclosed and taught by Sekiguchi et al. in view of Tsutsui, as applied to claim 1 above. Regarding claim 9, Sekiguchi et al. further discloses that the process comprises a plurality of process steps, wherein the plurality of process steps comprises a plurality of temperature setpoints such that a temperature in the thermal processing chamber moves between the plurality of temperature setpoints during the process (paragraphs [0027]-[0028], “…a data primary arrangement device is configured to monitor to determine whether the time from a first state to a preset second state of a first parameter of the manufacturing device is outside a first set range to detect a malfunction of the manufacturing device…”). Regarding claim 10, Sekiguchi et al. further discloses that the temperature rate-of-change data comprises an approximate slope of temperature transitions between the plurality of temperature setpoints (paragraphs [0034]-[0035]: the parameter changes such as the temperature changes of the substrate while forming the material film are collected). Regarding claim 11, Sekiguchi et al. further discloses that the temperature measurements comprise a time series of temperature readings from the one or more temperature sensors; and the temperature rate-of-change data comprises a calculated first derivative of the time series of temperature readings (paragraphs [0034]-[0035]: the parameter changes such as the temperature changes of the substrate while forming the material film are collected). Regarding claim 15, Sekiguchi et al. and Tsutsui further disclose one or more non-transitory computer-readable media (Sekiguchi et al. – 2, Tsutsui – (paragraph [0007]) comprising instructions (Fig. 4) that, when executed by one or more processors, cause the one or more processors to perform operations comprising the method disclosed and taught by Sekiguchi et al. in view of Tsutsui, as applied to claim 1 above. Regarding claim 16, Sekiguchi et al. and Tsutsui further disclose that the model is trained to model a thermal response of the thermal processing chamber when heat energy is added to the thermal processing chamber (see Sekiguchi et al. paragraph [0050] and figure 1: the data on the manufacturing situation such as the substrate heater temperature is collected) and see Tsutsui paragraphs [0045]-[0050], [0202] and figures 1, 9: the inference unit (162) infers the quality indicator based on the device state information and the time series data sets, wherein the time series data acquiring device may include the process data acquiring device that acquires various process data, such as temperature data). Regarding claim 17, Sekiguchi et al. and Tsutsui further disclose the thermal response of the thermal processing chamber accounts for a thermal mass of the thermal processing chamber (see Sekiguchi et al. paragraph [0050] and figure 1: the data on the manufacturing situation such as the substrate heater temperature is collected) and see Tsutsui paragraphs [0045]-[0050], [0202] and figures 1, 9: the inference unit (162) infers the quality indicator based on the device state information and the time series data sets, wherein the time series data acquiring device may include the process data acquiring device that acquires various process data, such as temperature data). Regarding claim 18, Tsutsui further teaches that the output from the model comprises one or more scalar values that correspond to the one or more temperature sensors and that indicate a confidence level of how well the result of the thermal deposition process will match the target result for each of the one or more temperature sensors (paragraph [0045] and figure 1: the quality indicator is information representing the result (quality) of the semiconductor manufacturing process). Regarding claim 19, Tsutsui further teaches characterizing the thermal processing chamber based on the output from the model comprises: characterizing the thermal processing chamber as not matching one or more thermal processing chambers used to train the model; and identifying a component of the thermal processing chamber as a cause for the thermal processing chamber not matching the one or more chambers (paragraph [0130] and figure 13: a predicting section (1350) specifies the value of the device state information, in which the quality indicator acquired for each of the values of the device state information first exceeds the predetermined threshold (1352), and also predicts replacement time of each part in the semiconductor manufacturing device based on the specified value of the device state information and a current value of the device state information). Regarding claim 20, Tsutsui further teaches that the operations further comprise providing a tolerance to the model that indicates an allowed deviation from the target result (paragraph [0130] and figure 13: a predicting section (1350) specifies the value of the device state information, in which the quality indicator acquired for each of the values of the device state information first exceeds the predetermined threshold (1352), and also predicts replacement time of each part in the semiconductor manufacturing device based on the specified value of the device state information and a current value of the device state information). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiguchi et al. (JP2005307239A) and Tsutsui (20210166121), as applied to claim 1 above, further in view of Circuits Today “Chemical Vapor Deposition (CVD). Sekiguchi et al. discloses all of the claimed subject matter except for specifically disclosing depositing an epitaxial layer on a substrate (chemical vapor deposition (CVD)). See Sekiguchi et al. paragraphs [0021]-[0024] and Figures 12 and 13. Circuits Today teaches for (claim 5) a special chemical vapor deposition of an epitaxial layer on a substrate for the purposes of controlling the doping profile. See Circuits Today pages 1-3. Since Sekiguchi et al., Tsutsui, and Circuits Today are all in the same field of endeavor the purpose disclosed by Circuits Today would have been recognized in the pertinent art of Sekiguchi et al. It would have been obvious at a time before the invention was effectively filed to a person having ordinary skill in the art to further modify the layer deposited on the substrate to be an epitaxial layer for the purposes of controlling the doping profile. Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sekiguchi et al. (JP2005307239A) and Tsutsui (20210166121), as applied to claim 1 above, further in view of Ravi et al. (20090016406). Sekiguchi et al. discloses all of the claimed subject matter except for causing a temperature to vary in the thermal processing chamber without active precursors flowing into the thermal processing chamber such that the temperature varies in the thermal processing chamber without depositing a layer on a substrate and an inert gas flowing into the thermal processing chamber in place of the active precursors. Ravi et al. teaches for a method of monitoring an calibrating thermal processing chambers by causing a thermal processing chamber to execute a process, wherein the process causes a temperature in the thermal processing chamber to vary during the process and that there is (claim 6) causing a temperature to vary in the thermal processing chamber without active precursors flowing into the thermal processing chamber such that the temperature varies in the thermal processing chamber without depositing a layer on a substrate (paragraph [0030] “…a test process for a chemical vapor deposition chamber may include setting the chamber temperature following the designated chemical vapor deposition recipe, setting chamber pressure similar to the designated chemical vapor deposition, and flowing one or more inert gases to the chamber, instead of reactant gases specified by the deposition recipe…”) and (claim 7) an inert gas flowing into the thermal processing chamber in place of the active precursors (paragraph [0030], “…flowing one or more inert gases to the chamber, instead of reactant gases specified by the deposition recipe…”) for the purposes of more precisely conducting non-destructive temperature measurements to improve the quality of the finished device. Since Sekiguchi et al., Tsutsui, and Ravi et al. are all in the same field of endeavor the purpose disclosed by Ravi et al. would have been recognized in the pertinent art of Sekiguchi et al. It would have been obvious at a time before the invention was effectively filed to a person having ordinary skill in the art to further modify the method of Sekiguchi et al. to include causing a temperature to vary in the thermal processing chamber without active precursors flowing into the thermal processing chamber such that the temperature varies in the thermal processing chamber without depositing a layer on a substrate and an inert gas flowing into the thermal processing chamber in place of the active precursors for the purposes of more precisely conducting non-destructive temperature measurements to improve the quality of the finished device. Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sekiguchi et al. (JP2005307239A) and Tsutsui (20210166121), as applied to claim 1 above, further in view of Harada et al. (JP4220378). Sekiguchi et al., as modified, discloses all of the claimed subject matter except that the thermal processing chamber comprises a quartz dome above a susceptor, and a temperature sensor in the one or more temperature sensors is configured to measure a temperature of the quartz dome, the thermal processing chamber comprises a susceptor, a first temperature sensor in the one or more temperature sensors is configured to measure a temperature underneath the susceptor, and a second temperature sensor in the one or more temperature sensors is configured to measure a temperature of a substrate on top of the susceptor, and the thermal processing chamber comprises a liner, and a first temperature sensor in the one or more temperature sensors is configured to measure a temperature of the liner. Harada et al. teaches for a method of monitoring an calibrating thermal processing chambers by causing a thermal processing chamber to execute a process, wherein the process causes a temperature in the thermal processing chamber to vary during the process and that (claim 12) the thermal processing chamber comprises a quartz dome 4 above a susceptor 2, and a temperature sensor (not shown) in the one or more temperature sensors is configured to measure a temperature of the quartz dome 4, (claim 13) the thermal processing chamber comprises a susceptor 2, a first temperature sensor (not shown) in the one or more temperature sensors is configured to measure a temperature underneath the susceptor 2, and a second temperature sensor (not shown) in the one or more temperature sensors is configured to measure a temperature of a substrate on top of the susceptor 2, and (claim 14) the thermal processing chamber comprises a liner 2A, and a first temperature sensor (not shown) in the one or more temperature sensors is configured to measure a temperature of the liner (see Harada page 5, lines 31-47 and figures 1-2: a temperature of a shower head (4), a temperature of an inner wall surface of a processing chamber (1), and a temperature of a lower electrode (2) are used as a temperature in the processing chamber (1)) for the purposes of processing semiconductor wafers Since Sekiguchi et al, Tsutsui, and Harada et al. are all in the same field of endeavor the purpose disclosed by Harada et al. would have been recognized in the pertinent art of Sekiguchi et al. It would have been obvious at a time before the invention was effectively filed to a person having ordinary skill in the art to further modify the method of Sekiguchi et al. such that the thermal processing chamber comprises a quartz dome above a susceptor, and a temperature sensor in the one or more temperature sensors is configured to measure a temperature of the quartz dome, the thermal processing chamber comprises a susceptor, a first temperature sensor in the one or more temperature sensors is configured to measure a temperature underneath the susceptor, and a second temperature sensor in the one or more temperature sensors is configured to measure a temperature of a substrate on top of the susceptor, and the thermal processing chamber comprises a liner, and a first temperature sensor in the one or more temperature sensors is configured to measure a temperature of the liner for the purposes of processing semiconductor wafers. Prior Art Prior art made of record but not relied upon is considered pertinent to Applicant's disclosure for showing other methods of characterizing thermal processing chambers by causing a thermal processing chamber to execute a process, wherein the process causes a temperature in the thermal processing chamber to vary during the process. Contact Information Any inquiry concerning this communication or earlier communication from the examiner should be directed to Thomas Lazo whose telephone number is (571) 272-4818. The examiner can normally be reached on Monday-Friday from 8:00 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Nathaniel Wiehe, can be reached on (571) 272-8648. The fax phone number for this Group is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS E LAZO/Primary Examiner, Art Unit 3745 February 5, 2026
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Prosecution Timeline

Mar 28, 2023
Application Filed
Feb 05, 2026
Non-Final Rejection (signed) — §103
Apr 08, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+8.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1369 resolved cases by this examiner. Grant probability derived from career allowance rate.

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