Prosecution Insights
Last updated: July 17, 2026
Application No. 18/191,177

SEMICONDUCTOR DEVICE AND POWER DEVICE

Final Rejection §102
Filed
Mar 28, 2023
Priority
Mar 29, 2022 — JP 2022-053039
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seiko Epson Corporation
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
727 granted / 1071 resolved
At TC average
Strong +30% interview lift
Without
With
+29.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
80 currently pending
Career history
1176
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
76.9%
+36.9% vs TC avg
§102
12.4%
-27.6% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1071 resolved cases

Office Action

§102
DETAILED ACTION This office action is in response to amendment filed 2/2/2026. Claims 1-12 are pending. Claim 12 is new. Claims 1, 10 and 11 have been amended. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Zhu et al. US 2022/0102559 A1 (Zhu). PNG media_image1.png 594 1352 media_image1.png Greyscale In re claim 1, Zhu discloses (e.g. FIG. 14) a semiconductor device comprising: a first semiconductor portion 1005 and a second semiconductor portion 1009 having the same conductivity type (¶ 36,38) and arranged along a first direction (vertical direction); a third semiconductor portion (lower portion of 1007) provided between the first semiconductor portion 1005 and the second semiconductor portion 1009 and having a lower impurity concentration than the first semiconductor portion 1005 and the second semiconductor portion 1009 (1007 is lightly doped, while 1005 and1009 are heavily doped, ¶ 36,38); a fourth semiconductor portion (upper portion of 1007) provided between the second semiconductor portion 1009 and the third semiconductor portion (lower portion of 1007) and having a lower impurity concentration than the first semiconductor portion 1005 and the second semiconductor portion 1009 (1007 is lightly doped, while 1005 and 1009 are heavily doped, ¶ 36,38); a gate insulating layer (lower portion of 1031) and a gate electrode 1033 that overlap with the third semiconductor portion (lower portion of 1007) when viewed in a second direction (horizontal direction), the second (horizontal) direction intersecting the first (vertical) direction, a part of the first semiconductor portion 1005 overlapping with a part of the gate insulating layer (lower portion of 1031) in the second (horizontal) direction; and a dielectric portion (upper portion of 1031) that overlaps with the fourth semiconductor portion (upper portion of 1007) when viewed in the second (horizontal) direction, wherein the dielectric portion (upper portion of 1031) is formed of a material (e.g. HfO2, ¶ 64) having a larger band gap and a larger relative permittivity than a material forming the fourth semiconductor portion (upper portion of 1007 formed of silicon, ¶ 38) (A high-k dielectric material such as HfO2 necessarily has larger band gap than a semiconductor material due their inherent electrical properties. Furthermore, dielectric material HfO2 has a relative permittivity of ~25 which is larger than a relative permittivity of silicon at ~12) and a depletion layer is formed at the fourth semiconductor portion (upper portion of 1007) when a predetermined voltage is applied to the gate electrode 1033 (the transistor comprising same conductive type source, drain, and channel (¶ 36,38); as such, a depletion layer is necessarily formed when adequate voltage is applied to the gate electrode). In re claim 2, Zhu discloses (e.g. FIG. 14) wherein the first semiconductor portion 1005, the third semiconductor portion (lower portion of 1007), and the fourth semiconductor portion (upper portion of 1007) are stacked in the first direction to form a column portion. In re claim 3, Zhu discloses (e.g. FIG. 14) wherein the gate insulating layer (lower portion of 1031) surrounds the third semiconductor portion (lower portion of 1007) when viewed from the first (vertical) direction and the gate electrode 1033 surrounds the gate insulating layer (lower portion of 1031). In re claim 4, Zhu discloses (e.g. FIG. 14) wherein the first semiconductor portion 1005 constitutes a source region (¶ 34) and the second semiconductor portion 1009 constitutes a drain region (¶ 34). In re claim 5, Zhu discloses (e.g. FIG. 14) wherein the dielectric portion (upper portion of 1031) is composed of transition metal oxide (¶ 64). In re claim 6, Zhu discloses (e.g. FIG. 14) wherein the dielectric portion (upper portion of 1031) is composed of hafnium oxide (¶ 64). In re claim 7, Zhu discloses (e.g. FIG. 14) wherein the gate insulating layer (lower portion of 1031) is formed of a material (e.g. HfO2, ¶ 64) having a larger band gap and a larger relative permittivity than a material forming the third semiconductor portion (lower upper portion of 1007 formed of silicon, ¶ 38). A high-k dielectric material such as HfO2 necessarily has larger band gap than a semiconductor material due their inherent electrical properties. Furthermore, dielectric material HfO2 has a relative permittivity of ~25 which is larger than a relative permittivity of silicon at ~12. In re claim 8, Zhu discloses (e.g. FIG. 14) wherein the gate insulating layer (lower portion of 1031) is composed of transition metal oxide (¶ 64). In re claim 9, Zhu discloses (e.g. FIG. 14) wherein the gate insulating layer (lower portion of 1031) is composed of hafnium oxide (¶ 64). In re claim 10, Zhu discloses (FIG. 14) 1003 is a heavily doped layer (¶ 32). In an alternative interpretation, the first semiconductor portion correspond to 1009, the second semiconductor portion correspond to the combination of 1003+1005, the third semiconductor portion correspond to an upper portion of 1007, and the fourth semiconductor portion corresponds to a lower portion of 1007. See FIG. 14 annotated below. PNG media_image2.png 594 1359 media_image2.png Greyscale As such, Zhu discloses (e.g. FIG. 14) further comprising an electrode 1039-2 that overlaps with the second semiconductor portion 1003+1005 when viewed in the first (vertical) direction, wherein the second semiconductor portion 1003+1005 overlaps with the dielectric portion (in this case, lower portion of 1031 surrounding lower portion of 1007) in the first (vertical) direction (lower portion of dielectric 1031 having laterally extending portion that overlaps 1003 in the vertical direction). In re claim 11, Zhu discloses (e.g. FIG. 14) a power device comprising: a first semiconductor portion 1005 and a second semiconductor portion 1009 having the same conductivity type (¶ 36,38) and arranged along a first direction (vertical direction); a third semiconductor portion (lower portion of 1007) provided between the first semiconductor portion 1005 and the second semiconductor portion 1009 and having a lower impurity concentration than the first semiconductor portion 1005 and the second semiconductor portion 1009 (1007 is lightly doped, while 1005 and1009 are heavily doped, ¶ 36,38); a fourth semiconductor portion (upper portion of 1007) provided between the second semiconductor portion 1009 and the third semiconductor portion (lower portion of 1007) and having a lower impurity concentration than the first semiconductor portion 1005 and the second semiconductor portion 1009 (1007 is lightly doped, while 1005 and 1009 are heavily doped, ¶ 36,38); a gate insulating layer (lower portion of 1031) and a gate electrode 1033 that overlap with the third semiconductor portion (lower portion of 1007) when viewed in a second direction (horizontal direction), the second (horizontal) direction intersecting the first (vertical) direction, a part of the first semiconductor portion 1005 overlapping with a part of the gate insulating layer (lower portion of 1031) in the second (horizontal) direction; and a dielectric portion (upper portion of 1031) that overlaps with the fourth semiconductor portion (upper portion of 1007) when viewed in the second (horizontal) direction, wherein the dielectric portion (upper portion of 1031) is formed of a material (e.g. HfO2, ¶ 64) having a larger band gap and a larger relative permittivity than a material forming the fourth semiconductor portion (upper portion of 1007 formed of silicon, ¶ 38) (A high-k dielectric material such as HfO2 necessarily has larger band gap than a semiconductor material due their inherent electrical properties. Furthermore, dielectric material HfO2 has a relative permittivity of ~25 which is larger than a relative permittivity of silicon at ~12) and a depletion layer is formed at the fourth semiconductor portion (upper portion of 1007) when a predetermined voltage is applied to the gate electrode 1033 (the transistor comprising same conductive type source, drain, and channel (¶ 36,38); as such, a depletion layer is necessarily formed when adequate voltage is applied to the gate electrode). In re claim 12, Zhu discloses (e.g. FIG. 14) a semiconductor device comprising: a first semiconductor portion 1005 and a second semiconductor portion 1009 having the same conductivity type (¶ 36,38) and arranged along a first direction (vertical direction); a third semiconductor portion (lower portion of 1007) provided between the first semiconductor portion 1005 and the second semiconductor portion 1009 and having a lower impurity concentration than the first semiconductor portion 1005 and the second semiconductor portion 1009 (1007 is lightly doped, while 1005 and1009 are heavily doped, ¶ 36,38); a fourth semiconductor portion (upper portion of 1007) provided between the second semiconductor portion 1009 and the third semiconductor portion (lower portion of 1007) and having a lower impurity concentration than the first semiconductor portion 1005 and the second semiconductor portion 1009 (1007 is lightly doped, while 1005 and 1009 are heavily doped, ¶ 36,38); a gate insulating layer (lower portion of 1031) and a gate electrode 1033 that overlap with the third semiconductor portion (lower portion of 1007) when viewed in a second direction (horizontal direction), the second (horizontal) direction intersecting the first (vertical) direction; and a dielectric portion (upper portion of 1031) that overlaps with the fourth semiconductor portion (upper portion of 1007) when viewed in the second (horizontal) direction, the gate electrode 1033 overlapping with the dielectric portion (upper portion of 1031 having a horizontal portion) in the first (vertical direction, wherein the dielectric portion (upper portion of 1031) is formed of a material (e.g. HfO2, ¶ 64) having a larger band gap and a larger relative permittivity than a material forming the fourth semiconductor portion (upper portion of 1007 formed of silicon, ¶ 38) (A high-k dielectric material such as HfO2 necessarily has larger band gap than a semiconductor material due their inherent electrical properties. Furthermore, dielectric material HfO2 has a relative permittivity of ~25 which is larger than a relative permittivity of silicon at ~12) and a depletion layer is formed at the fourth semiconductor portion (upper portion of 1007) when a predetermined voltage is applied to the gate electrode 1033 (the transistor comprising same conductive type source, drain, and channel (¶ 36,38); as such, a depletion layer is necessarily formed when adequate voltage is applied to the gate electrode). Response to Arguments Applicant's arguments filed 2/2/2026 have been fully considered but they are not persuasive. Regarding Wang, Applicant argues the first semiconductor portion S1 does not overlap with the gate insulating layer 150 in the horizontal direction (Remark, pages 7-8). This is not persuasive. The “second direction” as recited in the claim only need to “intersect” the first direction. If the first direction is the vertical direction. The second direction can be any direction that is non-parallel to the first direction. As such, Wang teaches a “second direction” that intersect the first vertical direction at an angle less than 90°. As viewed from such angled “second direction”, a part of the gate insulating layer (lower portion of 150) does overlap with a part of the first third semiconductor S1. Applicant’s other arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
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Prosecution Timeline

Mar 28, 2023
Application Filed
Nov 05, 2025
Non-Final Rejection mailed — §102
Feb 02, 2026
Response Filed
Apr 07, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.6%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1071 resolved cases by this examiner. Grant probability derived from career allowance rate.

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