DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,4 -11,13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US 20210265275 A1) in view of Pietambaram et al. (US-20220278032 A1; Pie) and further in view of Pietambaram et al. (US 20200312767 A1; Pie2).
Regarding claim 1, Rubin discloses a semiconductor package comprising: a substrate (Fig. 5B,550-530; ¶74-76) including a first redistribution member (Fig. 5B, 530; ¶76) including a first redistribution layer, and including a first surface (top) and a second surface (bottom) opposing each other, an interconnection chip (Fig. 5B, 110; ¶43-44) below the second surface and including an interconnection circuit (Fig. 5B, not labeled; ¶43-44) electrically connected to the first redistribution layer, a via structure (Fig. 5B, 514; ¶74-78) disposed around the interconnection chip and electrically connected to the first redistribution layer, an encapsulant (Fig. 5B, 522; ¶74-78) between the second surface and the interconnection chip and the via structure…, a first pillar (Fig. 5B, 526; ¶74-78) passing through the encapsulant to electrically connect the first redistribution layer and the interconnection circuit, the first pillar having a first height, a second pillar (Fig. 5B, 524; ¶74-78) passing through the encapsulant to electrically connect the first redistribution layer and the wiring layer of the via structure (Fig. 5B, 514; ¶74-78), and connection bumps (Fig. 5B, 580; ¶74-78) below the interconnection chip and the via structure (Fig. 5B, 514; ¶74-78); and first and second chip structures (Fig. 5B, 140/150; ¶74-78) on the first surface (top) of the first redistribution member and electrically connected to the first redistribution layer, wherein the first pillar (cylinder) and the second pillar (square) have different shapes, wherein the first pillar (Fig. 5B, 526; ¶74-78) has a shape in which an upper width adjacent to the second surface and a lower width adjacent to the interconnection chip are substantially the same…
Rubin is silent on, wherein a wiring layer of the via structure is embedded in the encapsulant, such that the second pillar has a second height different from the first height, and wherein the second pillar has a tapered shape in which a width decreases towards the via structure.
Pie discloses a semiconductor package comprising an encapsulant (Fig. 1A, 132; ¶24) filling a space between the second surface and the interconnection chip and the via structure, wherein a wiring layer (Fig. 1A, 136; ¶22) of the via structure (Fig. 1A, 134; ¶22) is embedded in the encapsulant,
Pie2 discloses a second pillar (Fig. 2H, 242; ¶68) has a tapered shape in which a width decreases in a direction from the second surface (bottom) of a first redistribution member (Fig. 2H, 246; ¶68) toward a via structure. (Fig. 2H, 216; ¶57)
Applicants relative pillar height is due to the claimed wiring layer configuration, while the first pillar is in direct contact with the bridge. Rubin discloses the first pillar in direct contact with the bridge. Pie discloses the claimed wiring layer (pad) on a via structure. Therefore, when the claimed wiring layer is added to Rubin the relative pillar height is achieved.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add the wiring layer to the conductive via to increase the reliability the electrical connection with the pillars. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a tapered shape because the additional space created by tapering the wire may decrease wire-to-wire capacitance in the case where optimizing power consumption by the data bus is desirable. Also, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 4, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 1, wherein a width of an upper surface of the second pillar (Fig. 5B, 524; ¶74-78 Rubin) in contact with the second surface of the first redistribution member (Fig. 5B, 530; ¶76 Rubin) is greater than a width of an upper surface of the first pillar (Fig. 5B, 526; ¶74-78 Rubin) in contact with the second surface of the first redistribution member.
Regarding claim 5, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 1, wherein the first redistribution member (Fig. 5B, 530; ¶74-78 Rubin) further includes a dielectric layer (Fig. 5B, 532; ¶76 Rubin) and a redistribution via (Fig. 5B, 534/536; ¶76 Rubin) extending through the dielectric layer and connecting the first redistribution layer (Fig. 5B, 530; ¶76 Rubin) to the first pillar (Fig. 5B, 526; ¶74-78 Rubin) and the second pillar. (Fig. 5B, 524; ¶74-78 Rubin)
Regarding claim 6, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 5, wherein the second pillar (Fig. 2H, 242; ¶68 Pie2) has a width greater than a width of the redistribution via. (Fig. 2H, 248; ¶68 Pie2)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a wider pillar to increase the contact surface area. Also, changing the shape or proportions of the pillar will not produce any unexpected results and has not been shown to be critical. Where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 7, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 5, wherein the dielectric layer includes a photosensitive resin. ) (Fig. 2H, 246; ¶69 Pie2)
Pie2 discloses using a photo-imageable dielectric (PID) (Fig. 2H, 246; ¶69)
which is a resin material for a redistribution dielectric layer. Photo-imageable dielectric material is resin (See US-12388046-B2 column 5 line 10) .
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to us PID resins for using lasers to form vias.
Regarding claim 8, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 1, wherein the first and second chip structures (Fig. 5B, 140/150; ¶74-78 Rubin) are electrically connected to each other through the interconnection circuit (Fig. 5B, 110; ¶43-44 Rubin)
Regarding claim 9, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 1, wherein the first redistribution member (Fig. 5B, 530; ¶76 Rubin) includes first pad structures (Fig. 5B, not labeled on top surface connected to 536 ; ¶55 Rubin) on the first surface of the first redistribution member and electrically connected to the interconnection circuit (Fig. 5B, 110; ¶43-44 Rubin) through the first redistribution layer, and second pad structures (Fig. 5B, not labeled on top surface connected to 534 ; ¶55 Rubin) on the first surface of the first redistribution member and electrically connected to the via structure (Fig. 5B, 514; ¶74-78 Rubin) through the first redistribution layer, wherein the first (Fig. 5B, 140; ¶74-78 Rubin) and second chip (Fig. 5B, 150; ¶74-78 Rubin) structures are electrically connected to the interconnection circuit through the first pad structures.
Regarding claim 10, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 9, wherein a first spacing between adjacent ones of the first pad structures (Fig. 5B, not labeled on top surface connected to 536 ; ¶55 Rubin) is less than a second spacing between adjacent ones of the second pad structures. (Fig. 5B, not labeled on top surface connected to 534; ¶55 Rubin)
The pad structures will take on the pitch of the pillars.
Regarding claim 11, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 10, wherein the first spacing ranges from about 10 μm to about 60 μm, and the second spacing ranges from about 60 μm to about 100 μm.(¶52 Rubin)
Regarding claim 13, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 1, wherein the substrate further includes a second redistribution member (Fig. 5B, 300-1; ¶73 Rubin) disposed between the connection bumps, the interconnection chip (Fig. 5B, 110; ¶43-44 Rubin) and the via structure (Fig. 5B, 10; ¶37 Rubin), and including a second redistribution layer electrically connecting the via structure to the connection bumps.
Regarding claim 14, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 1, wherein the substrate further includes a connection member (Fig. 5B,500/510; ¶74-78 Rubin) including the via structure (Fig. 5B, 514; ¶74-78 Rubin) and an insulating layer (Fig. 5B, 502/512; ¶74-78 Rubin) on side surfaces of the via structure, and including a through-hole in which the interconnection chip (Fig. 5B, 110; ¶43-44,74-78 Rubin) is received.
Regarding claim 15, Rubin in view of Pie and Pie2 discloses a semiconductor package comprising: a substrate (Fig. 5B, 550-530; ¶74-78) including a first redistribution member (Fig. 5B, 530; ¶74-78) including a first surface (top) and a second opposite surface (bottom), and including a first redistribution layer, an interconnection chip (Fig. 5B, 110; ¶43-44,74-78) below the second surface and including an interconnection circuit electrically connected to the first redistribution layer, a via structure (Fig. 5B, 514; ¶74-78) disposed around the interconnection chip and electrically connected to the first redistribution layer, an encapsulant (Fig. 5B,522; ¶74-78) filling a space between the second surface of the first redistribution member and the interconnection chip and the via structure,… a first pillar (Fig. 5B, 526; ¶74-78) passing through the encapsulant to electrically connect the first redistribution layer and the interconnection circuit, the first pillar having a first height, a second pillar (Fig. 5B, 524; ¶74-78) passing through the encapsulant to electrically connect the first redistribution layer…of the via structure, and connection bumps (Fig. 5B, 580; ¶74-78) below the interconnection chip and the via structure; and first and second chip structures (Fig. 5B, 140/150; ¶74-78) on the first surface of the first redistribution member and electrically connected to the first redistribution layer,… wherein the first pillar has a shape in which an upper width adjacent to the second surface and a lower width adjacent to the interconnection chip are substantially the same,….
The interconnection chip 110 is slightly below the surface of 510 causing the first pillars to have a higher height than the second pillars.
Rubin is silent on, wherein a wiring layer of the via structure is embedded in the encapsulant, a second pillar electrically connect the … , wherein the first pillar and the second pillar have different heights from each other and wherein the second pillar has a shape in which an upper width adjacent to the second surface is greater than a lower width adjacent to the wiring layer.
Pie discloses a semiconductor package comprising an encapsulant (Fig. 1A, 132; ¶24) filling a space between the second surface and the interconnection chip and the via structure, wherein a wiring layer (Fig. 1A, 136; ¶22) of the via structure (Fig. 1A, 134; ¶22) is embedded in the encapsulant,
Pie2 discloses a second pillar (Fig. 2H, 242; ¶68) has a tapered shape in which a width decreases in a direction from the second surface (bottom) of a first redistribution member (Fig. 2H, 246; ¶68) toward a via structure. (Fig. 2H, 216; ¶57)
Applicants relative pillar height is due to the claimed wiring layer configuration, while the first pillar is in direct contact with the bridge. Rubin discloses the first pillar in direct contact with the bridge. Pie discloses the claimed wiring layer (pad) on a via structure. Therefore, when the claimed wiring layer is added to Rubin the relative pillar height is achieved.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add the wiring layer to the conductive via to increase the reliability the electrical connection with the pillars. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a tapered shape because the additional space created by tapering the wire may decrease wire-to-wire capacitance in the case where optimizing power consumption by the data bus is desirable. Also, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 16, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 15, but is silent on wherein the second height of the second pillar is smaller than the first height of the first pillar in a direction perpendicular to the second surface (bottom) of the first redistribution member.
Pie discloses a semiconductor package comprising an encapsulant (Fig. 1A, 132; ¶24) filling a space between the second surface and the interconnection chip and the via structure, wherein a wiring layer (Fig. 1A, 136; ¶22) of the via structure (Fig. 1A, 134; ¶22) is embedded in the encapsulant,
Applicants relative pillar height is due to the claimed wiring layer configuration, while the first pillar is in direct contact with the bridge. Rubin discloses the first pillar in direct contact with the bridge. Pie discloses the claimed wiring layer (pad) on a via structure. Therefore, when the claimed wiring layer is added to Rubin the relative pillar height is achieved.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add the wiring layer to the conductive via to increase the reliability the electrical connection with the pillars. Also, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 17, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 15, wherein an upper surface of the first pillar (Fig. 5B, 526; ¶74-78 Rubin) is substantially coplanar with an upper surface of the second pillar. (Fig. 5B, 524; ¶74-78 Rubin)
Regarding claim 18, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 15, wherein a width of an upper surface of the second pillar (Fig. 5B, 524; ¶74-78 Rubin) is greater than a width of an upper surface of the first pillar. (Fig. 5B, 526; ¶74-78 Rubin)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US 20210265275 A1) in view of Pietambaram et al. (US-20220278032 A1; Pie) , Pietambaram et al. (US 20200312767 A1; Pie2), and further in view of in view of Tsai et al. (US 20210391272 A1; Tsai).
Regarding claim 12, Rubin in view of Pie and Pie2 discloses the semiconductor package of claim 9, but is silent on wherein a width of the first pad structures is substantially the same as a width of the second pad structures.
Rubin discloses a plurality of pads but does not show them. Tsai discloses a package structure where analogous first and second pads (Fig. 3,location of 162; ¶69) on a top surface of substrate (Fig. 3, 140; ¶29), and connected to a via structure (Fig. 3, 120b’; ¶43) and interconnect chip (Fig. 3, 110’; ¶43) respectively are substantially the same width.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to make the pads all the same width to limit processing steps associated with forming pads of varied sizes.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US 20210265275 A1) in view of Pietambaram et al. (US-20220278032 A1; Pie) , and further in view of Hsu et al. (US 20210391284 A1; Hsu).
Regarding claim 19, Rubin discloses a semiconductor package comprising: a first redistribution member (Fig. 5B, 530; ¶74-78)
including a first surface (top) and an opposite second surface (bottom), and including a first redistribution layer; an interconnection chip (Fig. 5B, 110; ¶43-44,74-78)
below the second surface of the first redistribution member and including an interconnection circuit electrically connected to the first redistribution layer; a via structure (Fig. 5B, 514; ¶74-78) disposed around the interconnection chip and electrically connected to the first redistribution layer; an encapsulant (Fig. 5B,522; ¶74-78) including a first portion disposed between the second surface of the first redistribution member and the interconnection chip and the via structure and a second portion disposed on a side surface of the interconnection chip…; a first pillar (Fig. 5B, 526; ¶74-78) extending through the first portion of the encapsulant and electrically connecting the first redistribution layer and the interconnection circuit, the first pillar having a first height; a second pillar (Fig. 5B, 524; ¶74-78) passing through the first portion of the encapsulant and electrically connecting the first redistribution layer and the wiring layer of the via structure, …a second redistribution member (Fig. 5B, 540; ¶74-78) below the interconnection chip and the via structure and including a second redistribution layer (Fig. 5B, 542/544; ¶74-78) electrically connected to the via structure; connection bumps (Fig. 5B, 580; ¶74-78) below the second redistribution member and electrically connected to the second redistribution layer; and first and second chip structures (Fig. 5B, 140/150; ¶74-78) on the first surface of the first redistribution member and electrically connected to the first redistribution layer ,wherein the first pillar has a shape in which an upper width adjacent to the second surface and a lower width adjacent to the interconnection chip are the same, .
Rubin is silent on, wherein a wiring layer of the via structure is embedded in the encapsulant, such that the second pillar has a second height different from the first height, and wherein the second pillar has a shape in which an upper width adjacent to the second surface is greater than a lower width adjacent to the wiring layer. Rubin is silent on the second pillar including a tapered shape decreasing in width in a direction from the second surface of the first redistribution member toward the via structure.
Pie discloses a semiconductor package comprising an encapsulant (Fig. 1A, 132; ¶24) filling a space between the second surface and the interconnection chip and the via structure, wherein a wiring layer (Fig. 1A, 136; ¶22) of the via structure (Fig. 1A, 134; ¶22) is embedded in the encapsulant,
Hsu discloses a package structure comprising tapered second pillars. (Fig. 10, vertical 31 over via structure 10; ¶31,51)
Applicants relative pillar height is due to the claimed wiring layer configuration, while the first pillar is in direct contact with the bridge. Rubin discloses the first pillar in direct contact with the bridge. Pie discloses the claimed wiring layer (pad) on a via structure. Therefore, when the claimed wiring layer is added to Rubin the relative pillar height is achieved.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to add the wiring layer to the conductive via to increase the reliability the electrical connection with the pillars. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a tapered shape because the additional space created by tapering the wire may decrease wire-to-wire capacitance in the case where optimizing power consumption by the data bus is desirable. Also, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. (US 20210265275 A1) in view of in view of Pietambaram et al. (US-20220278032 A1; Pie), Hsu et al. (US 20210391284 A1; Hsu), and further in view of Hsu et al. (US 20210391271 A1; Hsu2).
Regarding claim 20, Rubin in view of Hsu discloses the semiconductor package of claim 19, wherein the first redistribution member (Fig. 5B, 530; ¶74-78) further includes a redistribution via (Fig. 5B, 534/536; ¶74-78) connecting the first redistribution layer to the first pillar(Fig. 5B, 526; ¶74-78) and the second pillar (Fig. 5B, 524; ¶74-78), but is silent on and a width of a lower surface of the second pillar in contact with the via structure is greater than a width of a lower surface of the redistribution via in contact with the second pillar.
Hsu2 discloses a package structure comprising a second pillar (Fig. 3, 52; ¶16) with a lower surface in contact with the via structure (Fig. 3, 103; ¶17) is greater than a width of a lower surface of the redistribution via (Fig. 3, vertical 61; ¶16) in contact with the second pillar.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have smaller rdl vias for making higher density redistribution structures.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./ Examiner, Art Unit 2899