DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
2. Applicant’s election without traverse of Species A with Sub-Species I, identified as encompassing claims 1-10 and 17-20 is acknowledged.
Upon detailed consideration claim 9 is directed towards non-elected species having at least “the width center line of the bit line is misaligned with the width center line of the bit line contact spacer” as seen for example in Fig. 9. Therefore claim 9 is also withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-3, 6-7, and 10 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Choi et al. (US 2021/0159113 A1), hereinafter as C1
6. Regarding Claim 1, C1 discloses a semiconductor memory device (see in particular Figs. 1A-F and [0097] “semiconductor memory device”) comprising:
a substrate (element 100, see [0073] “substrate 100”) including an active region (regions of element ACT, see [0073] “active portions ACT”) defined by a device isolation layer (layer of element 102, see [0073] “device isolation pattern 102”);
a bit line (element 135, see [0106] “the conductive wire 135 may be a bit line”) which is disposed on the substrate and extends in a first direction (see Fig. 1A y-axis direction, see [0084] “Each of the conductive wires 135 may be connected to the wire-plugs 130 arranged in the y-axis direction”);
a bit line contact (element 130, see [0084] “wire-plugs 130”) which is disposed between the bit line and the substrate and connects the bit line to the active region (see Fig. 1B);
a bit line spacer (element 170, see [0085] “spacer structure 170”) which extends along a sidewall of the bit line (see Fig. 1B); and
a bit line contact spacer (element 127, see [0083] “insulating spacer 127”) which extends along a sidewall of the bit line contact and does not extend along the sidewall of the bit line (see Fig. 1B)
7. Regarding Claim 2, C1 discloses the semiconductor memory device of claim 1, further comprising:
a storage contact (element 120, see [0080] “conductive pad 120”) disposed on the substrate; and
a storage pad (element 160, see [0085] “Contact plugs 160”) disposed on the storage contact (see Fig. 1B),
wherein the bit line contact spacer is disposed between the bit line contact and the storage contact (see Fig. 1B).
8. Regarding Claim 3, C1 discloses the semiconductor memory device of claim 2, wherein an upper surface of the bit line contact is at a level the same as or higher than that of an upper surface of the storage contact based on a bottom surface of the bit line contact (see Fig. 1B).
9. Regarding Claim 6, C1 discloses the semiconductor memory device of claim 2, further comprising an information storage part (element DSP, see [0097] “Data storage parts DSP”) disposed on the storage pad and being in contact with the storage pad (see Fig. 1B contact through element 175 and [0097]).
10. Regarding Claim 7, C1 discloses the semiconductor memory device of claim 1, wherein a width of an upper surface of the bit line contact in a second direction (x-axis direction) orthogonal to the first direction is smaller than or equal to a width of a bottom surface of the bit line in the second direction (see Fig. 1B).
11. Regarding Claim 10, C1 discloses the semiconductor memory device of claim 1, wherein the bit line contact spacer is a single layer (see Fig. 1B element 127), and
the bit line spacer is a multilayer (element 170 which includes elements 143A, AG, 155).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2021/0159113 A1), hereinafter as C1, in view of Kim et al. (US 2011/0065275 A1), hereinafter as K1
13. Regarding Claim 4, C1 discloses the semiconductor memory device of claim 2, wherein a width of the bit line contact in a second direction (see Figs. 1A-B x-axis) orthogonal to the first direction.
C1 does not disclose the width of the bit line contact is smaller than or equal to a width of the storage contact in the second direction.
K1 discloses (see Fig. 2) wherein a width of the bit line contact (element 250b, see [0056] “DC bit line contact pads 250b”) in a second direction (see Fig. 1 lateral direction) orthogonal to the first direction (see Fig. 1 vertical direction) is smaller than or equal to a width of the storage contact (element 250a, see [0056] “BC storage contact pads 250a”) in the second direction (see [0056] “the BC storage contact pads 250a and the DC bit line contact pads 250b may be self-aligned and may have the same sectional area”).
The width relationship between the bit line contact and storage contact as taught by K1 is incorporated as a width relationship between the bit line contact and storage contact of C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with C1 because the combination allows for a self-aligned configuration, and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one width relationship between a bit line contact and storage contact for another in a similar device to obtain predictable results (see K1 [0056-0057] The width relationship is adjustable).
14. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2021/0159113 A1), hereinafter as C1, in view of Sung et al. (US 2018/0174971 A1), hereinafter as S1
15. Regarding Claim 5, C1 discloses the semiconductor memory device of claim 2.
C1 does not disclose wherein a height of the bit line contact spacer is smaller than or equal to a height of the storage contact.
S1 discloses wherein a height of the bit line contact spacer is smaller than or equal to a height of the storage contact (see Fig. 2A height of the bit line contact spacer element DCC is smaller than or equal to a height of the storage contact element BC).
The height of the bit line contact spacer with respect to the storage contact as taught by S1 is incorporated with C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with C1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one height relationship between a bit line contact spacer and storage contact for another in a similar device to obtain predictable results (see S1 Fig. 2A).
16. Claims 8 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2021/0159113 A1), hereinafter as C1, in view of Choi et al. (US 2020/0365537 A1), hereinafter as C2
17. Regarding Claim 8, C1 discloses the semiconductor memory device of claim 1.
C1 does not disclose wherein a height from a bottom surface of the bit line contact to an upper surface of the bit line contact is equal to a height from the bottom surface of the bit line contact to an upper surface of the bit line contact spacer.
C2 discloses (see in particular Figs. 1-2 and 11B) wherein a height from a bottom surface of the bit line contact (element DC, see [0018] “bit line node contact DC”) to an upper surface of the bit line contact is equal to a height from the bottom surface of the bit line contact to an upper surface of the bit line contact spacer (element 134, see [0022] “spacers 134 may be respectively disposed between bit line node contacts DC and storage node contacts BC” and [0051-0052] “Third spacers 134 may be formed in the substrate 102 and may fill spaces in which the bit line node contact DC is partially removed.”).
The height of the bit line contact spacer as taught by C2 is incorporated as a height of the bit line spacer of C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1 because the combination n is simple substitution of one known element for another to obtain predictable results – simple substitution of one height of a bit line spacer for another in a similar device to obtain predictable results (see C2 Figs. 1-2 and 11B and [0051-0052]).
18. Regarding Claim 17, C1 discloses a semiconductor memory device (see in particular Figs. 1A-F, 3A and [0097] “semiconductor memory device”) comprising:
a substrate (element 100, see [0073] “substrate 100”) which includes an active region (regions of element ACT, see [0073] “active portions ACT”) defined by a device isolation layer (layer of element 102, see [0073] “device isolation pattern 102”) and extending in a first direction (y-axis direction), the active region including a first region (see Fig. 1B center region defined by elements 102) and second regions (see Fig. 1B regions on left and right sides of the center region) defined at opposite sides of the first region (see Fig. 1B);
a bit line (element 135, see [0106] “the conductive wire 135 may be a bit line”) which is disposed on the substrate and the device isolation layer (see Fig. 1B), extends in a third direction orthogonal (z-axis direction out of the page in Fig. 1A and vertical direction in Fig. 1B) to the second direction, and is connected to the first region of the active region (see Fig. 1B electrically connected through element 130);
a bit line contact (element 130, see [0084] “wire-plugs 130”) which is disposed between the bit line and the substrate and connected to the bit line (see Fig. 1B), a width of an upper surface of the bit line contact in the second direction being smaller than a width of a bottom surface of the bit line in the second direction (see Fig. 1B);
a storage contact (element 120, see [0080] “conductive pad 120”) which is disposed on the substrate and connected to a second region (element ACT adjacent to the center element ACT) of an other active region adjacent to the active region (see Fig. 1B);
a storage pad (element 160, see [0085] “Contact plugs 160”) which is disposed on the storage contact and connected to the storage contact (see Fig. 1B); and
a capacitor (element DSP, see [0105] “data storage part DSP may be realized as a capacitor”) which is disposed on the storage pad and connected to the storage pad (see Fig. 3A).
C1 does not disclose a word line which extends in a second direction in the substrate and the device isolation layer and crosses the first region of the active region and the second region of the active region;
C2 discloses (see Figs. 1-2) a word line (see [0017] “A word line WL may be disposed to be buried in the substrate 102. Word lines WL may extend in a first direction D1 and be disposed to be spaced apart from each other in a second direction D2”) which extends in a second direction (x-axis direction) in the substrate and the device isolation layer and crosses the first region of the active region and the second region of the active region (see [0017] “Two adjacent word lines WL may be disposed to intersect/cross each of the active regions ACT (e.g., from a plan view)”)
The word lines as taught by C2 are incorporated as word lines of C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1 because the combination allows for conductive connection to the memory cell array in matrix formation with bit lines which is a compact configuration for memory devices (see C2 Fig. 1 and [0017]), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known word line configuration for another in a similar device to obtain predictable results (see C2 Fig. 1 and [0017]).
19. Regarding Claim 18, C1, C2 disclose the semiconductor memory device of claim 17, further comprising a bit line contact spacer (see C1 element 127, see [0083] “insulating spacer 127”)) disposed between the bit line contact and the storage contact (see C1 Fig. 1B),
wherein the upper surface of the bit line contact is in contact with the bottom surface of the bit line (see C1 Fig. 1B).
20. Regarding Claim 19, C1, C2 disclose the semiconductor memory device of claim 18, further comprising a bit line spacer (see C1 element 127, see [0083] “insulating spacer 127”)) disposed between the bit line and the storage pad (see C1 Fig. 1B),
wherein the bit line spacer is not in contact with a sidewall of the bit line contact (see C1 Fig. 1B).
21. Regarding Claim 20, C1, C2 disclose the semiconductor memory device of claim 17, wherein a height from a bottom surface of the bit line contact to a lowermost part of the storage pad is smaller than (see Fig. 1B less than) or equal to a height from the bottom surface of the bit line contact to the bottom surface of the bit line (see Fig. 1B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818