DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Group I, Species 1, as shown in FIG. 2, in the reply filed on March 06, 2026 is acknowledged. Applicant identified claims 1-17 are readable on the Elected Group I and Species 1.
Non-Elected Invention and/or Species, Claims 18-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Elected Group I and Species 1, claims 1-17 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 28, 2023 and March 06, 2026 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
LDMOS SEMICONDUCTOR DEVICE HAVING A PAIR OF GATE ELECTRODES AND DEEP WELLS THAT ARE NOT CONNECTED TO EACH OTHER
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 230 of FIGs 3, 5; 280 of FIG. 5; 330, 351, 361, 370, 380, 390 of FIG. 6.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-11 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6, line 11, recites: “wherein the gate electrode and the deep well have no closed path”.
What is “closed path” ?
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term is indefinite because the specification does not clearly redefine the term.
Claim 15 recites a similar limitation.
Therefore, claim 6-11 and 15 are indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-14 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHIN (US. Pub. No. 2021/0028166).
With respect to claim 12, SHIN teaches an LDMOS semiconductor device substantially as claimed including:
a deep well (50) in a core region, comprising a first impurity doped region in a substrate (10);
a first well (81) comprising a second impurity doped region in the deep well (50);
a drain (85) in the first well (81) and in the core region;
a body region (100) in the core region, comprising a third impurity doped region in the substrate;
a source (83) in the body region (100) and in the core region;
a gate electrode (110) on the substrate;
a device isolation layer (76) in each of two isolation regions and surrounding the deep well (50); and
a pair of deep trench isolation (DTI) structures (75), one in each of the isolation regions, near or adjacent to a boundary of the core region, wherein the DTI structures (75) are spaced apart along a length or similar longitudinal direction of the LDMOS semiconductor device. (See FIG. 1).
With respect to claim 13, the pair of DTI structures (75) of SHIN are directly connected to each other.
With respect to claim 14, the pair of DTI structures (75) of SHIN extend substantially parallel along a width or similar lateral direction of the LDMOS semiconductor device.
With respect to claim 16, the pair of DTI structures (75) of SHIN have ends in a width direction connected to each other on or in the device isolation layer.
With respect to claim 17, the DTI structure of SHIN comprises:
an upper section at least partially overlapping the device isolation layer (76), and having a smaller width than the device isolation layer (76); and
a lower section continuous with the upper section and having an end deeper than a lowermost surface of the upper section, wherein the lower section has a smaller width than the upper section.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over SHIN ‘166 as applied to claim 12 above, and further in view of CHEN et al. (US. Pub. No. 2013/0207184).
As best understood by the Examiner, SHIN teaches the LDMOS semiconductor device as described in claim 12 above including: the gate electrode (110) and the deep well (50).
Thus, SHIN is shown to teach all the features of the claim with the exception of explicitly disclosing the gate electrode and the deep well have no closed path.
However, CHEN teaches a LDMOS semiconductor device including:
a gate electrode (12) and the deep well (13), wherein the gate electrode (12) and the deep well (13) have no closed path. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the LDMOS semiconductor device of SHIN including the gate electrode and the deep well have no closed path as taught by CHEN to improve the maximum withstand voltage.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN ‘166 in view of CHEN ‘184.
With respect to claim 1, SHIN teaches a lateral double-diffused metal-oxide-semiconductor (LDMOS) semiconductor device substantially as claimed, including:
a core region including a source (83) and a drain (81) spaced apart from each other;
an isolation region (75); and
an extension region between the core region and the isolation region (75),
wherein the core region comprises a pair of gate electrodes (110) on opposite sides of the source (83) and on a substrate (10), and the pair of gate electrodes (110) extend through the core region to the extension region (not shown). (See FIG. 12A).
Thus, SHIN is shown to teach all the features of the claim with the exception of explicitly disclosing the pair of gate electrodes are not directly connected to each other.
However, CHEN teaches a semiconductor device including:
a core region including a source and a drain spaced apart from each other; and
an extension region between the core region and the isolation region,
wherein the core region comprises a pair of gate electrodes (22) on opposite sides of the region (241) and on a substrate (20), and the pair of gate electrodes (22) extend through the core region to the extension region and are not directly connected to each other. (See FIGs. 3-4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of SHIN including the extension region between the core region and the isolation region and are not directly connected to each other as taught by CHEN to improve the maximum withstand voltage.
With respect to claim 2, the isolation region (DTI) of SHIN comprises a deep trench isolation(DTI) structure (75) at, adjacent or near to a boundary of the core region.
With respect to claim 3, the isolation region of SHIN further comprises a device isolation layer, the device isolation layer comprises a shallow trench isolation (76) structure, and the DTI structure (75) at least partially overlaps the device isolation layer.
With respect to claim 4, the DTI structure of SHIN comprises: an upper section overlapping with the device isolation layer (76) and having a smaller width than the device isolation layer (76); and a lower section extending from the upper section.
With respect to claim 5, the lower section of SHIN has a smaller width than the upper section.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN ‘166 in view of OGURA (US. Pub. No. 2010/0078709) and CHEN ‘184.
With respect to claim 6, As best understood by the Examiner, SHIN teaches an LDMOS semiconductor device substantially as claimed, including:
a deep well (50), comprising a first impurity doped region in a substrate (10);
a first well (81) comprising second (81) impurity doped regions in the deep well (50);
a drain (85) in the first well (81);
a body region (100) in the substrate, comprising a fourth impurity doped region (100) spaced apart from the deep well (50);
a source (83) in the body region (100);
a gate electrode (110) on the substrate, spaced apart from the source (83) and drain (85); and a deep trench isolation structure (75) in the substrate (10). (See FIG. 1).
Thus, SHIN is shown to teach all the features of the claim with the exception of explicitly disclosing a second well in the deep well; and the gate electrode and the deep well have no closed path.
However, OGURA teaches a semiconductor device including:
a deep well (3), comprising a first impurity doped region in a substrate (2);
a first well and a second well, comprising second (9) and third (11) impurity doped regions in the deep well (3). (See FIG. 1A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of SHIN including the second well comprising the third doped region as taught by OGURA to provide ESD protection.
Further, CHEN teaches a semiconductor device including:
a deep well (13), comprising a first impurity doped region in a substrate (10); and
a gate electrode (12) on the substrate, spaced apart from the source and drain,
wherein the gate electrode (12) and the deep well (13) have no closed path. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of SHIN including the gate electrode and the deep well have no closed path as taught by CHEN to improve the maximum withstand voltage.
With respect to claim 7, the semiconductor device of SHIN further comprises: a device isolation layer surrounding the deep well (50).
With respect to claim 8, the DTI structure (75) of SHIN limits a longitudinal extension of the deep well.
With respect to claim 9, the DTI structure (75) of SHIN is in an isolation region and adjacent to a boundary with a core region.
With respect to claim 10, the semiconductor device of SHIN comprises a pair of the DTI structures (75), one each on opposite ends or boundaries of the core region, the pair of DTI structures (75) being spaced apart from each other, and extending along a width direction.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over SHIN, OGURA and CHEN as applied to claim 6 above, and further in view of KO et al. (US. Pub. No. 2015/0069508).
SHIN, in view of OGURA and CHEN, teaches the LDMOS semiconductor device as described in claim 6 above including a first buried layer (31).
Thus, SHIN, OGURA and CHEN are shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor device further comprises: a second buried layer in the substrate; and a high voltage well connected to the second buried layer and a well.
However, KO teaches a LDMOS semiconductor device including:
a first buried layer (102) and a second buried layer (104) in the substrate; and
a high voltage well (105) connected to the second buried layer (104) and a well (106). (See IFG. 1B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of SHEN further including the second buried layer in the substrate; and the high voltage well connected to the second buried layer and the well as taught by KO to suppress the operation of the parasitic device and thereby increase the breakdown voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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