DETAILED ACTION
This action is responsive to the application No. 18/191,505 filed on March 28, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to method claims 1-13, in the reply filed on October 31, 2025, is acknowledged. Claims 14-20 are withdrawn from consideration.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on June 20, 2022. It is noted, however, that applicant has not filed a certified copy of the JP 2022-099170 application as required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 recites the penetrating portion includes a plurality of through grooves, and the plurality of through grooves are concentrically opened on the wafer placement surface in plan view. The use of “through grooves” obfuscates the claimed invention since this implies the grooves (i.e. long narrow cuts or depressions) in the surface extend all the way through the holding member. If all of the surface grooves extend through the entire holding member it would be a set of rings having no mechanical integrity. There are apparently two distinct features present: there are through holes (Applicant’s “penetrating portions”) and these apparently connect to grooves formed in the surface of the holding member. This is shown in Figs. 6 and 7 and the only features extending all the way through the entire holding member are the discrete holes or openings corresponding to the REG features (black dashed line). For example, see Figs. 4-5 in Monteen et al. (US2010/0013169) showing more clearly the conventional combination of grooves 402/502 and through holes 408/508, and compare to Fig. 7 of the instant application. One would not refer to 408/508 as “through grooves”. The claim should instead recite the “penetrating portions” are connected to grooves in the wafer placement surface for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “…the maximum height of the wafer placement surface of the wafer holding member is equal to or smaller than 20 μn”. It is unclear how to interpret this limitation because the maximum height is not defined. A maximum height of a surface is determined with respect to a reference point or plane, e.g. an opposite surface or the floor, or some other location. A height of the upper surface, when used in a conventional wafer fab may be 1 meter or more above a factory floor. According to the specification (pp. 16-17), this limitation appears to correspond to a discussion of the flatness (or possibly bow or warp? and/or roughness?) of the surface, however, the disclosed measurement(s) and vaguely described calculation(s) are not fully defined in a manner that would allow one to perform an identical measurement thereby making it impossible to compare to prior art, nor are any known standards (ISO, SEMI, ANSI, etc.) recited. It is unclear how a roughness curve is determined, nor is it clear over what distance an average line is measured, or over what intervals this is determined, or specifically how any of this is actually measured and calculated. Since the measurements and calculations are not fully defined, this limitation is indefinite since different methods or even selecting different variables/ranges/statistics for a given method for determining flatness and surface roughness will result in different values (e.g. simply taking an average over a very small distance or area can produce vastly different results than if considered over a much much larger distance or area), it is unclear how the value disclosed can be compared to prior art making it unclear when infringement occurs. For the purpose of examination, this will simply be treated as a substantially flat surface.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lackner et al. (US 2008/0064184).
(Re Claim 1) Lackner teaches a method of manufacturing a semiconductor device comprising:
a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion by grinding a first back surface of a semiconductor wafer including a front surface and the first back surface opposite to the front surface (¶¶25, 90, and claim 21: wafer 7 thinned by grinding from a back surface 8, see Figs. 7A-7C);
a preparation step of preparing a wafer holding member including a wafer placement surface and a second back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion (wafer holding member 2 or 2+26, or 2+24, see configurations in Figs. 5, 6, and 7C);
a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the first back surface side of the semiconductor wafer (see Figs. 5, 6, and 7C, wafer 7 is placed on holder 2 as claimed); and
a movement step of moving the semiconductor wafer in a state in which the semiconductor wafer is held on the wafer holding member (see ¶¶16, 43, 51, 82, 91 regarding moving).
(Re Claim 5) wherein the wafer holding member includes a penetrating portion opened on the wafer placement surface and the second back surface, and the semiconductor wafer placed on the wafer placement surface is fixed by causing the penetrating portion to have a negative pressure state (¶¶59, 67, 86, 87, vacuum channels 22).
(Re Claim 6, also see §112 rejection above) wherein the maximum height of the wafer placement surface of the wafer holding member is equal to or smaller than 20 μn (the holder having a flat upper surface).
(Re Claim 9) further comprising a test step of testing the semiconductor wafer by applying a voltage to the semiconductor wafer through the wafer holding member, wherein the wafer holding member has an electrical conductivity (see Fig. 5, testing is performed by applying a voltage between the wafer and holding member, the wafer holder being conductive, ¶¶64-71).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lackner et al. (US 2008/0064184) as applied above, and further in view of Mori et al. (US 5,191,218), Yano et al. (US 2015/0145547), and Monteen et al. (US 2010/0013169).
(Re Claim 8, also see Objection above regarding “through grooves”) wherein the penetrating portion includes a plurality of through grooves, and the plurality of through grooves are concentrically opened on the wafer placement surface in plan view.
While Lackner teaches the penetrating portion includes a plurality of through grooves 22, there is no plan view of the wafer placement surface. A PHOSITA desiring to make and use Lackner’s wafer holding member would be motivated to look to related art to provide additional details where Lackner is silent. Related art from Mori teaches a vacuum wafer holder (Figs. 2A-2B) wherein the upper surface comprises a plurality of concentric grooves (91, 92) opened on the wafer placement surface. Related art from Yano also teaches a vacuum wafer holder (Figs. 2-3) wherein the upper surface comprises a plurality of concentric grooves 112/112a-n opened on the wafer placement surface. Related art from Monteen also similarly teaches this conventional configuration for a vacuum wafer holder (Figs. 4-5) comprising a plurality of concentric surface grooves 402/502. Forming a plurality of concentric grooves in the wafer placement surface as shown by Mori, Yano, and Monteen allows the vacuum to be evenly distributed across the entire wafer surface for uniform clamping force. A PHOSITA would find it obvious to form concentric surface grooves connected to the through holes 22 to provide uniform vacuum distribution and clamping force across the wafer placement surface.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lackner et al. (US 2008/0064184) as applied above, and further in view of Ogawa et al. (US 2001/0026486) and Seddon (US 202/0051877).
(Re Claim 10) further comprising a step of changing a manufacturing process condition in accordance with a result of the test step.
Lackner is silent regarding what one would do based on the testing results, however it would be obvious for any PHOSITA, if/when devices fail testing, to identify the source of the problem, and when caused by a manufacturing process, it is obvious to make appropriate changes to said process. This is just plain obvious, common practice, and well known throughout the entire semiconductor industry. Related art from Ogawa provides details of performing testing and then using the failure data to make changes to processes (e.g. see Figs. 1-8, abstract, ¶¶81-105, 283, 289). Related art from Seddon discloses testing to determine whether dies will be used in subsequent packaging, e.g. selecting only good dies for packaging, which also meets changing a manufacturing process condition as the subsequent processing for any given die will be changed based on the testing results (¶¶62-65). A PHOSITA would find it obvious to apply the general concept of feedback control in the manufacturing based on testing as taught by Ogawa and Seddon.
(Re Claim 11) further comprising a screening step of screening a non-defective chip and a defective chip in accordance with a result of the test step.
Lackner is silent regarding a screening step of screening a non-defective chip and a defective chip in accordance with a result of the test step, however this would be obvious to any PHOSITA. If a device fails testing and there is no way to repair it, it would be marked as defective and subsequently scrapped, and if a device passes testing it would be used, packaged, and/or shipped. This is just plain obvious as a company would want to only package and ship known good dies, rather than failed dies, to its customers. Related art from Ogawa provides such details of conventional testing (e.g. ¶239) to determine defective and non-defective dies. Related art from Seddon also provides similar details regarding testing to identify known good dies for use in packaging (¶¶62-65). A PHOSITA would find it obvious to screen for defective and non-defective devices when testing as this is one of the main reasons for testing.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lackner et al. (US 2008/0064184) as applied above, and further in view of Ogawa et al. (US 2001/0026949) and Yu et al. (US 2004/0161865).
(Re Claim 13) further comprising a step of cutting a fuse element formed on the semiconductor wafer by using laser beam.
Lackner is silent regarding a step of cutting a fuse element formed on the semiconductor wafer by using laser beam. Lackner discloses performing testing (Fig. 5 and ¶¶64-71), however lacks details regarding what is done after testing. Device testing involves determining when dies pass, fail, are out of spec, etc., and whether repairs can be made. A PHOSITA would be motivated to look to related testing art to determine subsequent steps. Related art from Yu discloses when testing is performed, one can determine whether or not to cut a particular fuse with a laser to repair the device, e.g. by eliminating a connection to a defective circuit of the device (see abstract, ¶¶11-17, 28-31, Figs. 3A-4B). Related art from Ogawa teaches using a laser to trim fuses based on testing to replace defective circuits (Fig. 11 and ¶¶116-146). A PHOSITA would find it obvious to use laser fuse trimming as taught by Yu an Ogawa, based on test results, to repair defective devices.
Rejection 2
Claims 1-3, 5-6, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Seddon (US 2020/0051877) in view of Yano et al. (US 2015/0145547).
(Re Claim 1) Seddon teaches a method of manufacturing a semiconductor device comprising (see Figs. 1a-3e and ¶¶46-64):
a grind step (Fig. 2d) of forming a small thickness portion and a large thickness portion surrounding the small thickness portion by grinding a first back surface of a semiconductor wafer (100) including a front surface and the first back surface opposite to the front surface;
a preparation step of preparing a wafer holding member including a wafer placement surface and a second back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion (Fig. 3d, holding member 194 (mislabeled 192 in figure));
a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the first back surface side of the semiconductor wafer (Fig. 3e).
Seddon places the wafer on the vacuum wafer holder for probing, however is silent regarding a movement step of moving the semiconductor wafer in a state in which the semiconductor wafer is held on the wafer holding member. A PHOSITA desiring to make, use, and improve upon Seddon’s methods would be motivated to look to art to teach details of probing setups where Seddon is silent. Related art from Yano teaches (Figs. 1-4) when probing a taiko wafer W on a vacuum wafer holder 10, the holder with mounted wafer is movable to allow for wafer positioning with respect to the stationary probing equipment, e.g. probe card 20, test head 30, etc. (¶¶18, 42). This configuration is advantageous because it is easier to move and align the wafer with respect to fixed prober probes than it is to move and align a probe card and probes with respect to a fixed wafer. In light of Yano, a PHOSITA would find it obvious to employ a similar configuration in Seddon’s testing apparatus, e.g. to include a driving unit 11 to allow the wafer and holder to move and align with respect to the fixed testing apparatus.
(Re Claim 2) wherein, in the placement step, the semiconductor wafer is placed on the wafer holding member so that the large thickness portion of the semiconductor wafer and the wafer holding member are not in contact with each other (see Fig. 3e, thicker portion of wafer separated from chuck surface 190a).
(Re Claim 3) wherein the wafer holding member includes: a stage having the wafer placement surface (190b); and an outer periphery (190a) formed to surround the stage on the first back surface side in plan view, in the placement step, the semiconductor wafer is placed on the stage so that the large thickness portion of the semiconductor wafer and the outer periphery of the wafer holding member face each other (Fig. 3e).
(Re Claim 5) wherein the wafer holding member includes a penetrating portion opened on the wafer placement surface and the second back surface, and the semiconductor wafer placed on the wafer placement surface is fixed by causing the penetrating portion to have a negative pressure state (vacuum ports 193, ¶60).
(Re Claim 6, also see §112 rejection above) wherein the maximum height of the wafer placement surface of the wafer holding member is equal to or smaller than 20 μn (190b has a flat planar surface).
(Re Claim 9) further comprising a test step of testing the semiconductor wafer by applying a voltage to the semiconductor wafer through the wafer holding member, wherein the wafer holding member has an electrical conductivity (see Fig. 3e and ¶¶60-65, several tests disclosed in ¶¶63-65 require the application of a voltage).
(Re Claim 10) further comprising a step of changing a manufacturing process condition in accordance with a result of the test step.
Seddon discloses testing to determine whether dies will be used in subsequent packaging, e.g. selecting only good dies for packaging, which meets changing a manufacturing process condition as the subsequent processing for any given die will be changed (¶¶62-65).
(Re Claim 11) further comprising a screening step of screening a non-defective chip and a defective chip in accordance with a result of the test step (testing to determine good dies for packaging, ¶¶62-65).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Seddon (US and Yano et al. as applied above, and further in view of Mori et al. (US 5,191,218) and Monteen et al. (US 2010/0013169).
(Re Claim 8, also see Objection above regarding “through grooves”) wherein the penetrating portion includes a plurality of through grooves, and the plurality of through grooves are concentrically opened on the wafer placement surface in plan view.
While Seddon teaches the penetrating portion includes a plurality of through grooves 193, there is no plan view of the wafer placement surface. A PHOSITA desiring to make and use Seddon’s wafer holding member would be motivated to look to related art to provide additional details where Seddon is silent. Related art from Mori teaches a vacuum wafer holder (Figs. 2A-2B) wherein the upper surface comprises a plurality of concentric grooves (91, 92) opened on the wafer placement surface. Related art from Yano also teaches a vacuum wafer holder (Figs. 2-3) wherein the upper surface comprises a plurality of concentric grooves 112/112a-n opened on the wafer placement surface. Related art from Monteen also similarly teaches this conventional configuration for a vacuum wafer holder (Figs. 4-5) comprising a plurality of concentric surface grooves 402/502. Forming a plurality of concentric grooves in the wafer placement surface as shown by Mori, Yano, and Monteen allows the vacuum to be evenly distributed across the entire wafer surface for uniform clamping force. A PHOSITA would find it obvious to form concentric surface grooves connected to the through holes 193 to provide uniform vacuum distribution and clamping force across the wafer placement surface.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Seddon and Yano et al. as applied above, and further in view of Lackner et al. (US 2008/0064184) and Kazou et al. (JP 2009/246199, citations from machine translation).
(Re Claim 12) further comprising a test step of testing the semiconductor wafer by applying a voltage to the semiconductor wafer through a prober being in contact with the front surface of the semiconductor wafer and the wafer holding member, wherein the wafer holding member has an electrical conductivity, the semiconductor wafer includes: a plurality of cell regions spaced apart from each other; and a scribe region formed between the plurality of cell regions, the penetrating portion is formed to overlap the scribe region in plan view, and, in the test step, the prober is in contact with the cell region so as not to overlap the penetrating portion.
Seddon teaches (¶¶61-69) testing the wafer on a conductive support and several tests disclosed by Seddon requires the application of a voltage and probing the top (device side) of the wafer, also noting Fig. 3h showing probing pads 112 on the top of the wafer in device “cell” regions, located between the streets 106 (see Figs. 1a-1b). Seddon is silent regarding the penetrating portion is formed to overlap the scribe region in plan view, and, in the test step, the prober is in contact with the cell region so as not to overlap the penetrating portion since when Seddon shows the wafer overlapping the penetrating portions (Fig. 3d), Seddon fails to show where a pad (and corresponding prober contacting said pad) is located with respect to the penetrating portions 193. Looking to related art, Lackner shows additional details of a testing/probing step (Fig. 5 and ¶¶64-70) wherein the probes 66, understood to contact device pads (not shown, e.g. see Seddon Figs. 1b and 3h), contacts the device wafer in locations that do not overlap the penetrating portions 22. In view of Lackner, a PHOSITA would find it obvious to arrange the wafer such that the probe pad locations in the device areas do not overlap the penetrating portions. Furthermore, in light of Kazuo recognizing that when using a holder with conventional through holes (Fig. 31, through hole 80, lines 186-190), the thinned wafer can deflect into the through hole when the vacuum is applied. A PHOSITA would recognize this may cause damage to devices and may make probing more channeling if the surface locally moves and becomes non-planar. Thus one would find it obvious to place the through holes in less critical locations, such as in the dicing streets instead of overlapping devices, where the material will be removed during dicing and no probing is necessary in the location.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Seddon and Yano et al. as applied above, and further in view of Ogawa et al. (US 2001/0026949) and Yu et al. (US 2004/0161865).
(Re Claim 13) further comprising a step of cutting a fuse element formed on the semiconductor wafer by using laser beam.
Seddon is silent regarding a step of cutting a fuse element formed on the semiconductor wafer by using laser beam. Seddon discloses performing testing (¶¶61-65), however lacks details regarding what is done after testing. Device testing involves determining when dies pass, fail, are out of spec, etc., and whether repairs can be made. A PHOSITA would be motivated to look to related testing art to determine subsequent steps. Related art from Yu discloses when testing is performed, one can determine whether or not to cut a particular fuse with a laser to repair the device, e.g. by eliminating a connection to a defective circuit of the device (see abstract, ¶¶11-17, 28-31, Figs. 3A-4B). Related art from Ogawa teaches using a laser to trim fuses based on testing to replace defective circuits (Fig. 11 and ¶¶116-146). A PHOSITA would find it obvious to use laser fuse trimming as taught by Yu an Ogawa, based on test results, to repair defective devices.
Rejection 3
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kazou et al. (JP 2009/246199, citations from machine translation).
(Re Claim 1) Kazou teaches a method of manufacturing a semiconductor device comprising:
a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion by grinding a first back surface of a semiconductor wafer including a front surface and the first back surface opposite to the front surface (wafer 31, grinding lines 76-94, Figs. 3, 11-13, 19-22, 26);
a preparation step of preparing a wafer holding member including a wafer placement surface and a second back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion (see wafer holding members 101/102/103 and Figs.1, 3, 7, 9, 11-13);
a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the first back surface side of the semiconductor wafer (wafer 31 placed on holding member, see Figs. 3, 11-13); and
a movement step of moving the semiconductor wafer in a state in which the semiconductor wafer is held on the wafer holding member (moving see lines 566-572 and 584-589, Figs. 13, 16).
(Re Claim 2) wherein, in the placement step, the semiconductor wafer is placed on the wafer holding member so that the large thickness portion of the semiconductor wafer and the wafer holding member are not in contact with each other (see wafer 31 placed on holding member in Figs. 3, 11-13, and lines 350-355 regarding a gap when height is greater than recess in rib wafer)
(Re Claim 3) wherein the wafer holding member includes: a stage having the wafer placement surface; and an outer periphery formed to surround the stage on the first back surface side in plan view, in the placement step, the semiconductor wafer is placed on the stage so that the large thickness portion of the semiconductor wafer and the outer periphery of the wafer holding member face each other (Figs. 3, 11-13).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kazuo et al. as applied above, and further in view of Kazunari (JP 2007258444, citations from machine translation), Nakamura et al. (US 2016/0163579), and Saito (US 2022/0115250).
(Re Claim 4) wherein a first notch is formed in a part of the outer periphery, a second notch is formed in a part of the outer periphery of the semiconductor wafer, and, in the placement step, the semiconductor wafer is placed on the stage so that the first notch of the wafer holding member and the second notch of the semiconductor wafer overlap each other.
Kazuo discloses the wafer has an orientation notch (lines 421-425) however does not disclose a corresponding notch in the outer periphery of the holding member. Notches in wafers are well known and standard practice for large wafers of 200-300 mm diameter, while smaller wafers use orientation flats. A PHOSITA desiring to make, use, and improve upon Kazuo’s methods would be motivated to look to related art to teach improvements. A PHOSITA would recognize it is well known and obvious to use the notches (or flats) to facilitate coarse/macro wafer positioning and alignment by using optical methods (e.g. see Saito Fig. 2, notch 26, ¶¶38, 44, 46, 138). In addition, it is also known to similarly form notches (or flats) in the perimeter of wafer carriers, also for positioning and alignment as taught by Kazunari (see Fig. 1, notch 7 and lines 157-158, 168-178). Also note Kazunari’s Figs. 4-6 showing the carrier may alternatively be the same size as the wafer (as in Kazuo) and while a flat corresponding to a smaller wafer is shown, for a larger wafer having a notch, it is obvious the carrier will have a corresponding notch in the perimeter. With two notches present, each in the outer perimeters of the wafer and holder, each having the same diameter, a PHOSITA would find it obvious to align the two notches, such that they overlap, to allow for conventional optical wafer alignment/position detection of the wafer+holder assembly. Related art from Nakamura teaches when mounting a wafer on a carrier, each having notches, the wafer and carrier are aligned such that the notches overlap (¶165). In view of the prior art, a PHOSITA would find it obvious to form a notch in the perimeter of Kazuo’s holder, and when placing the wafer having a notch on the holder, to align the notches such that they overlap to enable position detection and alignment of the wafer+holder assembly.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 recites the allowable subject matter “a second placement step of placing the wafer holding member and the semiconductor wafer onto a measuring stage including a suction groove for vacuum suction formed thereon in a state in which the semiconductor wafer is placed on the wafer holding member, in the second placement step, the wafer holding member is placed on the measuring stage so that the penetrating portion and the suction groove communicate with each other, and a second open width of the penetrating portion opened on the second back surface is larger than a first open width of the penetrating portion opened on the wafer placement surface”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches thinned wafers on various wafer holding members.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898