DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A & 4 in the reply filed on 12/17/2025 is acknowledged. Claims 1-4, 7-11, & 14-17 are examined on the merits.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the phrase “including electrodes disposed in different layers,” be added to the title.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, & 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Pat. Pub. No. US 20240186328 A1 to Gao (hereinafter “Gao’).
Regarding claim 1, Gao teaches an array substrate (of fig. 8) [0075], comprising:
a gate electrode (gate portion 211; fig. 8) [0067],
a compensation electrode (112; fig. 8) [0067] disposed on a side (shifted in the x-direction) of the gate electrode (211) and connected to the gate electrode (211);
an array substrate side common electrode (compensation electrode 113; fig. 8) [0083], and
a source electrode (structure of source portion 141 and elements immediately surrounding 141, hereinafter “source electrode”; fig. 8) [0069], wherein the source electrode (source electrode) and the gate electrode (211) are disposed in different layers (“first source electrode disposed in a layer different from the first gate portion”; fig. 8) [0008], and the source electrode (source electrode) and the compensation electrode (112) are disposed in different layers (“first source electrode disposed in a layer different… the first compensation electrode”; fig. 8) [0008];
wherein the source electrode (source electrode) comprises a storage capacitor portion (third extension part 144, comprising some capacitance between 144 and 113; fig. 8) [0084], a source electrode portion (first extension part 142; fig. 8) [0069], and a compensation portion (second extension part 143; fig. 8) [0069], the source electrode portion (142) and the compensation portion (143) are disposed on two opposite sides (shifted in the x-direction) of the storage capacitor portion (144) and are connected to the storage capacitor portion (144), a part of the source electrode portion (142) overlaps the gate electrode (211), a part of the compensation portion (143) overlaps the compensation electrode (112), the source electrode (source electrode) and the array substrate side common electrode (113) are disposed in different layers, in an extension direction (x-axis in fig. 8 starting from the center of 141 towards 142, hereinafter “x-direction of 142”) of the source electrode portion (142),
a part of the storage capacitor portion (144) intersecting the source electrode portion (142) at least partially overlaps (at the via hole located at the center of 141, elements 143 and 142 both meeting at this intersection and at least overlapping 113 in the y direction) [0075] the array substrate side common electrode (113); and
in an extension direction (x-axis in fig. 8 starting from the center of 141 towards 143, hereinafter “x-direction of 143”) of the compensation portion (143), a part of the storage capacitor portion (144) intersecting the compensation portion (143) at least partially overlaps (at the via hole located at the center of 141, elements 143 and 144 both meeting at this intersection and at least overlapping 113 in the y direction) [0075] the array substrate side common electrode (113).
The Examiner notes that the interpretation taken concerning the at least partial overlapping of the intersection of storage capacitor portion 144 and the source electrode 142 with the array substrate side common electrode would be untenable if the Applicant amends claim 1 to recite that the intersection “overlaps” (thus requiring a narrower interpretation; excluding the terms “at least partially”) these elements.
Regarding claim 3, Gao teaches the array substrate according to claim 2, wherein in a direction perpendicular (y-direction) to the extension direction of the source electrode portion (x-direction of 142) or the compensation portion (x-direction of 143), a distance between the storage capacitor portion (143) and the gate line (SL) is less than or equal to (equal as 143 and 142 are compared in the y-direction with respect to their distances from SL) a distance between the source electrode portion (142) and the gate line (SL), and the distance between the storage capacitor portion (144) and the gate line (SL) is less than or equal to a distance between the compensation portion (143) and the gate line (SL).
Regarding claim 4, Gao teaches the array substrate according to claim 1, wherein the extension direction of the source electrode portion (x-direction of 142) is parallel (not intersecting, for example, the extension direction of the source electrode portion located in the source electrode portion) to the extension direction of the compensation portion (x-direction of 143), and the extension direction of the source electrode portion (x-direction of 142) is opposite (extending in opposite directions to the left and to the right in fig. 8) to the extension direction of the compensation portion (x-direction of 143).
Regarding claim 7, Gao teaches the array substrate according to claim 4, wherein in the extension direction of the source electrode portion (x of 142) or the compensation portion (x of 143), an edge (extension leading side) of one of the storage capacitor portion (143) and the array substrate side common electrode (113) extends beyond (extends past) an edge of the other on the same side (extension leading side); and in a direction perpendicular (y-direction) to the extension direction of the source electrode portion (x of 142) or the compensation portion (x of 143), an edge (leading extension edge) of one of the storage capacitor portion (143) and the array substrate side common electrode (113) extends beyond an edge of the other on the same side (a side in the positive y-direction in fig. 8, 113 extending beyond 143).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of U.S. Pat. Pub. No. US 20030184699 A1 to Matsumoto et al. (hereinafter “Matsumoto”).
Regarding claim 8, Gao does not teach the array substrate according to claim 7, wherein in the extension direction of the source electrode portion or the compensation portion, a distance between the edge of the storage capacitor portion and an edge of the array substrate side common electrode on the same side ranges from 3 to 5 microns, and a distance between the gate electrode and the storage capacitor portion is greater than or equal to 4.3 microns.
However, Matsumoto teaches pixel electrode configurations wherein the distance between electrodes effects the electric field of the electrodes [0069].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the distance between the storage capacitor portion and the array substrate common electrode as well as the distance between the gate electrode and the storage capacitor portion to result in a lower voltage to generate the same electric field [0069].
Furthermore, given the above, arriving at the specific distances recited in claim 8 would have been a matter of routine optimization, as Matsumoto establishes the prior art conditions necessary for such an optimization on the part of the person of ordinary skill in the art. M.P.E.P. 2144.05 II (A).
Regarding claim 9, Gao does not explicitly teach the array substrate according to claim 7, wherein in the direction perpendicular to the extension direction of the source electrode portion or the compensation portion, and a distance between the edge of the storage capacitor portion and an edge of the array substrate side common electrode on the same side ranges from 3 to 5 microns, a width of the source electrode portion ranges from 7 to 10 microns.
Gao, however, teaches that the width of the electrodes effects parasitic capacitance [0110].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the width of the source electrode portion to control parasitic capacitance as taught by Gao [0110].
Furthermore, given the above, arriving at the specific width recited in claim 9 would have been a matter of routine optimization, as Gao establishes the prior art conditions necessary for such an optimization on the part of the person of ordinary skill in the art. M.P.E.P. 2144.05 II (A).
Regarding the electrode distances, Matsumoto teaches pixel electrode configurations wherein the distance between electrodes effects the electric field of the electrodes [0069].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the distance between the storage capacitor portion and the array substrate common electrode to result in a lower voltage to generate the same electric field [0069].
Furthermore, given the above, arriving at the specific distances between electrodes recited in claim 9 would have been a matter of routine optimization, as Matsumoto establishes the prior art conditions necessary for such an optimization on the part of the person of ordinary skill in the art. M.P.E.P. 2144.05 II (A).
Regarding claim 10, Gao teaches the array substrate according to claim 1, wherein the array substrate further comprises a drain electrode (130; fig. 8) [0073], in the extension direction of the source electrode portion (142) or the compensation portion (143),
Gao does not teach a distance between the drain electrode and an edge of a side of the gate electrode near the storage capacitor portion is greater than or equal to 7 microns.
However, Matsumoto teaches pixel electrode configurations wherein the distance between electrodes effects the electric field of the electrodes [0069].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the distance between the drain electrode and an edge of the gate electrode to result in a lower voltage to generate the same electric field [0069].
Furthermore, given the above, arriving at the specific distances recited in claim 10 would have been a matter of routine optimization, as Matsumoto establishes the prior art conditions necessary for such an optimization on the part of the person of ordinary skill in the art. M.P.E.P. 2144.05 II (A).
Allowable Subject Matter
Claims 11-17 are allowed.
Regarding claim 11, Gao does not teach that the minimum distance between the contact hole and the gate line is less than or equal to a width of the gate electrode, nor is this principle taught in the art. Matsumoto teaches that the distance between electrodes effects the electric field of the electrodes [0069], these distances being manipulated to result in a lower voltage to generate the same electric field [0069]. However, this principle is applied between a pixel electrode and a common electrode interconnect line, and is not considered to be similar enough to the subject matter of claim 11 so as to teach the person of ordinary skill in the art what is needed for them to reach the limitations of claim 11 through routine experimentation or the like. A rejection of claim 11 is thus untenable. Claims 12-17 are also allowable by virtue of their dependence on claim 11.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Gao does not teach that the minimum distance between the contact hole and the gate line is less than or equal to a width of the gate electrode, nor is this principle taught in the art. Matsumoto teaches that the distance between electrodes effects the electric field of the electrodes [0069], these distances being manipulated to result in a lower voltage to generate the same electric field [0069]. However, this principle is applied between a pixel electrode and a common electrode interconnect line, and is not considered to be similar enough to the subject matter of claim 2 so as to teach the person of ordinary skill in the art what is needed for them to reach the limitations of claim 2 through routine experimentation or the like. A rejection of claim 2 is thus untenable. Claim 3 is allowable by virtue of its dependence on claim 2.
Rejoinder
Claim 11 is allowable. Claims 12 & 13, previously withdrawn from consideration as a result of a restriction requirement, require all the limitations of an allowable claim. Pursuant to the procedures set forth in MPEP § 821.04(a), the restriction requirement between species A and B, as well as species 1-4, as these species relate to claim 11, as set forth in the Office action mailed on 10/23/2025, is hereby withdrawn and claims 12 & 13 hereby rejoined and fully examined for patentability under 37 CFR 1.104. In view of the withdrawal of the restriction requirement, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. The Examiner notes that claims 5 & 6, currently withdrawn from consideration as being directed to non-elected subject matter, are not rejoined because they do not require all the limitations of an allowable claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Pat. Pub. No. US 20140339554 A1 to Xi et al. teaches a pixel structure with separated electrodes.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892