CTNF 18/191,785 CTNF 81889 DETAILED ACTION 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. This Non-Final office action is in response to application 18/191,785, application filed on 03/28/2023. 3. Claims 1-20 are currently pending in this application. Information Disclosure Statement 4. The information disclosure statement (IDS) submitted on 03/28/2023, 04/06/2023 and 04/18/2024, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA 6. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hung et al. (US Patent No. 11,853,668) . 7. With respect to independent claim 1, Hung teaches : An electronic device (see device/apparatus of Fig 9, showing HDL DUT as input to compiler for programming hardware, Col 9, lines 50-60) , comprising: memory storing instructions; and a processor, that when executing the instructions (see computer system parts to carry out compiling programs into programmable hardware, Fig 7-8) , is to: receive a design for a programmable fabric of an integrated circuit device (see receiving HDL representing design, Fig 9, at 205; see Fig 9, showing HDL compiled for programming into a programmable hardware fabric, as shown in fig 9) ; cause compilation of the design into a configuration during a compilation window (compile is launched, Col 3, lines 12-25; timeline/window for compiling design into programmable chip, Col 3, lines 10-20; see compile time, Col 6, lines 10-20; see time period/window, Col 11, lines 50-55; see compilation/emulation timing windows, Col 14, lines 5-25) ; and determine at least some routing for the configuration outside of the compilation window (solving/reducing long compile times by not needing all routing to be completed during initial compile, doing some place & route later in sequential routing after initial compile, Col 3, lines 30-45; no urgency to finish all routing during initial compile window, Col 3, lines 30-45) . 8. With respect to claim 2, Hung teaches : wherein determining the at least some routing for the configuration comprises compiling the at least some routing before compiling the design in the compilation window (see compilation of some routing for critical timing paths, followed by additional stages of fpga design compilation, see Col 2, lines 5-25) . 9. With respect to claim 3, Hung teaches : wherein the at least some routing comprises external routing connecting a region with circuitry outside of the region (see interconnections between FPGA’s and connections within the FPGA, where critical path routing can occur in an FPGA region(s) before additional place & route compiling including routing/interconnections between FPGA regions during compilation, Col 2 lines 5-25, in conjunction with Col 13, lines 1-15) . 10. With respect to claim 4, Hung teaches : wherein causing compilation of the design during the compilation window comprises compiling intra-region routes (see interconnections between FPGA’s and connections within the FPGA, where critical path routing can occur in an FPGA region(s) before additional place & route compiling including routing/interconnections between FPGA regions during compilation, Col 2 lines 5-25, in conjunction with Col 13, lines 1-15; compile is launched, Col 3, lines 12-25; timeline/window for compiling design into programmable chip, Col 3, lines 10-20; see compile time, Col 6, lines 10-20; see time period/window, Col 11, lines 50-55; see compilation/emulation timing windows, Col 14, lines 5-25) . 11. With respect to claim 5, Hung teaches : wherein the intra-region routes comprise routes between processing elements of the programmable fabric or within processing elements of the programmable fabric (see critical timing paths for FPGA’s into a first set of logic elements, Col 15, lines 20-35) . 12. With respect to claim 6, Hung teaches : wherein the at least some routing comprises native multiplexers of the programmable fabric (see programmable sockets including multiplexing units, Col 2, lines 35-45) . 13. With respect to claim 7, Hung teaches : wherein determining the at least some routing comprises adding or modifying routing after the compilation window (some routing can be launched sequentially after initial compile, Col 3, lines 30-45; change circuitry, Col 10, lines 1-12; additional/changing connection routing, Col 4, lines 25-30; instructions modified to focus on routing, Col 4, lines 55-64; add functions of the DUT, Col 10, lines 1-12; compilation stage including changes to achieve better run-time performance, including updates/changes to place and route, timing, connection of FPGA subsets, Col 2, lines 1-25) . 14. With respect to claim 8, Hung teaches : wherein adding or modifying routing comprises using an engineering change order (see change order, compiler may change, reconfigure, add new functions for DUT design, Col 10, lines 5-15; user allowing to make changes in debug mode, Col 13, lines 35-45) . 15. With respect to independent claim 9, Hung teaches : A method, comprising: receiving a design for a programmable fabric of an integrated circuit device (see receiving HDL representing design, Fig 9, at 205; see Fig 9, showing HDL compiled for programming into a programmable hardware fabric, as shown in fig 9) ; compiling the design with at least some routing for an implementation of the design not being compiled with the rest of the design (compilation of FPGA with timing critical paths, while other non-critical timing paths can be placed/routed separately, Col 3, lines 25-35) ; determining to add or modify a route of the at least some routing (some routing can be launched sequentially after initial compile, Col 3, lines 30-45) ; changing the route (change circuitry, Col 10, lines 1-12; additional/changing connection routing, Col 4, lines 25-30; instructions modified to focus on routing, Col 4, lines 55-64) ; and utilizing the design to configure the programmable fabric to perform a function using the changed route (add functions of the DUT, Col 10, lines 1-12; compilation stage including changes to achieve better run-time performance, including updates/changes to place and route, timing, connection of FPGA subsets, Col 2, lines 1-25) . 16. With respect to claim 10, Hung teaches : wherein the at least some routing for the implementation of the design comprises default pre-configured routes (see use of overlay with place and route included, place and route already compiled onto the design, thus saving money, Col 1, lines 35-45; parallel FPGA place and route is performed by compiler and later substituted for overlay place and route, Col 5, lines 10-25) . 17. With respect to claim 11, Hung teaches : wherein the at least some routing comprises no external routes extending outside of a region until after compilation of the design (see interconnections between FPGA’s and connections within the FPGA, where critical path routing can occur in an FPGA region(s) before additional place & route compiling including routing/interconnections between FPGA regions during compilation, Col 2 lines 5-25, in conjunction with Col 13, lines 1-15) . 18. With respect to claim 12, Hung teaches : wherein changing the route includes removing the route, adding an additional route, replacing the route, or combination thereof (see interconnections between FPGA’s and connections within the FPGA, where critical path routing can occur in an FPGA region(s) before additional place & route compiling including routing/interconnections between FPGA regions during compilation, Col 2 lines 5-25, in conjunction with Col 13, lines 1-15) . 19. With respect to claim 13, Hung teaches : saving the changed route to a library (see design stored in a library, Col 8, lines 10-20, Col 9, lines 10-20; see memory and database, Col 7, lines 10-25) . 20. With respect to claim 14, Hung teaches : wherein determining whether to add or modify the route comprises prioritizing using routes that are pre-compiled over routes that are yet to be compiled (see use of overlay with place and route included, place and route already compiled onto the design, thus saving time/resources, Col 1, lines 35-45; parallel FPGA place and route is performed by compiler and later substituted for overlay place and route, Col 5, lines 10-25; see interconnections between FPGA’s and connections within the FPGA, where critical path routing can occur in an FPGA region(s) before additional place & route compiling including routing/interconnections between FPGA regions during compilation, Col 2 lines 5-25, in conjunction with Col 13, lines 1-15) . 21. With respect to independent claim 15, Hung teaches : An electronic device (see device/apparatus of Fig 9, showing HDL DUT as input to compiler for programming hardware, Col 9, lines 50-60) , comprising: memory storing instructions (see computer system parts [memory, processor, etc.] to carry out compiling programs into programmable hardware, Fig 7-8) and a plurality of routing layers each indicating one or more pre-compiled routes available for use in a design (see compilation of critical path routes first, for fpga compilation in stages, Col 2, lines 5-19) ; and a processor, that when executing the instructions (see computer system parts [memory, processor, etc.] to carry out compiling programs into programmable hardware, Fig 7-8) , is to: receive the design for a programmable fabric of an integrated circuit device (see receiving HDL representing design, Fig 9, at 205; see Fig 9, showing HDL compiled for programming into a programmable hardware fabric, as shown in fig 9) ; compile the design with local routing within a region during a compilation window (compile is launched, Col 3, lines 12-25; timeline/window for compiling design into programmable chip, Col 3, lines 10-20; see compile time, Col 6, lines 10-20; see time period/window, Col 11, lines 50-55; see compilation/emulation timing windows, Col 14, lines 5-25; solving/reducing long compile times by not needing all routing to be completed during initial compile, doing some place & route later in sequential routing after initial compile, Col 3, lines 30-45; no urgency to finish all routing during initial compile window, Col 3, lines 30-45) ; receive an indication of one or more of the plurality of routing layers (see multiple FPGA’s, place & routes in parallel, then combining them into one bitstream, see Fig 3A; merging altogether, Col 11, lines 60-67) ; merge the one or more of the plurality of routing layers with the design with local routing to generate a configuration bitstream (see multiple FPGA’s, place & routes in parallel, then combining them into one bitstream, see Fig 3A) ; and utilize the configuration bitstream to configure the programmable fabric of the integrated circuit device (see receiving HDL representing design, Fig 9, at 205; see Fig 9, showing HDL compiled for programming into a programmable hardware fabric, as shown in fig 9) . 22. With respect to claim 16, Hung teaches : wherein the instructions are part of design software stored in the memory and implemented by the processor (see design stored in a library, Col 8, lines 10-20, Col 9, lines 10-20; see memory and database, Col 7, lines 10-25) . 23. With respect to claim 17, Hung teaches : wherein a routing layer of plurality of routing layers comprises a single route for the region (routing layers, HDL description, other levels of abstraction, higher and lower levels, Col 8, lines 1-15) . 24. With respect to claim 18, Hung teaches : wherein the instructions, when executed, are to cause the processor to merge the one or more of the plurality of routing layers into a composite routing layer before merging the one or more of the plurality of routing layers with the design with local routing (see multiple FPGA’s, place & routes in parallel, then combining them into one bitstream, see Fig 3A; merging altogether, Col 11, lines 60-67; see multiple FPGA’s, place & routes in parallel, then combining them into one bitstream, see Fig 3A) . 25. With respect to claim 19, Hung teaches : wherein a routing layer of the plurality of routing layers comprises multiple routes indicated in the routing layer (routing layers, HDL description, other levels of abstraction, higher and lower levels, Col 8, lines 1-15) . 26. With respect to claim 20, Hung teaches : wherein the local routing comprises between processing elements of the region or within a processing element of the region, and the pre-compiled routes extend to a boundary of the region (see use of overlay with place and route included, place and route already compiled onto the design, thus saving time/resources, Col 1, lines 35-45; parallel FPGA place and route is performed by compiler and later substituted for overlay place and route, Col 5, lines 10-25; see interconnections between FPGA’s and connections within the FPGA, where critical path routing can occur in an FPGA region(s) before additional place & route compiling including routing/interconnections between FPGA regions during compilation, Col 2 lines 5-25, in conjunction with Col 13, lines 1-15) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851 Application/Control Number: 18/191,785 Page 2 Art Unit: 2851 Application/Control Number: 18/191,785 Page 3 Art Unit: 2851 Application/Control Number: 18/191,785 Page 4 Art Unit: 2851 Application/Control Number: 18/191,785 Page 5 Art Unit: 2851 Application/Control Number: 18/191,785 Page 6 Art Unit: 2851 Application/Control Number: 18/191,785 Page 7 Art Unit: 2851 Application/Control Number: 18/191,785 Page 8 Art Unit: 2851 Application/Control Number: 18/191,785 Page 9 Art Unit: 2851
Prosecution Insights