DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 12-14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0143721 A1 to Chu et al. (Chu) and US 2014/0306979 A1 to Chun et al. (Chun).
As to claim 1, Chu discloses a display device comprising: a first interface (L)(Fig. 1, Par. 3); a timing controller (100) providing reference data (test code stream) to a first transmitter of to the first interface (H) (Figs. 1-3, Pars. 48-50); and data driver (200) receiving the reference data (becomes encoded code stream) through a first receiver of the first interface (H) (Figs. 1-3, Pars. 48-50) and comparing a value of the reference data (value of test code stream) with a predetermined value (encoded code stream received by 200) to detect whether signal transmission quality of the first interface (H) has an error (Steps: 203-205; the test code stream does not matching with the encoded code stream) (Figs. 1-3, Pars, 50-52, 55), wherein the reference data (test code stream) is transmitted from the first transmitter (of 100) to the first receiver (of 200) via the first interface (H) (Figs. 1-2b, Pars. 50-52), wherein the timing controller (100) changes a transmission state of the first interface (H) when the error is detected in the signal transmission quality of the first interface (H) (Figs. 1-2b, Pars. 50-52, 68, 88-89); and the transmission state of the first interface includes at least one of a transmission frequency of the first interface (Pars. 74-75).
Chu does not expressly disclose the comparing of the reference data with the predetermined value is done in the timing controller.
However, Chu discloses the method may be implemented by the timing controller (Par. 41).
Chun discloses the timing controller (400) compares a first reference data (CUR) with a second reference data (data from 414) (Fig. 2, Pars. 60, 65), and wherein the transmission state of the first interface includes a driving current of the first interface (Fig. 3, Pars. 60, 62, 64).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Chun to reduce error thereby provide an improved display as suggested by Chun (Par. 9) and the location for performing comparing step is an obvious design choice.
As to claim 12, see claim 1 rejection and motivation above.
As to claim 2, Chu as modified discloses the timing controller (Chu’s 100, Chun’s 400) includes: a detector (Chu’s 430, Chun’s 413, 415) comparing the value of the first reference data (test code stream) with the predetermined value (decoded code stream) to detect the signal transmission quality of the first interface (Chu’s Figs. 1-4, Pars. 37-38, 41, 88, Chun’s Figs. 1, 3, Pars. 60, 62-64); and a transmission state controller (Chu’s 440, Chun’s 416) changing the transmission state of the first interface (Chu’s Figs. 1-4, Par. 89, see also Pars. 50-52, 68). See claim 1 motivation above.
As to claim 3, Chu as modified discloses the detector compares a value of the reference data with the predetermined value for each bit to detect the signal transmission quality of the first interface (Chu’s Figs. 1-4, Pars. 66-68), and wherein the detector determines that there is the error in the signal transmission quality of the first interface when the value of the reference data and the predetermined value have different data values from each other in at least one bit (Chu’s Figs. 1-4, Pars. 66-68).
As to claim 13, see claims 2 and 3 rejection and motivation above.
As to claim 14, see claim 13 rejection and motivation above.
As to claim 4, Chu as modified discloses the detector (Chu’s 430, Chun’s 413, 415) generates a first reception state abnormal signal when there is the error in the signal transmission quality of the first interface (Chu’s Figs. 1-3, Pars. 48-52, 88-89, Chun’s Figs. 1, 3, Pars. 60, 62-64), and wherein the transmission state controller (Chu’s 440, Chun’s 416) generates a transmission state control signal for changing the transmission state of the first interface based on the first reception state abnormal signal (Chu’s Figs. 1-3, Pars. 48-52, 88-89, Chun’s Figs. 1, 3, Pars. 60, 62-65). See claim 1 motivation above.
As to claim 5, Chu as modified discloses a second interface (Chu’s L) (Chu’s Pars. 3, 37, 44-45), wherein the timing controller (Chu’s 100) provides the transmission state control signal to a second transmitter (of 100) of the second interface (Chu’s Figs. 1-4, Pars. 41, 48-52, 88-89, Chun’s Figs. 1, 3, Pars. 60, 62-65), and wherein the data driver (Chu’s 200) changes the driving current of the first interface based on the transmission state control signal (Chu’s Figs. 1-3, Pars. 48-52, 88-89, Chun’s Figs. 1, 3, Pars. 60, 62-65). See claim 1 motivation above.
As to claim 7, Chu as modified discloses the detector (Chu’s 430) generates an inspection end signal and provides the inspection end signal to the data driver when there is no error in the signal transmission quality of the first interface (Chu’s Figs. 1-3, Pars. 48-52, 88-89, Chun’s Figs. 1, 3, Pars. 60-65). See claim 1 motivation above.
As to claim 17, Choi as modified discloses the changing of the transmission state of the first interface includes: generating a drive current code for controlling a drive current of the first transmitter of the first interface (Chu’s Figs. 1-4, Pars. 41, 48-52, 88-89, Chun’s Fig. 3, Pars. 60, 62, 64). See claim 12 motivation above.
Claim(s) 8, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0143721 A1 to Chu et al. (Chu) and US 2014/0306979 A1 to Chun et al. (Chun); in view of US 2012/0242628 A1 to Yuan et al. (Yuan).
As to claim 8, Choi as modified does not expressly disclose the reference data includes the predetermined value having a specific pattern.
Yuan discloses the reference data includes the predetermined value having a specific pattern (Par. 28, e.g. Fig. 3: steps 307-309).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Yuan to minimize loss of transmission data as suggested by Yuan (Par. 30).
As to claim 15, see claim 8 rejection and motivation above.
Claim(s) 10, 11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0143721 A1 to Chu et al. (Chu) and US 2014/0306979 A1 to Chun et al. (Chun); in view of US 2014/0084792 A1 to Oh et al. (Oh).
As to claim 10, Choi as modified does not expressly disclose a power supply generating a driving power source, wherein the timing controller blocks generation of the driving power source of the power supply when the error is detected in the signal transmission quality of the first interface.
Oh discloses a power supply (180) generating a driving power source (Figs. 1, Pars. 60, 108), wherein the timing controller blocks generation of the driving power source of the power supply when the error is detected in the signal transmission quality of the first interface (Figs. 1, Pars. 60, 108).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Oh to prevent damage to the display as suggested by Oh (Par. 62).
As to claim 11, see claims 1 and 10 rejection and motivation above.
As to claim 20, see claim 10 rejection and motivation above.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable US 2020/0143721 A1 to Chu et al. (Chu) and US 2014/0306979 A1 to Chun et al. (Chun); in view of US 2015/0054798 A1 to Park et al. (Park).
As to claim 16, Choi as modified does not expressly disclose the changing of the transmission state of the first interface includes: generating a frequency divider code for controlling a frequency of a data transmission clock signal of the first interface.
Park discloses generating a frequency divider code for controlling a frequency of a data transmission clock signal of the first interface (Par. 72).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Park to enhance signal quality of the interface as suggested by Park (Par. 72).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable US 2020/0143721 A1 to Chu et al. (Chu) and US 2014/0306979 A1 to Chun et al. (Chun); in view of US 2016/0043761 A1 to Kim et al. (Kim).
As to claim 16, Choi as modified does not expressly disclose the changing of the transmission state of the first interface includes: generating a termination resistance code for controlling a termination resistance of the first transmitter of the first interface.
Kim discloses the changing of the transmission state of the first interface includes: generating a termination resistance code for controlling a termination resistance of the first transmitter of the first interface (Figs. 10-11, Abstract, Par. 7).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Kim to improve signal quality as suggested by Kim (Par. 7).
Claim(s) 6, 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable US 2020/0143721 A1 to Chu et al. (Chu) and US 2014/0306979 A1 to Chun et al. (Chun); in view of US 2021/0058164 A1 to Song et al. (Song) and US 2016/0043761 A1 to Kim et al. (Kim).
As to claim 6, Choi as modified does not expressly a controller for generating a frequency divider code, a driving current code and a termination resistance code.
Song teaches a device comprising a frequency controller(400, 410, 450) generating a frequency divider code(vary frequency) for controlling a frequency of a data transmission clock signal of a first interface(see Figs. 2, 5-7; [0025, 0049, 0050, 0056, 0066-0067, 0118, 0119, 0120]), a driving current controller generating a driving current code (vary current) for controlling a driving current of a first transmitter(400, 410) of the first interface (see Figs. 2, 6-7; [0025, 0056,0065, 0067, 0118, 0119, 0120]]),: and
resistor controller generating a resistance code for controlling a resistance of the first transmitter (400, 410)(see Figs. 2, 6-7; [0056,0065, 0067, 0118, 0119, 0120]]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Song, so as to maximizing the convenience for data transmission in different frequency.
Choi as modified does not expressly a device for generating a termination resistance code for controlling a termination resistance of the first transmitter of the first interface.
Kim discloses the changing of the transmission state of the first interface includes: generating a termination resistance code for controlling a termination resistance of the first transmitter of the first interface (Figs. 10-11, Abstract, Par. 7).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Choi with the teaching of Kim to improve signal quality as suggested by Kim (Par. 7).
As to claims 9 and 19, see claim 6 rejection and motivation above. Choi as modified further discloses the timing controller changing the transmission state includes sequentially changes the transmission frequency, the driving current, and the termination resistance of the first interface when the error is detected in the signal transmission quality of the first interface (Chu’s Fig. 3, Par. 82, Song’s Figs. 2, 6-7; [0056,0065, 0067, 0118, 0119, 0120]], Kim’s Figs. 10-11, Abstract, Par. 7, Chu teaches repeating the process when the received signal still does not match the sent signal, and Song and Kim teach changing the transmission frequency, the driving current, and termination resistance). It would have been obvious to one of ordinary skill in the art to try with a reasonable expectation of success to change the transmission state by sequentially change the transmission frequency, the driving current, and the termination resistance of the first interface when an error is detected in the signal transmission quality of the first interface to improve signal quality as suggested by Kim (Par. 7).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground(s) of rejection.
On page 13 of the Remarks, Applicant argues that “Chu does not disclose nor suggest "a data driver providing reference data to a first transmitter of the first interface; and a timing controller receiving the reference data through a first receiver of the first interface and comparing a value of the reference data with a predetermined value to detect whether signal transmission quality of the first interface has an error . ..," as recited in amended claim 1. The Examiner respectfully disagrees since Chu clearly teaches data driver (200) receiving the reference data (becomes encoded code stream) through a first receiver of the first interface (H) (Figs. 1-3, Pars. 48-50) and comparing a value of the reference data (value of test code stream) with a predetermined value (encoded code stream received by 200) to detect whether signal transmission quality of the first interface (H) has an error (Steps: 203-205; the test code stream does not matching with the encoded code stream) (Figs. 1-3, Pars, 50-52, 55), wherein the reference data (test code stream) is transmitted from the first transmitter (of 100) to the first receiver (of 200) via the first interface (H) (Figs. 1-2b, Pars. 50-52), wherein the timing controller (100) changes a transmission state of the first interface (H) when the error is detected in the signal transmission quality of the first interface (H) (Figs. 1-2b, Pars. 50-52, 68, 88-89); and the transmission state of the first interface includes at least one of a transmission frequency of the first interface (Pars. 74-75).
On pages 15-16 of the Applicant’s Remarks, the Applicant argues that Chu and Chun do not teach “a data driver providing reference data to a first transmitter of the first interface; and a timing controller receiving the reference data through a first receiver of the first interface and comparing a value of the reference data with a predetermined value to detect whether signal transmission quality of the first interface has an error…because reversing Chu's data flow would require a fundamental change in the Chu's principle of operation and architecture”. The Examiner respectfully disagrees. Chu clearly teaches that the method of detecting whether signal transmission quality of the first interface has an error recited in all independent claims as addressed in the office action. Chu further teaches the method may be implemented by the timing controller (Par. 41; i.e. “the method may be implemented by, e.g., the timing controller 100 in an environment as shown in FIG. 1” as stated in Chu). Furthermore, examiner only uses the reference of Chun to emphasize the performing of comparison between two data information in the timing controller (400). It is noted that the controller (400) of Chun is absolutely a timing controller since it receives all the timing signals (MCLK, Vsync and Hsync and DE signals.). Therefore, it does not change Chu's principle of operation and architecture because Chu clearly teaches that the principal of method detecting whether signal transmission quality of the first interface has an error recited in all independent claims as addressed in the office action and further teaches the method may be implemented by the timing controller.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2016/0155381 A1 to Kwon et al. teaches a display with a data driver comprising of a plurality of current measurement units.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARURAT SUTEERAWONGSA whose telephone number is (571)270-7361. The examiner can normally be reached Monday thru Thursday, 8:30AM to 4:00PM, EST.
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/JARURAT SUTEERAWONGSA/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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