DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species A and 1 in the reply filed on 12/23/2025 is acknowledged. Claims 1-20 are examiner on the merits. Claims 21-27 are cancelled.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title be amended to include the phrase “including varying widths along stack contacts.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6-7, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20220139831 A1 to Kim et al. (hereinafter “Kim”) in view of U.S. Pat. Pub. No. US 20210335814 A1 to Zhang et al. (hereinafter “Zhang”).
Regarding claim 1, Kim teaches a semiconductor device (fig. 3A), comprising:
a first gate stack (lower stack LS’; fig. 3A) [0047] including first insulating patterns (38; fig. 3A) [0048] and first conductive patterns (lower gate layers 115L; fig. 3A) [0047], which are alternately stacked with each other (see fig. 3A or 16);
a second gate stack (upper stack US’; fig. 3A) [0047] provided on the first gate stack (LS’), the second gate stack (US’) including second insulating patterns (62; fig. 3A) [0048] and second conductive patterns (upper gate layers 115U; fig. 3A), which are alternately stacked with each other (see fig. 3A or 16);
a memory channel structure (81; fig. 3A) [0034] penetrating the first gate stack (LS’) and the second gate stack (US’);
a penetration contact (first gate contact plugs 136_1; fig. 3A) [0058] penetrating the first gate stack (LS’) and the second gate stack (US’); and
a barrier pattern (pattern of 115U and 109a, hereinafter “barrier pattern”; fig. 10B) [0146] provided on opposite sides (opposite sides in the x-direction, for example; fig. 10B) of the penetration contact (136_1),
wherein the first insulating patterns (38) comprise a first connection insulating pattern (38U; fig. 3A) [0048], which is the uppermost (vertically upper in the z-direction of fig. 3A) one of the first insulating patterns (38),
the second insulating patterns (62) comprise a second connection insulating pattern (62L; fig. 3A) [0048] which is in contact with a top surface (vertically upper) of the first connection insulating pattern (38U),
Kim does not teach:
a bottom surface of the barrier pattern is in contact with the top surface of the first connection insulating pattern, and
a top surface of the barrier pattern is in contact with the second connection insulating pattern.
Zhang, however, teaches a semiconductor device (fig. 1A) comprising a memory channel structure (116; fig. 1A) [0071] and a penetration contact (106; fig. 1A) [0027], wherein:
a bottom surface (vertically bottom in fig. 1A) of the barrier pattern (insulating spacer 114; fig. 1A) [0034] is in contact with the top surface (vertically top) of the first connection insulating pattern (uppermost portion of 114 in 104-1; fig. 1A) [0027], and
a top surface (vertically top) of the barrier pattern (114) is in contact with the second connection insulating pattern (lower portion of 114 in 104-2; fig. 1A) [0027].
It would have been obvious to a person of ordinary skill in the art to modify the barrier pattern of Kim to be disposed in contact with the first and second connection insulating patterns to insulate the penetration contact as taught by Zhang [0033] & [0034].
Additionally, the above modification allows for the conductor layers (120) of the structure of Zhang to be disposed closer to the interface of the first and second connection insulating patterns (because they are insulated by the barrier layer), thus allowing for higher circuit density. It thus further would have further been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify the barrier layer of Kim to be in contact with first and second connection insulating pattern to increase the circuit density of Kim.
Regarding claim 2, Kim in view of Zhang teaches the semiconductor device of claim 1, wherein the barrier pattern (barrier pattern) comprises an inner barrier layer (buffer insulating patter 109a; fig. 10B) [0146] encircling (surrounding; see fig. 1A) the penetration contact (136_1) and an outer barrier layer (first layer 115a; fig. 10B) [0087] encircling (surrounding) the inner barrier layer (109a).
Regarding claim 3, Kim in view of Zhang teaches the semiconductor device of claim 2, wherein the outer barrier layer (115a) [0088] comprises a material different (115a comprising AlO [0088] and 38U/62L comprising SiO [0205]) from the first connection insulating pattern (38U) and the second connection insulating pattern (62L).
Regarding claim 6, Kim in view of Zhang teaches the semiconductor device of claim 1, wherein the barrier pattern (barrier pattern) has a circular shape (as the contact 136_1 has a circular shape, see fig. 1A, the contact 136_1 defining the shape of the barrier pattern, it follows that the barrier pattern has a circular shape).
Regarding claim 7, Kim in view of Zhang teaches the semiconductor device of claim 1, wherein a side surface of the barrier pattern (barrier pattern) is in contact with the second connection insulating pattern (62L).
Regarding claim 19, Kim teaches an electronic system, comprising: a substrate;
a semiconductor device on the substrate (2001; fig. 28) [0258]; and
a controller (2002; fig. 28) [0258], which is provided on the substrate (2001) and is electrically connected to the semiconductor device (DRAM 2004; fig. 28) [0258],
wherein the semiconductor device (2004 as considered as overlapping in scope with other embodiments of the disclosure of Kim) comprises:
a first gate stack (lower stack LS’; fig. 3A) [0047] including first insulating patterns (38; fig. 3A) [0048] and first conductive patterns (lower gate layers 115b of 115L; fig. 3A and 10B) [0047], which are alternately stacked with each other (see fig. 3A or 16);
a second gate stack (upper stack US’; fig. 3A) [0047] provided on the first gate stack (LS’), the second gate stack (US’) comprising second insulating patterns (62; fig. 3A) [0048] and second conductive patterns (upper gate layers 115b of 115U; fig. 3A and 10B), which are alternately stacked with each other (see fig. 3A or 16);
a memory channel structure (81; fig. 3A) [0034] penetrating the first gate stack (LS’) and the second gate stack (US’);
a penetration contact (first gate contact plugs 136_1; fig. 3A) [0058] penetrating the first gate stack (LS’) and the second gate stack (US’); and
a barrier pattern (pattern of 115a; fig. 10B) [0146] surrounding (being all around; see fig. 1A) the penetration contact (136_1),
wherein the first gate stack (LS’) further comprises first contact insulating patterns (contact conductive liner layer 138a; fig. 10B) [0122] disposed on first (left side in fig. 10B) and second (right side in fig. 10B) sides of the penetration contact (136_1),
the second gate stack (US’) further comprises second contact insulating patterns (buffer insulating patterns 109a; fig. 10B) [0146] disposed on the first (left) and second (right) sides of the penetration contact (136_1),
the first insulating patterns (38) comprise a first connection insulating pattern (38U; fig. 3A) [0048], which is disposed at a level higher (at least partially) than the first conductive patterns (115b of 115L) and the first contact insulating patterns (138a),
the second insulating patterns (62) comprise a second connection insulating pattern (62L; fig. 3A) [0048], which is disposed at a level lower (at least partially) than the second conductive patterns (115b of 115U) and the second contact insulating patterns (109a),
Kim does not teach:
the barrier pattern is disposed on a top surface of the first connection insulating pattern, and the second connection insulating pattern is in contact with a top surface of the barrier pattern.
Zhang, however, teaches a semiconductor device (fig. 1A) comprising a memory channel structure (116; fig. 1A) [0071] and a penetration contact (106; fig. 1A) [0027], wherein:
the barrier pattern (insulating spacer 114; fig. 1A) [0034] is disposed on a top surface (vertically top) of the first connection insulating pattern (uppermost portion of 114 in 104-1; fig. 1A) [0027], and the second connection insulating pattern (lower portion of 114 in 104-2; fig. 1A) [0027] is in contact with a top surface (vertically top) of the barrier pattern (114).
It would have been obvious to a person of ordinary skill in the art to modify the barrier pattern of Kim to be disposed in contact with the first and second connection insulating patterns to insulate the penetration contact as taught by Zhang [0033] & [0034].
Additionally, the above modification allows for the conductor layers (120) of the structure of Zhang to be disposed closer to the interface of the first and second connection insulating patterns (because they are insulated by the barrier layer), thus allowing for higher circuit density. It thus further would have further been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify the barrier layer of Kim to be in contact with first and second connection insulating pattern to increase the circuit density of Kim.
Regarding claim 20, Kim in view of Zhang teaches the electronic system of claim 19, wherein the second connection insulating pattern (62L) is in contact (thermal or electrical) with a side surface of the barrier pattern (115b of 115U).
Claims 4-5 /are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zhang as applied to claim 3 above, and further in view of U.S. Pat. Pub. No. US 20210091102 A1, which is of record, to Zhu et al. (hereinafter “Zhu”).
Regarding claim 4, Kim in view of Zhang do not teach the semiconductor device of claim 3, wherein the inner barrier layer (109a) comprises the same material as the first connection insulating pattern (38U) and the second connection insulating pattern (62L) (requiring that the inner barrier layer be comprised of silicon dioxide).
Zhu, however, teaches a semiconductor device (fig. 1) comprising a memory channel structures (110; fig. 1) [0023] and a penetration contact (122; fig. 1) [0023], wherein the inner barrier layer (interior portion of barrier 108, barrier 108 being taught as comprising one or more dielectric layers, one of these dielectric layers being the inner barrier layer; fig. 1) [0031] comprises silicon dioxide [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the material of the inner barrier layer of Kim in view of Zhang to comprise silicon dioxide to provide an effective barrier as taught by Zhu [0030].
Regarding claim 5, Kim in view of Zhang and Zhu, as presently modified, does not teach the semiconductor device of claim 4, wherein the inner barrier layer comprises an oxide material, and the outer barrier layer comprises a nitride material.
Zhu, however, teaches that the barrier layer (108) may be comprised of one or more of silicon oxide and silicon nitride (providing a finite list of materials) [0031] to provide a barrier between a through contact (122; fig. 1) [0022] and an outside portion (104; fig. 1) [0023] of a memory stack (fig. 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the inner barrier layer of Kim in view of Zhang and Zhu to comprise an oxide material and the outer barrier layer to comprise a nitride material to provide an effective barrier as taught by Zhu [0030] as a matter of obvious to try i.e., Zhu establishes a finite list of materials used to provide a barrier, the list including silicon oxide and silicon nitride. M.P.E.P. 2143 I (E).
It is further noted that the use of silicon oxide and silicon nitride as an electrical barrier/separator/dielectric amounts to a use of a known material(s) for its intended purpose i.e., using dielectric materials as a barrier layer. M.P.E.P. 2144.07.
Claims 10, 12-13, 15, & 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of U.S. Pat. Pub. No. US 20190280003 A1 to Mushiga et al. (hereinafter “Mushiga”).
Regarding claim 10, Kim teaches a semiconductor device, comprising:
a first gate stack (lower stack LS’; fig. 3A) [0047] including a first insulating pattern (38; fig. 3A) [0048] and a first conductive pattern (lower gate layers 115b; fig. 3A) [0047], which are alternately stacked with each other (see fig. 3A or 16);
a second gate stack (upper stack US’; fig. 3A) [0047] provided on the first gate stack (LS’), the second gate stack (US’) including a second insulating pattern (62; fig. 3a) [0048] and a second conductive pattern (upper gate layers 115U; figs. 3A & 10B) [0047], which are alternately stacked with each other (see fig. 3A or 16);
a memory channel structure (81; fig. 3A) [0034] penetrating the first gate stack (LS’) and the second gate stack (US’);
a penetration contact (first gate contact plugs 136_1; fig. 3A) [0058] penetrating the first gate stack (LS’) and the second gate stack (US’); and
a barrier pattern (pattern of 115a; fig. 10B) [0144] provided on first (left side in fig. 10B) and second sides (right side in fig. 10B) of the penetration contact (136_1),
wherein the first gate stack (LS’) further comprises a first contact insulating pattern (contact conductive liner layer 138a; fig. 10B) [0122] provided on the first (left) and second (right) sides of the penetration contact (136_1),
the second gate stack (US’) further comprises a second contact insulating pattern (buffer insulating patterns 109a; fig. 10B) [0146] provided on the first (left) and second (right) sides of the penetration contact (136_1), and
Kim does not teach
the barrier pattern is disposed between the first contact insulating pattern and the second contact insulating pattern.
Mushiga, however, teaches a semiconductor device (figs. 39A-40) comprising a staircase memory structure (20; fig. 40) [0136] and a opening fill portion (984; fig. 40) [0270], wherein:
the barrier pattern (inter-tier dielectric 180; fig. 39A) [0151] is disposed between the first contact insulating pattern (first insulating layers 132; fig. 39A) [0140] and the second contact insulating pattern (second insulating layers; fig. 39A) [0168].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Kim to dispose the barrier layer between the first and second contact insulating pattern to allow for lithography patterning (patterning regarding the shape of the contacts 984) as taught by Mushiga [0152].
Regarding claim 12, Kim in view of Mushiga teaches the semiconductor device of claim 10, wherein the barrier pattern (115a) is overlapped (at least partially with respect to a view in the z-direction and a view with an angular shift from the z-direction; see fig. 10B) with the first contact insulating pattern (138a) and the second contact insulating pattern (109a).
Regarding claim 13, Kim in view of Mushiga teaches the semiconductor device of claim 10, wherein the first contact insulating pattern (138a) is disposed between (see fig. 10B in view of the below note) the first conductive pattern (115b) and the penetration contact (136_1), and the second contact insulating pattern (109a) is disposed between the second conductive pattern (115U) and the penetration contact (136_1) (see fig. 10B).
It is noted that the view of fig. 10B explicitly shows a gate contact portion 136E1 disposed in the second stack US’. However, with reference to fig. 3A, these gate contact portions are also disposed in the first stack LS’. The view of fig. 10B is thus considered as applicable to the first stack LS’, the necessary tagline designations changed to match the corresponding elements in the first stack LS’ e.g., 115U of the second stack US’ would be 115L in fig. 10B.
Regarding claim 15, Kim in view of Mushiga, as currently modified, does not teach the semiconductor device of claim 10, wherein the barrier pattern comprises an inner barrier layer encircling the penetration contact and an outer barrier layer encircling the inner barrier layer.
Mushiga, however, teaches wherein the barrier pattern (memory film 05; fig. 39E) [0190] comprises an inner barrier layer (tunneling dielectric layer 56; fig. 39E) [0190] encircling the penetration contact (opening fill structure 58; fig. 39E) [0196] and an outer barrier layer (blocking dielectric layer 52; fig. 39E) [0188] encircling the inner barrier layer (56).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the barrier pattern of Kim in view of Mushiga to comprise an inner and outer barrier layer to allow for memory material to form between these two layers as taught by Mushiga [0189].
Regarding claim 17, Kim in view of Mushiga teaches the semiconductor device of claim 15, wherein the inner barrier layer (56 of Mushiga modified to be added to 115a of Kim) is overlapped (when viewed in a horizontal direction of Kim in fig. 10B) with the first contact insulating pattern (138a of Kim as modified by 132 of Mushiga) and the first conductive pattern (115b of Kim), and the outer barrier layer (52 of Mushiga as modified to be added to 115a of Kim) is overlapped (when viewed in a horizontal direction of Kim in fig. 10B) with the first conductive pattern (115b of Kim).
Regarding claim 18, Kim in view of Mushiga teaches the semiconductor device of claim 10, wherein the penetration contact (136_1) comprises a plurality of penetration contacts (see fig. 2), the barrier pattern (115a) comprises a plurality of barrier patterns (see fig. 2 wherein the view of 10B is present in each penetration contact), each of the plurality of barrier patterns (115a) is provided to encircle (see fig. 1A and 10B) a corresponding one of the plurality of penetration contacts (136_1), and the plurality of barrier patterns (115a) are spaced apart from each other (horizontally).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Mushiga as applied to claim 10 above, and further in view of Zhang.
Regarding claim 14, Kim in view of Mushiga teaches the semiconductor device of claim 10, wherein the penetration contact (136_1) comprises a first penetration portion (portion in first stack LS’) penetrating the first gate stack (LS’) and a second penetration portion (portion in stack US’) on the first penetration portion (portion in LS’).
Kim in view of Mushiga does not teach a top surface of the barrier pattern is coplanar with a top surface of the first penetration portion.
Zhang, however, teaches a semiconductor device (fig. 1A) comprising a memory channel structure (116; fig. 1A) [0071] and a penetration contact (106; fig. 1A) [0027], wherein:
a top surface (vertically top) of the barrier pattern (insulating spacer 114; fig. 1A) [0034] is coplanar with a top surface (vertically top) of the first penetration portion (portion of 106 in 104-1; fig. 1A)
It would have been obvious to a person of ordinary skill in the art to modify the barrier pattern of Kim in view of Mushiga to be disposed coplanar with a top surface of the first penetration portion to insulate the penetration contact as taught by Zhang [0033] & [0034].
Additionally, the above modification allows for the conductor layers (120) of the structure of Zhang to be disposed closer to the interface of the first and second connection insulating patterns (because they are insulated by the barrier layer), thus allowing for higher circuit density. It thus further would have further been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify the barrier layer of Kim in view of Mushiga to be in contact with top surface of the first penetration contact to increase the circuit density of Kim in view of Mushiga.
Allowable Subject Matter
Claims 8-9, 11, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, it is not found a semiconductor device requiring all the elements of claim 1 in addition to the barrier pattern being disposed around the second penetration portion and comprising the width relationship of claim 8. Kim in view of Zhang would be required to have a wide base in order to read on claim 8 which is not found nor is there found a motivation to modify Kim in view of Zhang to meet this limitation. Claim 9 further comprises allowable subject matter by virtue of its dependence on claim 8.
Regarding claim 11, it is known that the thickness of an insulative material (e.g., a dielectric) can effect its insulative properties. However, it is not found a motivation to modify the thickness of the barrier pattern specifically. For example, the thickness of the contact insulating patterns could be modified to reach the same insulative tuning effect. A rejection of claim 11 would thus be untenable.
Claim 16 comprises allowable subject matter for the same reason as claim 11.
Conclusion
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892