DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species Group I corresponding to claims 1-12, 18, and 20 in the reply filed on 08/07/2025 is acknowledged.
Claims 13-17 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/07/20258.
Claim Objections
Claims 8-9 are objected to because of the following informalities:
Claim 8, lines 5-6 recite “a width of the upper portion of the conductive filling pattern being narrow than a width of…”. It is suggested to change the quoted phrase to “a width of the upper portion of the conductive filling pattern being narrower than a width of…” for grammatical formality. Appropriate correction is required.
Claim 9 is objected to based on its dependency on claim 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 7-11 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al in US 2007/0152257 A1 (hereinafter Park).
Regarding claim 1, Park teaches in FIG. 5 and related text, a semiconductor device comprising:
a first contact plug structure (57/57S/74, [0039-0044]) on a substrate (51, [0038]);
a lower spacer structure (55/69, [0039]/[0042]) on a sidewall of the first contact plug structure (57/57S/74); and
a bit line structure (77/78, [0044]) on the first contact plug structure (57/57S/74), the bit line structure (77/78) including a conductive structure (77, [0044]) and an insulation structure (78, [0044]) stacked in a vertical direction substantially perpendicular to an upper surface of the substrate (51),
wherein the first contact plug structure (57/57S/74) includes,
a conductive pad (57, [0039]) contacting the upper surface of the substrate (51),
an ohmic contact pattern (57S, [0040]) on the conductive pad (57), and
a conductive filling pattern (74, [0041]) on the ohmic contact pattern (57S), the conductive filling pattern (74) including metal ([0043]), and including a lower portion having a relatively large width and an upper portion having a relatively small width (see annotated FIG. 5 below), and
wherein the lower spacer structure (55/69) contacts a sidewall of the conductive filling pattern (74).
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Annotated FIG. 5 (Park)
Regarding claim 3, Park teaches the semiconductor device according to claim 1, wherein
an active pattern (52, [0038]) is on the substrate (51), and the conductive pad (57) contacts an upper surface of the active pattern (52), and
an area of an upper surface of the conductive pad (57) is greater than an area of the upper surface of the active pattern (52).
Regarding claim 7, Park teaches the semiconductor device according to claim 1. Park further teaches wherein the lower spacer structure (55/69) contacts sidewalls of the conductive pad (57), the ohmic contact pattern (57S) and the conductive filling pattern (74).
Regarding claim 8, Park teaches the semiconductor device according to claim 7. Park teaches further comprising:
a capping pattern (65, [0041]) covering a sidewall of the upper portion of the conductive filling pattern (74, see annotated FIG. 5 in the rejection of claim 1), an upper surface of the lower portion of the conductive filling pattern (74, annotated FIG. 5), and an upper surface of the lower spacer structure (55/69), a width of the upper portion of the conductive filling pattern being narrow than a width of the lower portion of the conductive filling pattern (annotated FIG. 1); and
an insulating filling pattern (89, [0047]) on the capping pattern (65).
Regarding claim 9, Park teaches the semiconductor device according to claim 8. Park teaches further comprising:
an upper spacer structure (79, [0044]) on the capping pattern (65) and the insulating filling pattern (89), the upper spacer structure (79) covering a sidewall of the bit line structure (77/78).
Regarding claim 10, Park teaches the semiconductor device according to claim 1. Park teaches further comprising:
an active pattern (52, [0038]) and an isolation pattern (53, [0038]) on the substrate (51), the isolation pattern (53) covering a sidewall of the active pattern (52),
wherein the first contact plug structure (57/57S/74) contacts an upper surface of a central portion of the active pattern (52).
Regarding claim 11, Park teaches the semiconductor device according to claim 10. Park teaches further comprising:
a conductive pad structure (56, [0039]) on the active pattern (52) and the isolation pattern (53), the conductive pad structure (56) overlapping at least a portion of the first contact plug structure (57/57S/74) in a horizontal direction substantially parallel to the upper surface of the substrate (51).
Regarding claim 18, Park teaches in FIG. 5 and related text, a semiconductor device comprising:
an active pattern (52, [0038]) on a substrate (51, [0038]);
a contact plug structure (57/57S/74, [0039-0044]) on the active pattern (52), the contact plug structure (57/57S/74) including,
a conductive pad (57, [0039]) on an upper surface of the active pattern (52),
an ohmic contact pattern (57S, [0040]) on the conductive pad (57), and
a conductive filling pattern (74, [0041]) on the ohmic contact pattern (57S),
a lower spacer structure (55/69, [0039]/[0042]) on a sidewall of the conductive pad (57);
a capping pattern (65, [0041]) on sidewalls of the ohmic contact pattern (57S, noting 65 is at least indirectly on top, bottom, and side surfaces of 57S) and the conductive filling pattern (74) and an upper surface of the lower spacer structure (55/69);
an insulating filling pattern (89, [0047]) on the capping pattern (65); and
a bit line structure (77/78, [0044]) on the contact plug structure (57/57S/74), the bit line structure (77/78) including a conductive structure (77, [0044]) and an insulation structure (78, [0044]) stacked in a vertical direction substantially perpendicular to an upper surface of the substrate (51).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al in US 2007/0152257 A1 (hereinafter Park) in view of Shin in US 2012/0126426 A1 (hereinafter Shin).
Regarding claim 2, Park teaches the semiconductor device according to claim 1. Park further teaches wherein the conductive pad (57) includes single crystalline silicon or polysilicon (polysilicon, [0039]), and the ohmic contact pattern (57S) includes metal silicide ([0040]).
Park does not explicitly state that the conductive pad (57) includes doped polysilicon.
Shin teaches in FIG. 2 and related text, a conductive pad (120c, [0038]) includes doped polysilicon ([0038]), in order to provide a contact plug with reduced resistance ([0029]).
Park and Shin are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Shin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive pad of Park such that it is doped polysilicon, as taught by Shin, in order to provide a contact plug with reduced resistance (Park, [0029]).
Regarding claim 20, Park teaches the semiconductor device according to claim 18. Park further teaches wherein the conductive pad (57) includes polysilicon ([0039]), the ohmic contact pattern (57S) includes metal silicide ([0040]), the conductive filling pattern (74) includes metal ([0043]), the capping pattern (65) includes silicon oxide ([0041]), and the insulating filling pattern (89) includes silicon nitride ([0047]).
Park does not explicitly state that the conductive pad (57) includes polysilicon doped with impurities.
Shin teaches in FIG. 2 and related text, a conductive pad (120c, [0038]) includes polysilicon doped with impurities ([0038]), in order to provide a contact plug with reduced resistance ([0029]).
Park and Shin are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Shin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive pad of Park such that it is doped with impurities, as taught by Shin, in order to provide a contact plug with reduced resistance (Park, [0029]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al in US 2007/0152257 A1 (hereinafter Park) in view of He in US 2021/0082923 A1 (hereinafter He).
Regarding claim 4, Park teaches the semiconductor device according to claim 3. Park does not explicitly state wherein an area of a lower surface of the conductive pad (57) is greater than an area of the upper surface of the active pattern (52).
He teaches in FIG. 4e and related text, a lower surface of a conductive pad (310, [0033]) is greater than an area of an upper surface of an active pattern (110, [0027]), in order to reduce contact resistance ([0056]).
Park and He are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of He because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park such that an area of a lower surface of the conductive pad is greater than an area of the upper surface of the active pattern, as taught by He, in order to reduce contact resistance (He, [0056]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al in US 2007/0152257 A1 (hereinafter Park) in view of Cho et al. in US 2004/0217407 A1 (hereinafter Cho).
Regarding claim 5, Park teaches the semiconductor device according to claim 3. Park does not explicitly state wherein the active pattern (52) includes an impurity region at an upper portion thereof, the impurity region contacting a lower surface of the conductive pad (57).
Cho teaches in FIG. 8D and related text, an active pattern (110, [0032]) includes an impurity region ([0043]) at an upper portion thereof, the impurity region contacting a lower surface of a conductive pad (450, [0043]), in order to reduce contact resistance ([0043]).
Park and Cho are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Cho because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park such that the active pattern includes an impurity region at an upper portion thereof, the impurity region contacting a lower surface of the conductive pad, as taught by Cho, in order to reduce contact resistance (Cho, [0043]).
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al in US 2007/0152257 A1 (hereinafter Park) in view of Lee et al. in US 2021/0098460 A1 (hereinafter Lee).
Regarding claim 6, Park teaches the semiconductor device according to claim 1. Park does not explicitly state wherein the lower spacer structure includes: a second lower spacer contacting the sidewall of the first contact plug structure and including silicon oxycarbide; and a first lower spacer contacting an outer sidewall of the second lower spacer and including silicon oxide.
Lee teaches in FIG. 12 and related text, wherein a lower spacer structure (151, [0107]) includes: a second lower spacer (151c, [0107]) contacting a sidewall of a first contact plug structure (140, [0107]) and including silicon oxycarbide ([0109]); and a first lower spacer (151b, [0107]) contacting an outer sidewall of the second lower spacer (151c) and including silicon oxide ([0109]), in order to reduce parasitic capacitance by providing a spacer structure having a low dielectric constant.
Park and Lee are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park such that the lower spacer structure includes: a second lower spacer contacting the sidewall of the first contact plug structure and including silicon oxycarbide; and a first lower spacer contacting an outer sidewall of the second lower spacer and including silicon oxide, as taught by Lee, in order to reduce parasitic capacitance by providing a spacer structure having a low dielectric constant.
Regarding claim 12, Park teaches the semiconductor device according to claim 11. Park further teaches wherein
the conductive pad structure (56) contacts each of opposite edge portions of the active pattern (52, see FIG. 4), and
the semiconductor device further comprises
a second contact plug structure (96, [0047]) on the conductive pad structure (56), and
a storage node (97, [0047]) on the first contact plug structure (56).
Park does not explicitly state that the storage node structure (97) is a capacitor.
Lee teaches in FIG. 12 and related text, a capacitor (190, [0089]) on a first contact plug structure (120, [0078]), in order to store information in a memory device ([0037]).
Park and Lee are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park in view of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park such the storage node is a capacitor, as taught by Lee, in order to store information in a memory device (Lee, [0037]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN LEE JOHNSON JR whose telephone number is (571)270-3217. The examiner can normally be reached Mon-Fri: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.L.J./Examiner, Art Unit 2811
/ORI NADAV/Primary Examiner, Art Unit 2811
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