CTNF 18/192,601 CTNF 72630 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim 1 is rejected under 35 U.S.C. 102( a)(1) and 102 (a)(2 ) as being anticipated by Wu et al (US 9419015) . With respect to Claim 1, Wu et al discloses an integrated circuit device (Figures 3A – 3B) comprising: a plurality of field effect transistors (FETs) ((309) formed on a substrate (101), wherein a first FET (309) of the plurality of first FETs comprises a first channel material (fin, 307) comprising a portion of the substrate (101) (see column 4, line 63-column 5, line 20 and Figures 3A-3B); and a plurality of second FETs formed on the substrate (101) , wherein a second FET of the plurality of second FETs comprises a second channel material (209, polysilicon layer) that is different than the first channel material (307, Si fin) , wherein the second channel material comprises a thin film transistor (TFT) channel material. See column 4, line 63-column 5, line 20 and Figures 3A-3B . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-22-aia AIA Claim s 2-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 9419015) as applied to claim 1 above, and further in view of Sachin Surve et al, Mobility and Threshold voltages comparison of zinc nitride based thin film transistor fabricated on Si and glass. Materials Research Express, 25 September 2020, Vol . 7, No. 9, pages 1-8 . Wu et al is relied upon as discussed above with respect to Claim 1. However, Wu et al do not disclose the material and properties of the TFT channel material as required by the Claims at hand. Sachin Surve et al discloses the use of zinc nitride as the TFT channel material, and its charge carrier mobility and threshold voltage. See Abstract and Figure 1 and Abstract of Sachin Surve et al. It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use zinc nitride in the device of Wu et al, for its known benefit in the art, as a TFT channel material. The use of a known compound, for its known benefit, would have been prima facie obvious to one of ordinary skill in the art. With respect to Claim 2, the combined references make obvious the limitation “wherein the TFT channel material has a charge carrier mobility within a range of 50 cm2/(Vs) to 700 cm2/Vs and a bandgap voltage within a range of 1.15 eV to 6.5 eV to 300 degrees Kelvin”. See Abstract and Figure 1 and Abstract of Sachin Surve et al. With respect to Claim 3, and the limitation “wherein the plurality of first FETs are separated by a first average pitch and the plurality of second FETs are separated by a second average pitch that is greater than the first average pitch”, the limitation would be obvious to one of ordinary skill in the art, as a rearrangement of parts. See In re Japikse, 86 USPQ 70 (CCPA 1950). With respect to Claim 4, and the limitation “ wherein the plurality of second FETs comprise gate dielectrics that are thicker than gate dielectrics of the plurality of first FETs and wherein the plurality of second FETs are adapted to operate at a higher voltage than the plurality of first FETs”, the limitation would be obvious to one of ordinary skill in the art, as changes in size in order to optimize the function are prima facie obvious. See In re Rose, 105 USPQ 237 (CCPA 1955). With respect to Claim 5, and the limitation “wherein the plurality of first FETs and the plurality of second FETs are FinFETs”, Wu et al discloses two separate FinFET zones. See the Abstract of Wu et al. With respect to Claim 6, and the limitation “wherein the plurality of first FETs and the plurality of second FETs are top-gated transistors, recessed gate transistors, or recessed spherical shaped transistors”, the Examiner takes Official Notice that the afore mentioned transistors and their use are well known in the art. With respect to Claim 7, Wu et al discloses further comprising a structural material on the substrate, wherein the second channel material of the second FET coats a portion of the structural material that is not in contact with the substrate. See Figures 3A – 3B and corresponding text. With respect to Claim 8, Wu et al discloses further comprising an integrated circuit die comprising the plurality of first FETs and the plurality of second FETs. See column 6, lines 1-20 of Wu et al. With respect to Claim 9, and the limitation “ further comprising a circuit board coupled to the integrated circuit die”, the Examiner takes Official Notice that circuit dies are well known in the art. With respect to Claim 10, Wu et al discloses comprising at least one of a network interface, battery, or memory coupled to the integrated die. See column 6, lines 1-20 of Wu et al. With respect to Claim 11, Claim 11 is rejected for the reasons as discussed in Claims 1 and 2. With respect to Claim 12, Claim 12 is rejected for the reasons as discussed in Claim 5. With respect to Claim 13, and the limitation “wherein the second FETs comprises nanowires or nanosheets comprising the second channel material”, the Examiner takes Official Notice that said components are well known in the art. With respect to Claim 14, and the limitation “wherein the second FETs comprise backgate FETs”, the Examiner takes Official Notice that said components are well known in the art. With respect to Claim 15, Wu et al discloses “wherein the second channel material forms a coating around at least a portion of a structural material” . See Figures 3A – 3B and corresponding text. With respect to Claim 16, Wu et al discloses wherein the first channel material comprises a portion of a silicon substrate. See Figures 3A – 3B and corresponding text. With respect to Claim 17, and the limitation “wherein the first FETs are on a front side of the integrated circuit device and the second FETs are on a back side of the integrated circuit device”, the limitation would be obvious to one of ordinary skill in the art, as a rearrangement of parts. See In re Japikse, 86 USPQ 70 (CCPA 1950). With respect to Claim 18, Claim 18 is rejected for the reasons as discussed with respect to Claim 11. With respect to Claim 19, Wu et al discloses wherein the first channel material is a substrate, wherein forming the plurality of second FETs comprises depositing the second channel material as the substrate. See Figures 3A- 3B and corresponding text. With respect to Claim 20, the combined references make obvious the TFT channel material comprises a zinc nitride film. See Abstract and Figure 1 and Abstract of Sachin Surve et al. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AGG April 14, 2026 /ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812 Application/Control Number: 18/192,601 Page 2 Art Unit: 2812 Application/Control Number: 18/192,601 Page 3 Art Unit: 2812 Application/Control Number: 18/192,601 Page 4 Art Unit: 2812 Application/Control Number: 18/192,601 Page 5 Art Unit: 2812 Application/Control Number: 18/192,601 Page 6 Art Unit: 2812 Application/Control Number: 18/192,601 Page 7 Art Unit: 2812 Application/Control Number: 18/192,601 Page 8 Art Unit: 2812
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