DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on September 28, 2022. It is noted, however, that applicant has not filed a certified copy of the KR 10-2022-0123452 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 30, 2023 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I (Figs. 1, 4, 16, 28, and 31B, claims 1-8 and 10-34) in the reply filed on December 16, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 recites the limitation "the second substrate" in lines: 8-9. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the substrate of the second substrate structure”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, 10-12, 16-19, 22, 25, and 30-33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Said (US 2021/0233881). Claim 1, Said discloses (Fig. 3A) a semiconductor device comprising: a first stacked (700, second semiconductor die, Para [0066]) structure that includes a first base body (708, second substrate, Para [0066]), a first connection pad (788B, second metallic fill portions of second bonding pads, Para [0070]) disposed over a surface of the first base body (788B is disposed over top surface of 708), and a first pad buffer layer (772, second metal-oxide framework MOF, Para [0079]) disposed adjacent to the first connection pad (772 is laterally adjacent to 788B), the first pad buffer layer including a first insulating material having a porous structure (772 is formed of MOFs which are porous, Para [0059]); a second stacked structure (900, first semiconductor die, Para [0052]) that includes a second base body (908, first substrate, Para [0040]), a second connection pad (988B, first metallic fill material portion of first bonding pad, Para [0052]) disposed over a surface of the second base body (988B is disposed over a bottom surface of 908), and a second pad buffer layer (972, first metal-organic framework MOF dielectric layer, Para [0062]) disposed adjacent to the second connection pad (972 is laterally adjacent to 988B), the second pad buffer layer including a second insulating material having a porous structure (972 is formed of MOFs which are porous, Para [0059]); and a connection portion (region of 991/791, first/second SAM layer, Para [0073], hereinafter “connect”) of the first and second stacked structures (connect is of both 700 and 900) that connects the first and second connection pads with each other (connect physically connects 788B to 988B). Claim 2, Said discloses (Fig. 3A) the semiconductor device of claim 1, wherein the first (772) and second insulating materials (972) having the porous structure comprise a metal-organic framework (both 772 and 972 at MOFs). Claim 3, Said discloses (Fig. 3A) the semiconductor device of claim 2, wherein the metal- organic framework has a two-dimensional structure including cavities (MOFs have cavities forming a dimension larger than monoatomic, Para [0059]), and wherein each of the first and second pad buffer layers comprises at least one layer of the metal-organic framework (772 and 972 are MOFs, Para [0062, [0079]). Claim 4, Said discloses (Fig. 3A) the semiconductor device of claim 1, further comprising: a first pad barrier layer (788A, second metallic liner, Para [0070]) disposed between the first connection pad and the first pad buffer layer (788A is between 788B and 772), the first pad barrier layer including a two-dimensional material (778A is shown as two-dimensional in Fig. 3A); and a second pad barrier layer (988A, first metallic liner, Para [0050]) disposed between the second connection pad and the second pad buffer layer (988A is between 988B and 972), the second pad barrier layer including a two-dimensional material (988A is shown as two-dimensional in Fig. 3A).
Claim 8, Said discloses (Fig. 3A) the semiconductor device of claim 1, wherein in the connection portion (connect), a surface area of the first connection pad (788B) is substantially the same as a surface area of the second connection pad (in connect the surface are of 788B is substantially the same as surface area of 988B). Claim 10, Said discloses (Fig. 3A) the semiconductor device of claim 1, wherein the first stacked structure (700) further includes a first bonding dielectric layer (771, second pad-level dielectric layer, Para [0069]) disposed adjacent to the first connection pad in a lateral direction (771 is disposed adjacent to 788B in lateral direction), wherein the second stacked structure (900) further includes a second bonding dielectric layer (971, first pad-level dielectric layer, Para [0083]) disposed adjacent to the second connection pad in a lateral direction (971 is disposed adjacent to 988B in lateral direction), and wherein the connection portion (connect) further includes bonding of the first bonding dielectric layer and the second bonding dielectric layer (under BRI 771 is bonded to 971 through 791/991 of connect). Claim 11, Said discloses (Fig. 3A) the semiconductor device of claim 1, wherein the connection portion (connect) further includes bonding of the first and second pad buffer layers (under BRI 772 is bonded to 972 through 791/991 of connect). Claim 12, Said discloses (Fig. 3A) the semiconductor device of claim 1, wherein the first pad buffer layer (772) is disposed to surround the first connection pad (788B) over the surface of the first base body (772 surrounds 788B over 708), and wherein the second pad buffer layer (972) is disposed to surround the second connection pad (988B) over the surface of the second base body (972 surrounds 988B over 908). Claim 16, Said discloses (Fig. 3A) a semiconductor device comprising: a first substrate structure (700, second semiconductor die, Para [0066]) that includes a substrate (708, second substrate, Para [0066]), a memory cell driver circuit (720, second semiconductor devices may include drive circuit, Para [0067]) disposed over the substrate (720 is disposed over 708), a first connection pad (788B, second metallic fill portions of second bonding pads, Para [0070]) disposed over the substrate (788B is disposed over 708) to be electrically connected to the memory cell driver circuit (788B is electrically connected to 720 through 780, Para [0068]), and a first pad buffer layer (772, second metal-oxide framework MOF, Para [0079]) disposed in a lateral direction of the first connection pad (772 is disposed in a lateral direction 788B), the first pad buffer layer including a first insulating material having a porous structure (772 is formed of MOFs which are porous, Para [0059]); a second substrate structure (900, first semiconductor die, Para [0052]) that includes a substrate (908, first substrate, Para [0040]), a memory cell structure (920, first semiconductor devices may include NAND memory device, Para [0042]) disposed over the substrate (920 is disposed over the bottom surface of 908), a second connection pad (988B, first metallic fill material portion of first bonding pad, Para [0052]) disposed over the substrate (988B is disposed over bottom surface of 908) to be electrically connected to the memory cell structure (988B is connected to 920 through 980, Para [0040]), and a second pad buffer layer (972, first metal-organic framework MOF dielectric layer, Para [0062]) disposed in a lateral direction of the second connection pad (972 is disposed in a lateral direction 988B), the second pad buffer layer including a second insulating material having a porous structure (972 is formed of MOFs which are porous, Para [0059]); and a connection portion (region of 991/791, first/second SAM layer, Para [0073], hereinafter “connect”) of the first and second substrate structures (connect is of both 700 and 900), that connects the first and second connection pads (connect physically connects 788B to 988B). Claim 17, Said discloses (Fig. 3A) The semiconductor device of claim 16, wherein the first (772) and second insulating materials (972) having the porous structure comprise a metal-organic framework (both 772 and 972 at MOFs). Claim 18, Said discloses (Fig. 3A) the semiconductor device of claim 17, wherein the metal- organic framework of each of the first (972) and second pad buffer layers (772) has a two-dimensional structure including cavities (MOFs have cavities forming a dimension larger than monoatomic, Para [0059]), and wherein each of the first and second pad buffer layers comprises at least one layer of the metal-organic framework (772 and 972 are MOFs, Para [0062, [0079]).
Claim 19, Said discloses (Fig. 3A) the semiconductor device of claim 16, further comprising at least one of a first pad barrier layer (788A, second metallic liner, Para [0070]) disposed between the first connection pad and the first pad buffer layer (788A is between 788B and 772), the first pad barrier layer including a two-dimensional material (778A is shown as two-dimensional in Fig. 3A); and a second pad barrier layer (988A, first metallic liner, Para [0050]) disposed between the second connection pad and the second pad buffer layer (988A is between 988B and 972), the second pad barrier layer including a two-dimensional material (988A is shown as two-dimensional in Fig. 3A).
Claim 22, Said discloses (Fig. 3A) the semiconductor device of claim 16, wherein the first substrate structure (700) further includes a first bonding dielectric layer (771, second pad-level dielectric layer, Para [0069]) disposed adjacent to the first connection pad in a lateral direction (771 is disposed adjacent to 788B in lateral direction), wherein the second substrate structure (900) further includes a second bonding dielectric layer (971, first pad-level dielectric layer, Para [0083]) disposed adjacent to the second connection pad in a lateral direction (971 is disposed adjacent to 988B in lateral direction), and wherein the connection portion (connect) further includes bonding of the first bonding dielectric layer and the second bonding dielectric layer (under BRI 771 is bonded to 971 through 791/991 of connect).
Claim 25, Said discloses (Figs 1A-2E and Fig. 3A) a method of fabricating a semiconductor device, the method comprising: forming (Fig. 2A) a first substrate structure (700, second semiconductor die, Para [0066]) that includes a substrate (708, second substrate, Para [0066]), a first connection pad (788B, second metallic fill material of second bonding pads 788, Para [0070]) disposed over a surface of the first substrate (788B is disposed over a top surface of 708), and a first pad buffer layer (Fig. 2E, 772, second metal-oxide framework, Para [0079]) disposed adjacent to the first connection pad (772 is disposed adjacent to 788B), the first pad buffer layer including a metal-organic framework (772 can be metal-organic framework, Para [0080]); forming a second substrate structure (Fig. 1A, 900, first semiconductor die, Para [0040]) that includes a substrate (908, first substrate, Para [0040]), a second connection pad (Fig. 1D, 988B, first metallic material portion of first bonding pad, Para [0051]) disposed over a surface of the substrate of the second substrate structure (988B is disposed over a top surface of 908) , and a second pad buffer layer (Fig. 1H, 972, metal organic framework, Para [0062]) disposed adjacent to the second connection pad (972 is disposed adjacent to 988B), the second pad buffer layer including a metal- organic framework (972 is MOF, Para [0062]); and bonding (Fig. 3A) the first and second substrate structures to each other (700 and 900 bonded in Fig. 3A) to form a connection portion (region of 991/791, first/second SAM layer, Para [0073], hereinafter “connect”) of the first and second connection pads (connect physically connects 788B to 988B).
Claim 30, Said discloses (Figs 1A-2E and Fig. 3A) the method of claim 25, wherein forming (Fig. 2C) the first substrate structure (700) further includes forming a first bonding dielectric layer (771, second dielectric material layers, Para [0066]) disposed adjacent to the first connection pad in a lateral direction (771 is disposed adjacent to 788B), wherein forming (Fig. 1F) the second substrate structure (900) further includes forming a second bonding dielectric layer (971, first dielectric material layer, Para [0040]) disposed adjacent to the second connection pad in a lateral direction (971 is adjacent 988B in lateral direction), and wherein bonding the first (700) and second substrate structures (900) to each other includes bonding the first and second connection pads to each other (788B and 988B are bonded to each other through 991/791) and bonding the first and second bonding dielectric layers to each other (771 and 971 are bonded to each other through 991/791).
Claim 31, Said discloses (Fig. 3A) a semiconductor device comprising: a first substrate structure (700, second semiconductor die, Para [0066]) that includes a first connection pad (788B, second metallic fill portions of second bonding pads, Para [0070]) and a first pad buffer layer (772, second metal-oxide framework MOF, Para [0079]) disposed to surround at least a sidewall of the first connection pad (772 surrounds at least a sidewall of 788B); and a second substrate structure (900, first semiconductor die, Para [0052]) that includes a second connection pad (988B, first metallic fill material portion of first bonding pad, Para [0052]) and a second pad buffer layer (972, first metal-organic framework MOF dielectric layer, Para [0062]) disposed to surround at least a sidewall of the second connection pad (972 surrounds at least a sidewall of 988B), wherein the first and second substrate structures are physically and electrically bonded to each (700 and 900 are physically and electrically bonded to each other) other using the first and second connection pads (998B and 788B are bonded through SAM layers 991/791, Para [0073]), and wherein the first and second pad buffer layers include an insulating material having a porous structure (772 and 972 are MOFs which are porous, Para [0059]). Claim 32, Said discloses (Fig. 3A) the semiconductor device of claim 31, wherein the insulating material (MOFs) having the porous structure comprises a metal- organic framework (MOFs are metal-organic framework which are porous, Para [0059]). Claim 33, Said discloses (Fig. 3A) the semiconductor device of claim 32, wherein the first substrate structure (700) further includes a first pad barrier layer (788A, second metallic liner, Para [0070]) disposed between the first connection pad and the first pad buffer layer (788A is between 788B and 772), the first pad barrier layer including a two-dimensional material (778A is shown as two-dimensional in Fig. 3A), and wherein the second substrate structure (900) further includes a second pad barrier layer (988A, first metallic liner, Para [0050]) disposed between the second connection pad and the second pad buffer layer (988A is between 988B and 972), the second pad barrier layer including a two-dimensional material (988A is shown as two-dimensional in Fig. 3A).
Allowable Subject Matter
Claims 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejection above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Said (US 2021/0233881), Karda (US 2021/0057424), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 26 (from which claim 27 depends), forming a via barrier layer disposed between the via and the base buffer layer and including MXene…
Regarding Claim 28, forming a via barrier layer disposed between the via and the base buffer layer and including MXene…
Regarding Claim 29, forming a via barrier layer disposed between the via and the base buffer layer and including MXene…
Claims 5-7, 13-15, 20-21, 23-24, and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Said (US 2021/0233881), Karda (US 2021/0057424), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 5 (from which claims 6-7 depend), wherein the two- dimensional material of each of the first and second pad barrier layers comprises MXene.
Regarding Claim 13, a via barrier layer disposed between the via and the base buffer layer in a lateral direction and the via barrier layer including a two- dimensional material.
Regarding Claim 14, a via barrier layer disposed between the via and the base buffer layer in a lateral direction and the via barrier layer including a two- dimensional material.
Regarding Claim 15, a via barrier layer disposed between the second base body and the through via in a lateral direction and the via barrier layer including a two-dimensional material.
Regarding Claim 20 (from which claim 21 depends), wherein the two- dimensional material of each of the first and second pad barrier layers comprises MXene.
Regarding Claim 23, a via barrier layer disposed between the via and the base buffer layer in a lateral direction and the via barrier layer including a two- dimensional material.
Regarding Claim 24, a via barrier layer disposed between the via and the base buffer layer in a lateral direction and the via barrier layer including a two- dimensional material.
Regarding Claim 34, wherein the two- dimensional material comprises MXene.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Karda (US 2021/0057424) discloses (Fig. 2B) 2D materials 106 comprising Mxene formula (Para [0034]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/G.G.R/Examiner, Art Unit 2812