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Office Actions › International Business Machines Corporation › 18192839
Last updated: July 17, 2026
Application No. 18/192,839

LOCATION AWARE TIMING ANALYSIS OF A DIGITAL INTEGRATED CIRCUIT

Non-Final OA
Filed
Mar 30, 2023
Examiner
PARIHAR, SUCHIN
Art Unit
Tech Center
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Interview Optional

— +8.9% interview lift. Interview lift (+8.9%) is below the 15.0% threshold. A written response is recommended.
Based on 1167 resolved cases, 2023–2026

Examiner Intelligence

PARIHAR, SUCHIN View full profile →
Grants 88% — above average
88%
Career Allowance Rate
1024 granted / 1167 resolved
+27.7% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
12 currently pending
Career history
1181
Total Applications
across all art units

Statute-Specific Performance

§101
3.2%
-36.8% vs TC avg
§103
21.3%
-18.7% vs TC avg
§102
70.9%
+30.9% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1167 resolved cases

Prosecution Timeline

Mar 30, 2023
Application Filed
Jun 13, 2024
Response after Non-Final Action
May 06, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

18/011,168
Patent 12683411
METHODS AND SYSTEMS FOR CHARGING FOR DEVICE IDENTIFICATION, ADDITION AND/OR CHANGE
3y 7m to grant Granted Jul 14, 2026
18/126,164
Patent 12682143
IDENTIFYING RTL CODE THAT CAN BE A SOURCE OF VERIFICATION COMPLEXITY FOR DOWNSTREAM EQUIVALENCE CHECKERS AND GENERATING RECOMMENDATIONS TO IMPROVE RUNTIME OF EQUIVALENCE CHECKERS
3y 3m to grant Granted Jul 14, 2026
18/076,968
Patent 12675623
TIMING OPTIMIZATION METHOD AND APPARATUS BASED ON OUTPUT TRANSITION CONSTRAINTS, AND COMPUTER DEVICE
3y 7m to grant Granted Jul 07, 2026
17/886,670
Patent 12662008
Electric Vehicle Charging System
3y 10m to grant Granted Jun 23, 2026
18/076,007
Patent 12645856
CREATION OF REDUCED FORMAL MODEL FOR SCALABLE SYSTEM-ON-CHIP (SOC) LEVEL CONNECTIVITY VERIFICATION
3y 5m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1167 resolved cases by this examiner. Grant probability derived from career allowance rate.

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Data sourced from USPTO Patent File Wrapper (daily) and Office Action Archive (weekly). Analysis generated by IP Author.

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