Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
In response to election/restriction, applicant elected claims 1-21 without traverse.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7, 9-13, 18, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Aharoni et al. (US 2010/0249976, hereinafter Aharoni) in view of David (US 2017/0109646, hereinafter David).
With respect to claim 1, Aharoni discloses a method of fabricating an integrated circuit (IC) (Para 0005; 0028), the method comprising:
processing a plurality of semiconductor wafers in a fabrication flow (Para 0009 & 0055) having a sequence of process steps including a targeted process step (Para 0055), wherein the targeted process step comprises an operation performed at a process tool using a first process recipe with respect to a material layer over the semiconductor wafers (Para 0011-0015; generating at least one heat map having rows that correspond to sensors implemented in said machine tool, columns that correspond to recipe steps representing a process used to fabricate said microelectronic devices and cells at the intersection of said rows and said columns; assigning each row of said heat map to a sensor; assigning each column of said heat map to a recipe step; using at least one sensor for obtaining trace data of a recipe step while manufacturing at least one microelectronic device); obtaining a measurement of a response metric variable for the semiconductor wafers (Para 0004; 0029, 0059 – set of measurements made over time by any one sensor enabled for a particular process, temp, pressure, etc.) the response metric variable relating to a parameter associated with the semiconductor wafers (Para 0065; 0073; and 0078); obtaining a first average of the response metric variable from a first subset of the plurality of semiconductor wafers (Para 0066; 0076; average time series includes multiple averages); obtaining a second average of the response metric variable from a second subset of the plurality of semiconductor wafers (Para 0091; 0114; and 0134; average trace data includes multiple averages); on the condition that a difference between the first and second averages is
statistically significant (Para 0064-0065; and 0067; difference between the two time periods – current and past data – which implies current and past averages), adjusting one or more process parameters of the targeted process step (Para 0109 -0110; 0124-0125; adjusting process parameters).
Aharoni does not explicitly disclose processing a subsequent semiconductor wafer at the targeted process step containing the IC at an intermediate stage of formation, wherein the subsequent semiconductor wafer is of a same technology node as the plurality of semiconductor wafers.
In an analogous art, David discloses processing a subsequent semiconductor wafer at the targeted process step containing the IC at an intermediate stage of formation, wherein the subsequent semiconductor wafer is of a same technology node as the plurality of semiconductor wafers (Para 0088; 0124 and 0128; other wafers (subsequent wafers) share similar processing conditions).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni’s method by having David’s disclosure in order to reduce failures in wafer processing by timely detecting and addressing the abnormalities.
With respect to claim 12, Aharoni discloses a method of fabricating an integrated circuit (IC) (Para 0005; 0028), the method comprising:
determining yield data, on a wafer-by-wafer basis (Para 0074; yield rate for each wafer), for a plurality of wafer lots processed through a fabrication flow (Para 0009 and 0055) having a sequence of process steps including a targeted process step (Para 0055), wherein the targeted process step comprises an operation performed at a process tool using a first process recipe with respect to a material layer over a plurality of semiconductor wafers in a wafer lot (Para 0011-0015; generating at least one heat map having rows that correspond to sensors implemented in said machine tool, columns that correspond to recipe steps representing a process used to fabricate said microelectronic devices and cells at the intersection of said rows and said columns; assigning each row of said heat map to a sensor; assigning each column of said heat map to a recipe step; using at least one sensor for obtaining trace data of a recipe step while manufacturing at least one microelectronic device); obtaining a first average of a yield variable from a first subset of each respective wafer lot (Para 0057; 0066; 0069; 0076; average time series includes multiple averages); obtaining a second average of the yield variable from a second subset of each respective wafer lot (Para 0057; 0066; 0069; 0091; 0114; and 0134; average trace data includes multiple averages); on the condition that a difference between the first and second averages is statistically significant (Para 0064-0065; and 0067; difference between the two time periods – current and past data – which implies current and past averages), adjusting one or more process parameters of the targeted process step (Para 0109 -0110; 0124-0125; adjusting process parameters).
Aharoni does not explicitly disclose processing a subsequent wafer lot including a semiconductor wafer at the targeted process step containing the IC at an intermediate stage of formation, wherein the subsequent wafer lot containing the semiconductor wafer is of a same technology node as the plurality of wafer lots immediately preceding the subsequent wafer lot.
In an analogous art, David discloses processing a subsequent wafer lot including a semiconductor wafer at the targeted process step containing the IC at an intermediate stage of formation, wherein the subsequent wafer lot containing the semiconductor wafer is of a same technology node as the plurality of wafer lots immediately preceding the subsequent wafer lot (Para 0088; 0124 and 0128; other wafers (subsequent wafers) share similar processing conditions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni’s method by having David’s disclosure in order to reduce failures in wafer processing by timely detecting and addressing the abnormalities.
With respect to claims 2 and 13, Ahorni discloses wherein the first subset and the second subset are non-intersecting subsets (Para 0064; data collected at two different time periods are non-intersection subsets).
With respect to claims 7 and 18, Ahorni discloses wherein the transitional condition comprises a process recipe transition relative to changing a process recipe to the first process recipe for processing the targeted process step (Para 0109 and 0124).
With respect to claims 9 and 20, Ahorni discloses wherein the transitional condition comprises a technology node transition relative to changing from one technology node to another technology node at the process tool for processing the plurality of semiconductor wafers at the targeted processing step (Para 0109; 0122-0124 – changes in processing conditions and recipes).
With respect to claims 10 and 21, Aharoni does not explicitly disclose wherein the transitional condition comprises a state transition relative to the process tool deployed to perform the targeted process step.
In an analogous art, David discloses wherein the transitional condition comprises a state transition relative to the process tool deployed to perform the targeted process step (Para 0066; 0107; and 0122). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni’s method by having David’s disclosure in order to improve the processing conditions by managing critical parameters.
With respect to claim 11, Aharoni discloses wherein the response metric variable comprises a yield variable, a quality parametric variable, a critical dimension (CD) variable, an overlay alignment variable, a layer thickness variable, a layer planarization variable, an etch profile variable, a defect count variable, and an electrical parametric variable (Para 0069; and 0131-0132; yield, quality, etc.).
Claims 3-6 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Aharoni/David in view of Toshima (US 5,944,940, hereinafter Toshima).
With respect to claims 3 and 14, Aharoni/David does not explicitly disclose that the first subset comprises semiconductor wafers from a first portion of a slot order sequence of the plurality of semiconductor wafers, the slot order sequence identifying a run sequence of loading of the plurality of the semiconductor wafers in the process tool; and the second subset comprises semiconductor wafers from a second portion of the slot order sequence of the plurality of semiconductor wafers, wherein the first and second portions are at respective opposite ends of the run sequence.
In analogous art, Toshima discloses that the first subset comprises semiconductor wafers from a first portion of a slot order sequence of the plurality of semiconductor wafers (Col. 8; lines 13-26; cassette stage 28a to hold the wafers), the slot order sequence identifying a run sequence of loading of the plurality of the semiconductor wafers in the process tool (Col. 14; lines 20-25; lines 61-65; Col. 2; lines 1-34); and the second subset comprises semiconductor wafers from a second portion of the slot order sequence of the plurality of semiconductor wafers (Col. 8; lines 13-26; cassette stages 28b to hold the wafers) wherein the first and second portions are at respective opposite ends of the run sequence (Col. 8; lines 13-26; wafers in the beginning of 28a are first portions and wafers in the last slots of 28b are second portions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni/David’s method by having Toshima’s disclosure in order to improve the throughput of a semiconductor manufacturing process.
With respect to claims 4 and 15, Aharoni/David does not explicitly disclose wherein the first portion of the slot order sequence comprises first five slots of a wafer lot comprising the plurality of semiconductor wafers.
In an analogous art, Toshima discloses wherein the first portion of the slot order sequence comprises first five slots of a wafer lot comprising the plurality of semiconductor wafers (Col. 5; lines 54- 65; Col. 8; lines 15-20; it can be first five slots of 28a). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni/David’s method by having Toshima’s disclosure in order to improve the throughput of a semiconductor manufacturing process.
With respect to claims 5 and 16, Aharoni/David/Toshima discloses the method as recited in claim 3.
Aharoni/David does not explicitly disclose wherein the second portion of the slot
order sequence comprises last five slots of a wafer lot comprising the plurality of
semiconductor wafers.
In an analogous art, Toshima discloses wherein the second portion of the slot order sequence comprises last five slots of a wafer lot comprising the plurality of semiconductor wafers (Col. 5; lines 54- 65; Col. 8; lines 15-20; it can be last five slots of 28b). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni/David’s method by having Toshima’s disclosure in order to improve the throughput of a semiconductor manufacturing process.
With respect to claims 6 and 17, Aharoni/David discloses the method as recited in claim 1.
Aharoni/David does not explicitly disclose wherein the first and second subsets
are of different size.
In an analogous art, Toshima discloses wherein the first and second subsets
are of different size (Col. 5; lines 44- 65; five or six wafers). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni/David’s method by having Toshima’s disclosure in order to improve the throughput of a semiconductor manufacturing process.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Aharoni/David in view of Ayyagari et al. (US 2022/0004689, hereinafter Ayyagari).
With respect to claims 8 and 19, Aharoni/David does not explicitly disclose
wherein the transitional condition comprises a product design transition relative to changing from one IC design to another IC design at the process tool for processing the plurality of semiconductor wafers at the targeted processing step.
In an analogous art, Ayyagari discloses wherein the transitional condition comprises a product design transition relative to changing from one IC design to another IC design at the process tool for processing the plurality of semiconductor wafers at the targeted processing step (Para 0022; 0034; and 0039). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Aharoni/David’s method by having Ayyagari’s disclosure in order to achieve the optimal performance by adjusting the product design according to processing demands.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899