Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 5-14 are rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0098140 A1) in view of Shih (US 2018/0102311 A1) and Wang et al. (US 2016/0293576 A1).
Regarding independent claim 1: Bartley teaches (e.g., Figs. 1-4) a semiconductor structure, comprising:
a first horizontally-fabricated semiconductor die section ([0033]-[0034]: bottommost horizontally-fabricated semiconductor die section 12 on the left-side, including functional unit 14) having a major surface; and
a vertical interconnect (VI) ([0031]-[0034] and [0044]: 16) perpendicularly oriented to the major surface (as shown in Fig. 1), comprising:
vertical conductive interconnect lines ([0033]-[0035] and [0043]) electrically connecting components above ([0033]-[0034]: chip 12 including functional unit 14 in layers 2 up to layer N) and below the VI die ([0033]-[0034]: chip 12 in layer 1).
Barley does not expressly teach
a vertical interconnect (VI) die embedded in the first horizontally-fabricated semiconductor die section, and
metal interconnect lines disposed within the dielectric insulating layer, the vertical metal interconnect lines; and
a VI substrate having a substrate surface extending perpendicular to the major surface.
Shih teaches (e.g., Figs. 1-14) a semiconductor structure comprising an interconnect (VI) die ([0029] and [0056]: 101/100); and
metal interconnect lines ([0023]-[0024], [0027] and [0040]: 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley, the interconnect (VI) die and metal interconnect lines, as taught by Shih, for the benefits of increasing signal speeds of the integrated circuit during operation, since metals are well-known to be very good electrical conductors.
Wang teaches (e.g., Figs. 1-7) a semiconductor structure comprising
a vertical interconnect (VI) die ([0023]-[0026]: 122/120) embedded in a first horizontally-fabricated semiconductor die section ([0018], [0025]-[0028]: region between horizontally-fabricated die 132a and 132b), and
metal interconnect lines ([0023]-[0026]: 120) disposed within a dielectric insulating layer ([0033]: 106b), the vertical metal interconnect lines (120); and
a VI substrate ([0023]-[0026]: 122) having a substrate surface extending perpendicular to the major surface (substrate 122 extends vertically perpendicular the horizontal surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Barley as modified by Shih, the vertical interconnect (VI) die embedded in the first horizontally-fabricated semiconductor die section, and metal interconnect lines disposed within the dielectric insulating layer, the vertical metal interconnect lines; and the VI substrate having a substrate surface extending perpendicular to the major surface, as taught by Wang, for the benefits of strengthening the semiconductor device package by using the interconnect substrate as a support structure; thus, increasing device package reliability.
Regarding claim 3: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
wherein the VI die comprises selection from the group consisting of:
active devices and connecting lines connecting at least two of the vertical metal lines (Shih: [0056]: 101).
Regarding claim 5: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Bartley as modified by Shih teaches that the semiconductor structure further comprising
a second horizontally-fabricated semiconductor die section (Bartley: Figs. 1-2; [0033]-[0034]: right side horizontally-fabricated semiconductor die section opposite portion of first horizontally-fabricated semiconductor die 12 on the left side),
wherein the VI die is embedded in a trench ([0043]: VI die 16 is embedded in a trench) between the first horizontally-fabricated semiconductor die section and the second horizontally-fabricated semiconductor die section (Bartley: Figs. 1-2; [0033]-[0034]: left side region and right-side region respectively).
Regarding claim 6: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Bartley as modified by Shih teaches that the vertical metal interconnect lines comprise a feature selected from the group consisting of: non-rectilinear lines, airgaps between the vertical metal interconnect lines, low-k dielectric between the vertical metal interconnect lines, capping layers for vertical metal interconnect lines, nonconformal and nonsymmetric features, and back-end-of-line features (Shih: [0046]-[0047]: 210/900).
Regarding claim 7: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends,
Bartley as modified by Shih and Wang teaches that the semiconductor structure further comprises a second level comprising:
a first second-level horizontally-fabricated semiconductor die section (Bartley: Fig. 4, [0042]: second chip from bottommost chip); and
a second VI die (Bartley: Fig. 4, [0043]-[0044]: second VI die 48 from bottommost VI die) embedded adjacent to the first second-level horizontally-fabricated semiconductor die section (Bartley: Fig. 4; [0042]-[0044]).
Regarding claim 8: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Bartley as modified by Shih teaches that semiconductor structure further comprises
a second-level horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: semiconductor die section 12 with functional unit 14) attached vertically above the first horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: bottommost semiconductor die section 12 with functional unit 14),
wherein the VI die is embedded adjacent to the first horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: bottommost semiconductor die section 12 with functional unit 14) and the second-level horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: second semiconductor die section 12 with functional unit 14 from bottommost semiconductor die section 12 with functional unit 14).
Regarding claim 9: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 8, on which this claim depends, further comprising
a top horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: third semiconductor die section 12 with functional unit 14 from bottommost semiconductor die section 12 with functional unit 14) over the VI die (Bartley: [0033], [0036] and [0044]) and the second-level horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: second semiconductor die section 12 with functional unit 14 from bottommost semiconductor die section 12 with functional unit 14).
Regarding claim 10: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Bartley as modified by Shih teaches that the VI die (Bartley: [0031]-[0034] and [0043]-[0044]: 16) is embedded in a hole (Bartley: [0031]-[0034] and [0043]-[0044]: 16) in the first horizontally-fabricated semiconductor die section (Bartley: [0031]-[0034] and [0044]: 16).
Regarding independent claim 11: Bartley teaches (e.g., Figs. 1-4) a semiconductor structure, comprising
a first vertical interconnect (VI) die ([0031]-[0034] and [0043]-[0044]: 16) comprising vertical conductive interconnect lines ([0033]-[0035]);
a top connection layer ([0038]-[0040]: 22/50 above third component layer from the bottommost component) electrically connecting the VI die to top components ([0033]-[0034]: components 12 including functional unit 14) above the VI die; and
a bottom connection layer ([0038]-[0040]: 22/50 below second component layer from the bottommost component) electrically connecting the VI die to bottom components ([0033]-[0034]: components 12 including functional unit 14) below the VI die.
Barley does not expressly teach a first interconnect (VI) die embedded in horizontally-fabricated die section,
comprising vertical metal interconnect lines disposed within a dielectric insulating layer on a VI substrate.
Barley does not expressly teach
a vertical interconnect (VI) die embedded in the first horizontally-fabricated semiconductor die section, and
metal interconnect lines disposed within the dielectric insulating layer, the vertical metal interconnect lines; and
a VI substrate having a substrate surface extending perpendicular to the major surface.
Shih teaches (e.g., Figs. 1-14) a semiconductor structure comprising
([0029] and [0056]: 101: 101); and metal interconnect lines ([0023]-[0024] and [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley, the interconnect (VI) die and the metal interconnect lines, as taught by Shih, for the benefits of increasing signal speeds of the integrated circuit during operation, since metals are well-known to be very good electrical conductors.
Wang teaches (e.g., Figs. 1-7) a semiconductor structure comprising
a first vertical interconnect (VI) die ([0023]-[0026]: 122/120) embedded in a first horizontally-fabricated semiconductor die section ([0018], [0025]-[0028]: die section region between horizontally-fabricated die 132a and 132b),
comprising vertical metal interconnect lines ([0023]-[0026]: 120) disposed within a dielectric insulating layer ([0033]: 106b), the vertical metal interconnect lines (120); on a VI substrate ([0023]-[0026]: 122)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Barley as modified by Shih, a first interconnect (VI) die embedded in horizontally-fabricated die section, comprising vertical metal interconnect lines disposed within a dielectric insulating layer on a VI substrate, as taught by Wang, for the benefits of strengthening the semiconductor device package by using the interconnect substrate as a support structure; thus, increasing device package reliability.
Regarding claim 12: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 11, on which this claim depends, further comprising
a horizontally-fabricated semiconductor die section (Bartley: [0033]-[0034]: bottommost horizontally-fabricated semiconductor die section 12 including functional unit 14) adjacent to the first VI die and between the top connection layer and the bottom connection layer (Bartley: [0038]-[0040]: 22/50).
Regarding claim 13: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 11, on which this claim depends. further comprising
Barley as modified by Shih teaches a second VI die (Bartley: Fig. 4, [0043]-[0044]: second VI die 48 from bottommost VI die) above the top connection layer.
Regarding claim 14: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 13, on which this claim depends.
further comprising a horizontally-fabricated semiconductor die section (Bartley: [0033], [0036] and [0044]: semiconductor die section 12 with functional unit 14 in second level from the first horizontally-fabricated semiconductor die section) adjacent to the second VI die.
Claims 2 and 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0098140 A1) in view of Shih (US 2018/0102311 A1) and Wang et al. (US 2016/0293576 A1) as applied above and further in view of Barowski et al. (US 2016/0070842 A1).
Regarding claim 2: Bartley and Shih teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Barley as modified by Shih does not expressly teach that the first horizontally-fabricated semiconductor die section comprises an active front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) system.
Barowski teaches (e.g., Fig. 1) a semiconductor structure comprising
a first horizontally-fabricated semiconductor die section ([0035]: 118) comprising an active front-end-of-line (FEOL) layer ([0026] and [0041]: FEOL) and a back-end-of-line (BEOL) system ([0035]-[0036]: BEOL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley as modified by Shih, the first horizontally-fabricated semiconductor die section comprising an active front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) system, as taught by Barowski, for the benefits of processing and transferring information to integrated circuit memory devices for storage and thus improving device function efficiency.
Regarding independent claim 15: Bartley teaches (e.g., Figs. 1-4) a semiconductor structure, comprising:
a first horizontally-fabricated semiconductor die section ([0033]-[0034]: bottommost horizontally-fabricated semiconductor die section 12 including functional unit 14) comprising
a vertical interconnect (VI) ([0031]-[0034] and [0044]: 16) comprising: a substrate oriented vertically relative to the major surface; and
interconnect lines ([0031]-[0034] and [0044]: 16) within the substrate oriented vertically (interconnect lines 16 are oriented vertically) relative to the major surface (horizontal surface).
Bartley does not expressly teach that
an active front-end-of-line (FEOL) layer on a major surface and a back-end-of-line (BEOL) system;
interconnect (VI) die, and
metal interconnect lines.
Barley does not expressly teach
a vertical interconnect (VI) die embedded in the first horizontally-fabricated semiconductor die section, and
a dielectric insulating layer on the substrate; and
metal interconnect lines disposed within the dielectric insulating layer, the vertical metal interconnect lines.
Shih teaches (e.g., Figs. 1-14) a semiconductor structure comprising an interconnect (VI) die ([0029] and [0056]: 101: 101); and
metal interconnect lines ([0023]-[0024] and [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley, the interconnect (VI) die and metal interconnect lines, as taught by Shih, for the benefits of increasing signal speeds of the integrated circuit during operation, since metals are well-known to be very good electrical conductors.
Barowski teaches (e.g., Fig. 1) a semiconductor structure comprising
a first horizontally-fabricated semiconductor die section ([0035]: 118) comprising an active front-end-of-line (FEOL) layer ([0026] and [0041]: FEOL) and a back-end-of-line (BEOL) system ([0035]-[0036]: BEOL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley as modified by Shih, the first horizontally-fabricated semiconductor die section comprising an active front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) system, as taught by Barowski, for the benefits of processing and transferring information to integrated circuit memory devices for storage and thus improving device function efficiency.
Wang teaches (e.g., Figs. 1-7) a semiconductor structure comprising
a vertical interconnect (VI) die ([0023]-[0026]: 122/120) embedded in a first horizontally-fabricated semiconductor die section ([0018], [0025]-[0028]: region between horizontally-fabricated die 132a and 132b), comprising
a dielectric insulating layer ([0033]: 106b) on a substrate ([0023]-[0026]: 122) oriented perpendicular to the major surface (upper surface of substrate 122); and
metal interconnect lines ([0023]-[0026]: 120) disposed within the dielectric insulating layer ([0033]: 106b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Barley as modified by Shih and Barowski, the vertical interconnect (VI) die embedded in the first horizontally-fabricated semiconductor die section, and a dielectric insulating layer on the substrate; metal interconnect lines disposed within the dielectric insulating layer, the vertical metal interconnect lines, as taught by Wang, for the benefits of strengthening the semiconductor device package by using the interconnect substrate as a support structure; thus, increasing device package reliability.
Regarding claim 16: Bartley, Shih, Barowski and Wang teach the claim limitation of the semiconductor structure of claim 15, on which the claim limitation depends.
Bartley as modified by Shih and Barowski teaches that the VI die comprises a height that is taller than the first horizontally-fabricated semiconductor die section (Bartley: Fig. 1; vertical interconnect structure 16 is taller than the height of the first horizontally-fabricated semiconductor die section 12 including functional unit).
Regarding claim 17: Bartley, Shih, Barowski and Wang teach the claim limitation of the semiconductor structure of claim 15, on which the claim limitation depends, wherein the VI die comprises
an orientation selected from the group consisting of:
embedded in a trench between the first horizontally-fabricated semiconductor die section and a second horizontally-fabricated semiconductor die section,
attached adjacent to the first horizontally-fabricated semiconductor die section, surrounded on two sides by the first horizontally-fabricated semiconductor die section,
surrounded on three sides by the first horizontally-fabricated semiconductor die section, and surrounded on four sides by the first horizontally-fabricated semiconductor die section (Bartley: Fig. 1; [0033]-[0034]: attached adjacent to the first horizontally-fabricated semiconductor die section 12 including functional unit 14).
Regarding claim 19: Bartley, Shih, Barowski and Wang teach the claim limitation of the semiconductor structure of claim 15, on which the claim limitation depends, further comprising
a second level comprising a second VI die (Bartley: Fig. 4, [0043]-[0044]: second VI die 48 from bottommost VI die) embedded adjacent to a first second-level horizontally-fabricated semiconductor die section (Bartley: Figs. 1-2; [0033]-[0034]: right side horizontally-fabricated semiconductor die section opposite portion of first horizontally-fabricated semiconductor die 12 on the left side, at least in layer 2).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0098140 A1) in view of Shih (US 2018/0102311 A1) and Wang et al. (US 2016/0293576 A1) as applied above and further in view Qian et al. (US 2016/0111468 A1).
Regarding claim 4: Bartley, Shih and Wang teach the claim limitation of the semiconductor structure of claim 1, on which this claim depends.
Bartley as modified by Shih does not expressly teach that the semiconductor structure further comprises a surrounding material between the VI die and the first horizontally-fabricated semiconductor die section.
Qian teaches (e.g., Figs. 3D-3G) a semiconductor structure comprising
a surrounding material ([0016]: 141) between a VI die ([0031]—[0033]: structure comprising 371-374) and a first horizontally-fabricated semiconductor die section ([0024]-[0028]: region 120 of device 305).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley as modified by Shih, the surrounding material between the VI die and the first horizontally-fabricated semiconductor die section, as taught by Qian, for the benefits of reducing signal interferences between adjacent devices through the conductive channels.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0098140 A1) in view of Shih (US 2018/0102311 A1), Barowski et al. (US 2016/0070842 A1) and Wang et al. (US 2016/0293576 A1) as applied above and further in view of Chen et al. (US 2018/0151507 A1).
Regarding claim 18: Bartley, Shih, Barowski and Wang teach the claim limitation of the semiconductor structure of claim 15, on which this claim limitation depends,
Bartley as modified by Shih and Barowski does not expressly teach that the VI die further comprises alignment wings that protrude above the first horizontally-fabricated semiconductor die section.
Chen teaches (e.g., Figs. 10c and 14) a semiconductor structure comprising a VI die (205 see [0041] and [0059]) further comprising alignment wings ([0080] and [0085]: alignment structure 115 is in a form of wings) that protrude above a first horizontally-fabricated semiconductor die section (210/215 see [0055] and [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley as modified by Shih and Barowski, the VI die further comprising alignment wings that protrude above the first horizontally-fabricated semiconductor die section, for the benefits of increasing the accuracy of alignment of the interconnect structure and integrated circuit electrodes and thus improve device reliability.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0098140 A1) in view of Shih (US 2018/0102311 A1), Barowski et al. (US 2016/0070842 A1) and Wang et al. (US 2016/0293576 A1) as applied above and further in view of Yang et al. (US 2022/0384326 A1).
Regarding claim 20: Bartley, Shih, Barowski and Wang teach the claim limitation of the semiconductor structure of claim 15, on which the claim limitation depends, further comprising
Barley does not expressly teach a second VI die bonded to the VI die,
wherein the second VI die is bonded on a side of the VI die away from the substrate.
Yang teaches (e.g., Figs. 10A-11B) a semiconductor structure comprising a substrate ([0183]: 2);
Yang further teachers that a second VI die ([0148]-[0149]: second VI die 468 in third level from the bottommost interconnect die) bonded to a VI die ([0148]-[0149] and [0197]-[0198]: bottommost VI die 468; each horizontally-fabricated semiconductor die section 251 includes at least a VI die and all VI dies/dice are aligned as shown in Fig. 11A and upper die bonded to lower die, see [0185]-[0186] and [0197]-[0198]),
wherein the second VI die is bonded on a side of the VI die away from the substrate ([0183]-[0184]: 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor structure of Bartley as modified by Shih and Barowski, the second VI die bonded to the VI die, wherein the second VI die is bonded on a side of the VI die away from the substrate, as taught by Yang, for the benefits of increasing the integrated circuit density by stacking more device and at the same time ensure increased signal speeds between interconnected device by aligning the VI dies/dice in the integrated circuit device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference or combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or new references introduced due to new limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
Prosecution Insights