Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10, 12, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Suk et al. (US 2025/0070038).
Regarding claim 1, Suk discloses an electronic device, comprising:
a semiconductor die (210) having a side, first conductive terminals (213) along a first portion of the side, and second conductive terminals (215) along a second portion of the side (for example, above S1) [Fig. 3A];
a substrate (S1/S2) having conductive features (150) facing the first portion of the side of the semiconductor die (210) and electrically coupled to respective ones of the first conductive terminals (213) [Figs. 3A (annotated below), and 3B];
a capacitor die or a ceramic capacitor (400) having conductive capacitor terminals (411) facing the second portion of the side of the semiconductor die and electrically coupled to respective ones of the second conductive terminals [Figs. 3A-3B]; and
a package structure (360/300) at least partially enclosing the semiconductor die (210), the substrate (S1/S2) and the capacitor die or ceramic capacitor (400), a portion (300) of the package structure abutting the capacitor die or ceramic capacitor (400) extending through the substrate (S1/S2) to a bottom surface (bottom surface of 300, bottom of trench TR1 and/or bottom surface of S1/S2) of the electronic device (S1/S2,210, 250, 400, 360/300) [Fig. 3A, annotated below].
[AltContent: textbox (Bottom Surface of layer 300)][AltContent: textbox (S3)][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (S2)][AltContent: textbox (S1)][AltContent: textbox ((annotated))]
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Regarding claim 2, Suk discloses wherein:
the semiconductor die (210) has third conductive terminals (213) along a third portion of the side (above S2) [Fig. 3A, annotated above];
the substrate is a first substrate (S1) [Fig. 3A, annotated above];
the electronic device further comprises a second substrate (S2) having second conductive features (215) facing a third portion of the side of the semiconductor die (210) and electrically coupled to respective third conductive terminals [Fig. 3A, annotated above]; and
the capacitor die or ceramic capacitor (400) is located between the first and second substrates (S1/S2) [Fig. 3A, annotated above].
Regarding claim 3, Suk discloses wherein the substrate (S1/S2) has an opening (TR1); and the capacitor die or ceramic capacitor (400) is located in the opening of the substrate [Fig. 3A, annotated above].
Regarding claim 4, Suk discloses wherein the substrate (S1/S2) is a multilevel package substrate (105,107) [Fig. 3A, annotated above].
Regarding claim 5, Suk discloses wherein the substrate (S1/S2) is a laminated organic ceramic substrate [paragraphs 0026-0027 and 0029].
Regarding claim 6, Suk discloses wherein:
the second conductive terminals (215/350) are conductive metal pillars that extend outward from the second portion of the side of the semiconductor die [Fig. 3A and paragraph 0041];
the capacitor die or ceramic capacitor (400) is a capacitor die [Fig, 3A and paragraph 0042]; and
the conductive capacitor terminals (411/350) are further conductive metal pillars that extend toward, and are soldered to, respective ones of the conductive metal pillars [Fig. 3A, and paragraphs 0041-0042].
Regarding claim 7, Suk discloses wherein the capacitor die (400) includes a trench capacitor (459) formed in a semiconductor body (Section B) of the capacitor die [Fig. 3A and 4].
Regarding claim 8, Suk discloses wherein the first conductive terminals (213/350) are conductive metal pillars that extend outward from the first portion of the side of the semiconductor die [Fig. 3A and paragraph 0041]
Regarding claim 9, Suk discloses wherein the conductive capacitor terminals (213/350) of the capacitor die or ceramic capacitor are solder bumps [Fig. 3A and paragraph 0041].
Regarding claim 10, Suk discloses wherein the second conductive terminals (215/350) are solder bumps [paragraph 0041].
Regarding claim 12, Suk discloses wherein the package structure includes: a first molded structure (360) that at least partially encloses the semiconductor die and the substrate; and a mold underfill (300) at least partially encloses the semiconductor die, the substrate and the capacitor die or ceramic capacitor [Fig. 3A].
Regarding claim 15, Suk discloses wherein the capacitor die or ceramic capacitor (400) located between the substrate (S1/S2) and a side of the package structure (360/300) [Fig. 3A].
Regarding claim 16, Suk discloses a system, comprising:
a circuit board (800) [Fig. 3A and paragraph 0023]; and
an electronic device (S1/S2, S3, 210, 250, 400, 360/300) coupled to the circuit board (800) [Fig. 3A and Fig. 3A, annotated above], the electronic device having a semiconductor die (210), a substrate (S1/S2), a capacitor die or a ceramic capacitor (400), and a package structure (360/300), wherein:
the semiconductor die (210) has a side, first conductive terminals (213) along a first portion of the side, and second conductive terminals (215) along a second portion of the side [Fig. 3A];
the substrate (S1/S2) has conductive features (150) facing the first portion of the side of the semiconductor die and electrically coupled to respective ones of the first conductive terminals [Fig. 3A, annotated above];
the capacitor die or a ceramic capacitor (400) has conductive capacitor terminals (411) facing the second portion of the side of the semiconductor die and electrically coupled to respective ones of the second conductive terminals [Figs. 3A-3B and 4]; and
the package structure (360/300) at least partially enclosing the semiconductor die, the substrate and the capacitor die or ceramic capacitor, a portion of the package structure (300) abutting the capacitor die or ceramic capacitor (400) extending through the substrate (S1/S2) to a bottom surface (bottom surface of 300, bottom of trench TR1 and/or bottom surface of S1/S2) of the electronic device [Fig. 3A, annotated above].
Regarding claim 17, Suk discloses a method of fabricating an electronic device, the method comprising:
attaching conductive capacitor terminals (411) of a capacitor die or a ceramic capacitor (400) to respective second conductive terminals (215) of a semiconductor die (210) [Fig. 16];
attaching first conductive terminals (213) of the semiconductor die (210) to respective conductive features of a substrate (S1/S2) [Figs. 17 and 3A, annotated above]; and
forming a package structure (360/300) that at least partially encloses the semiconductor die, the substrate and the capacitor die or ceramic capacitor, a portion (300) of the package structure abutting the capacitor die or ceramic capacitor (400) extending through the substrate to a bottom surface (bottom surface of 300, bottom of trench TR1 and/or bottom surface of S1/S2) of the electronic device [Figs. 19 and 3A, above].
Regarding claim 18, Suk discloses wherein forming the package structure includes forming a mold underfill (360/300) at least partially encloses the semiconductor die, the substrate and the capacitor die or ceramic capacitor [Fig. 19 and 3A].
Regarding claim 20, Suk discloses wherein:
attaching the conductive capacitor terminals (411) of the capacitor die or ceramic capacitor (400) to the respective second conductive terminals (215) of the semiconductor die (210) includes performing a first flip-chip die attach process [Figs. 16-17 and paragraph 0108]; and
attaching the first conductive terminals (213) of the semiconductor die (210) to the respective conductive features (150) of the substrate (S1/S2) includes performing a second flip-chip die attach process [Figs. 16-17 and 3A, annotated above].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Suk et al. (US 2025/0070038) in view of OGAWA et al. (JP 2005197763 A).
Regarding claim 11, Suk does not disclose a ceramic capacitor.
Regarding claim 11, Ogawa teaches wherein the capacitor die or ceramic capacitor is a ceramic capacitor [pages 4 and 15 in English Machine Translation].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Suk by including a ceramic capacitor as taught by Ogawa because it helps to obtain high reliability [page 4 in English Machine Translation].
Allowable Subject Matter
Claims 13-14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on March 30, 2026 have been fully considered but they are not persuasive. Applicant’s representative argue that Suk does not teach the newly added limitation about “a portion of the package structure abutting the capacitor die or ceramic capacitor extending through the substrate to a bottom surface of the electronic device” because the layer 300 in Sulk does not extend further downward into dielectric layers 103 and 101 of substrate 100 [See remarks]. However, the current rejection cured this deficiency by labeling layers 105 and 107 as the new substrate (S1/S2). [See claims rejection above]. Hence, Sulk does teach the argued limitation since layer 300 extends further downward into dielectric layers 105 and 107. As such, the rejection is considered to be proper.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Elsherbini et al. (US 2020/0273840) teaches a capacitor (114-1), semiconductor die (114-2/114-6, 114-3) and substrate (102) [Figs. 1 and 7].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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