DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination. Claims 1, 6, 8-9, 14, 16-17, and 20 are newly amended by the response received August 24, 2026.
Examiner notes that paragraphs [0050]-[0053] and [0055]-[0056] are directed to URDMSR but intervening paragraph [0054] is directed to FIG. 2 which describes UWRMSR. Similarly, Examiner notes that paragraphs [0057]-[0062] are directed to UWRMSR but immediately following paragraph [0063] is directed to FIG. 4 which describes URDMSR. Examiner recommends having paragraph [0054] be directed to a figure which describes URDMSR and paragraph [0063] be directed to a figure which describes UWRMSR so that FIG. 2 and FIG. 4 are presented in the context of respective relevant portions of the specification for clarity of the invention.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
Paragraph [0054] as amended on August 24, 2026, line 1, associates FIG. 2 with UWRMSR; however, paragraph [0004] continues to associate FIG. 2 with URDMSR.
In paragraph [0062] as amended on August 24, 2026, lines 1-2, “UWRMSR SRC, IMM” is new matter; note that FIG. 2 discloses UWRMSR IMM32, R64 (which has the immediate operand as the operand directly adjacent to UWRMSR).
Paragraph [0063] as amended on August 24, 2026, line 1, associates FIG. 4 with URDMSR; however, paragraph [0006] continues to associate FIG. 4 with UWRMSR.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Examiner submits that instructions which, for example, read some type of control register (e.g., to determine whether an overflow flag is set), or write some type of status register (e.g., to set an overflow flag), were widespread before the effective filing date of the claimed invention. As such, Examiner submits that the title does not have sufficient informative value in indexing, classifying, searching, etc. Examiner generally notes that if a satisfactory title is not supplied by the applicant, the examiner will, at the time of allowance, change the title by an examiner s amendment to increase informative value in indexing, classifying, searching, etc.
Drawings
The drawings are objected to because:
Numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. However, the drawings do not meet this requirement. As one example, see the text of FIG. 2.
In amended FIG. 5, the lead line associated with reference character 121 mingles with text.
In amended FIG. 32, reference characters 3200, 3210, 3230, 3240, 3242, 3244, 3246, 3248, and 3250 all appear to be directed to a same surface area.
Words must appear in a horizontal, left-to-right fashion when the page is either upright or turned so that the top becomes the right side, except for graphs utilizing standard scientific convention to denote the axis of abscissas (of X) and the axis of ordinates (of Y). However, amended FIG. 33 has two instances (RING INTERCONNECT, THREAD DISPATCHER) of this requirement not being met.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the execution circuitry to execute the decoded instance of the single instruction according to the opcode” in lines 12-13. However, there is insufficient antecedent basis for this limitation in the claims. For the purposes of this office action, Examiner is interpreting this limitation as “the execution circuitry, wherein the execution circuitry is to execute the decoded instance of the single instruction according to the opcode”.
Claims 2-8 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 17 recites the limitation “the execution circuitry to execute the decoded instance of the single instruction according to the opcode” in lines 13-14. However, there is insufficient antecedent basis for this limitation in the claims. For the purposes of this office action, Examiner is interpreting this limitation as “the execution circuitry, wherein the execution circuitry is to execute the decoded instance of the single instruction according to the opcode”.
Claims 18-20 are rejected for failing to alleviate the rejection of claim 17 above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 and 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. While the claim(s) do recite circuitry, paragraph [00345] discloses: “Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.” As such, Examiner recommends inserting the limitation “hardware” in an appropriate part of the claim and all relevant places in further dependent claims (e.g. replacing the limitation “execution circuitry” with the limitation “hardware execution circuitry”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 9-10, 12-15, 17-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang) (US 20230161593 A1) in view of Lee (US 20150186077 A1).
Consider claim 1, Wang discloses an apparatus comprising: decoder circuitry to decode an instance of a single instruction ([0007], lines 6-8, instruction translator is configured to obtain the target instruction from the instruction cache, and decode the target instruction), wherein the instance of the single instruction is to include one or more fields for an opcode ([0036], line 6, opcode; [0036], line 15, opcode), one or more fields for a source operand ([0030], lines 3-4, source operand of the instruction) that is to store a control and/or status register address ([0036], lines 8-9, the first type of target instruction TAI1 may include a model specific register index to point to an address of a model specific register; [0036], lines 17-18, a model specific register index to point to a model specific register), wherein the opcode is to indicate that execution circuitry is to read data from the control and/or status register addressed by the source operand responsive to access to the control and/or status register being allowed ([0038], lines 1-4, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible; [0045], lines 7-10, it is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction), wherein access to the control and/or status register is at least in part determined by data of an operating system controlled data structure indexed by the control and/or status register address ([0038], lines 1-8, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible by searching a continuous model specific register space MSPx (associated with the model specific register set 238 inside the microprocessor 150) defined by a start address ST and a BitMap BM according to the instruction of the target instruction TAI; [0043], lines 4-6, an input/output system (Basic Input/output System, BIOS) may be executed to initialize the BitMap BM; [0051], lines 3-4, the Basic Input/Output System (BIOS) executes to configure the memory BitMap; [0045], lines 6-10, another model specific register space according to an embodiment of the present invention. It is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0047], lines 1-5, the microprocessor 150 may first search for BitMapLMSRRB and BitMapLMSRWB (the 2KB spaces associated with LWB and LRB), and then search for BitMapHMSRRB and BitMapHMSRWB (the 2KB spaces associated with HWB and HRB); [0038], lines 11-22, the read indication bit R of the model specific register space MSPx indicates if an associated model specific register is readable in unprivileged mode, while the write indication bit W of the model specific register space MSPx indicates if an associated model specific register is writable in unprivileged mode. Exemplarily, when the bit value of the read indication bit R is 1, it means that the corresponding model specific register may be read in an unprivileged state. Likewise, when the bit value of the write indication bit W is 1, it indicates that the corresponding model specific register may be written in an unprivileged state; [0053], line 3, indexing operation shown in FIG. 4; [0054], line 3, indexing operation shown in FIG. 5); and the execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0030], lines 2-5, when the instruction is ready to be executed (the source operand of the instruction is ready), this instruction is scheduled and dispatched to the corresponding execution unit; [0031], line 1-4, execution units 216 may include one or more integer execution units, such as integer arithmetic logic units, one or more floating point execution units, memory order buffers (MOB s), and the like; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction).
However, Wang does not explicitly disclose the instance of the single instruction includes one or more fields for a destination register operand, wherein the opcode is to indicate that execution circuitry is to write the data into the destination register operand.
On the other hand, Lee explicitly discloses an instance of a single instruction includes one or more fields for a destination register operand, wherein an opcode is to indicate that execution circuitry is to write data into the destination register operand ([0028], line 2, data access instruction; [0028], lines 7-11, in some embodiments, the data access instruction may be a user-level instruction capable of being performed by user-level software (e.g., user-level applications not just the operating system or similar privileged and/or supervisory-level software). For example, the user-level instruction may be performed at ring 3 instead of only at ring 0; [0035], lines 16-18, in some embodiments, the data access instruction may also cause the processor to store the retrieved or otherwise accessed data 110; [0035], lines 21-23, examples of suitable destination storage locations include, but are not limited to, general-purpose registers of the processor; [0035], line 1, execution unit; [0042], lines 1-5, data may be stored in a destination storage location (e.g., an architectural register or other storage location of the processor) indicated by the data access instruction, in response to and/or as a result of the data access instruction; [0062], lines 8-11, the instruction format also includes a destination specifier 662, which may include bits or one or more fields to specify an address of a processor register or other destination storage location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee with the invention of Wang in order to provide increase capability and functionality via supporting storing accessed data to a destination.
Consider claim 2, the overall combination entails the apparatus of claim 1 (see above). In addition, Lee further discloses a source operand is a general purpose register ([0029], lines 1-5, the data access instruction may explicitly specify (e.g., through one or more fields or a set of bits), or otherwise indicate (e.g., implicitly indicate), a data address 112 associated with desired data 110 to be looked up or otherwise accessed; [0029], lines 14-18, in some embodiments, the data address may be provided by an immediate of the instruction. In other embodiments, the data address may be stored a register (e.g., a general-purpose register) that is explicitly specified or implicitly indicated by the instruction); [0062], lines 14-18, the instruction format also includes a data address specifier 664, which may include bits or one or more fields to specify a data address, or to specify a register (e.g., a general-purpose register) storing the data address). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the aforementioned further teaching of Lee with the previously-explained combination of Wang and Lee in order to increase flexibility and capability via support for a further source operand location.
Consider claim 4, the overall combination entails the apparatus of claim 1 (see above), wherein the instance of the single instruction is executable in a user privilege level (Wang, [0022], lines 1-5, the invention discloses a device and a method that … may read and write a model specific register (MSR) in a user state and a privileged state, so as to make the reading and the writing of the MSR more flexible; [0038], lines 1-4, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible; [0045], lines 7-10, it is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction; Lee, [0028], lines 7-11, in some embodiments, the data access instruction may be a user-level instruction capable of being performed by user-level software (e.g., user-level applications not just the operating system or similar privileged and/or supervisory-level software). For example, the user-level instruction may be performed at ring 3 instead of only at ring 0).
Consider claim 5, the overall combination entails the apparatus of claim 1 (see above), wherein the control and/or status register is a model specific register (Wang, [0022], lines 1-5, the invention discloses a device and a method that … may read and write a model specific register (MSR) in a user state and a privileged state, so as to make the reading and the writing of the MSR more flexible).
Consider claim 6, the overall combination entails the apparatus of claim 1 (see above), wherein the operating system controlled data structure is a bitmap that is to have a plurality of entries (Wang, [0038], line 7, BitMap BM; [0047], lines 1-5, the microprocessor 150 may first search for BitMapLMSRRB and BitMapLMSRWB (the 2KB spaces associated with LWB and LRB), and then search for BitMapHMSRRB and BitMapHMSRWB (the 2KB spaces associated with HWB and HRB)), wherein an entry of the bitmap is to indicate each control and/or status register that is accessible (Wang, [0038], lines 11-22, the read indication bit R of the model specific register space MSPx indicates if an associated model specific register is readable in unprivileged mode, while the write indication bit W of the model specific register space MSPx indicates if an associated model specific register is writable in unprivileged mode. Exemplarily, when the bit value of the read indication bit R is 1, it means that the corresponding model specific register may be read in an unprivileged state. Likewise, when the bit value of the write indication bit W is 1, it indicates that the corresponding model specific register may be written in an unprivileged state; [0039], lines 3-7, BitMap BM totally has 64 bits, which may be divided into 32 groups (each group encompasses a read indication bit R and a write indication bit W) corresponding with the model specific registers with one-by-one manner; [0045], lines 17-18, the read indication value R corresponding to the target instruction TAI; [0045], lines 22-23, the write instruction value W corresponding to the target instruction TAI).
Consider claim 7, the overall combination entails the apparatus of claim 6 (see above), wherein a first portion of the control and/or status register address is to act as a byte offset into the bitmap and a second portion of the control and/or status register address is to act as a bit offset into a byte of an indexed byte of the bitmap (Wang, FIG. 4, for example, wherein a first portion of an MSR is used to select one of byte 63:56, … , and byte 7:0, and a second portion of an MSR is used to select a particular W and/or R bit within that byte that corresponds to that MSR; [0053], line 3, indexing operation shown in FIG. 4; [0054], line 3, indexing operation shown in FIG. 5).
Consider claim 9, Wang discloses a method comprising: decoding an instance of a single instruction ([0007], lines 6-8, instruction translator is configured to obtain the target instruction from the instruction cache, and decode the target instruction), wherein the instance of the single instruction is to include one or more fields for an opcode ([0036], line 6, opcode; [0036], line 15, opcode), one or more fields for a source operand ([0030], lines 3-4, source operand of the instruction) that is to store a control and/or status register address ([0036], lines 8-9, the first type of target instruction TAI1 may include a model specific register index to point to an address of a model specific register; [0036], lines 17-18, a model specific register index to point to a model specific register), wherein the opcode is to indicate that execution circuitry is to read data from the control and/or status register addressed by the source operand responsive to access to the control and/or status register being allowed ([0038], lines 1-4, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible; [0045], lines 7-10, it is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction), wherein access to the control and/or status register is at least in part determined by data of an operating system controlled data structure indexed by the control and/or status register address ([0038], lines 1-8, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible by searching a continuous model specific register space MSPx (associated with the model specific register set 238 inside the microprocessor 150) defined by a start address ST and a BitMap BM according to the instruction of the target instruction TAI; [0043], lines 4-6, an input/output system (Basic Input/output System, BIOS) may be executed to initialize the BitMap BM; [0051], lines 3-4, the Basic Input/Output System (BIOS) executes to configure the memory BitMap; [0045], lines 6-10, another model specific register space according to an embodiment of the present invention. It is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0047], lines 1-5, the microprocessor 150 may first search for BitMapLMSRRB and BitMapLMSRWB (the 2KB spaces associated with LWB and LRB), and then search for BitMapHMSRRB and BitMapHMSRWB (the 2KB spaces associated with HWB and HRB); [0038], lines 11-22, the read indication bit R of the model specific register space MSPx indicates if an associated model specific register is readable in unprivileged mode, while the write indication bit W of the model specific register space MSPx indicates if an associated model specific register is writable in unprivileged mode. Exemplarily, when the bit value of the read indication bit R is 1, it means that the corresponding model specific register may be read in an unprivileged state. Likewise, when the bit value of the write indication bit W is 1, it indicates that the corresponding model specific register may be written in an unprivileged state; [0053], line 3, indexing operation shown in FIG. 4; [0054], line 3, indexing operation shown in FIG. 5); and executing the decoded instance of the single instruction according to the opcode ([0030], lines 2-5, when the instruction is ready to be executed (the source operand of the instruction is ready), this instruction is scheduled and dispatched to the corresponding execution unit; [0031], line 1-4, execution units 216 may include one or more integer execution units, such as integer arithmetic logic units, one or more floating point execution units, memory order buffers (MOB s), and the like; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction).
However, Wang does not explicitly disclose the instance of the single instruction includes one or more fields for a destination register operand, wherein the opcode is to indicate that execution circuitry is to write the data into the destination register operand.
On the other hand, Lee explicitly discloses an instance of a single instruction includes one or more fields for a destination register operand, wherein an opcode is to indicate that execution circuitry is to write data into the destination register operand ([0028], line 2, data access instruction; [0028], lines 7-11, in some embodiments, the data access instruction may be a user-level instruction capable of being performed by user-level software (e.g., user-level applications not just the operating system or similar privileged and/or supervisory-level software). For example, the user-level instruction may be performed at ring 3 instead of only at ring 0; [0035], lines 16-18, in some embodiments, the data access instruction may also cause the processor to store the retrieved or otherwise accessed data 110; [0035], lines 21-23, examples of suitable destination storage locations include, but are not limited to, general-purpose registers of the processor; [0035], line 1, execution unit; [0042], lines 1-5, data may be stored in a destination storage location (e.g., an architectural register or other storage location of the processor) indicated by the data access instruction, in response to and/or as a result of the data access instruction; [0062], lines 8-11, the instruction format also includes a destination specifier 662, which may include bits or one or more fields to specify an address of a processor register or other destination storage location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee with the invention of Wang in order to provide increase capability and functionality via supporting storing accessed data to a destination.
Consider claim 10, the overall combination entails the method of claim 9 (see above). In addition, Lee further discloses a source operand is a general purpose register ([0029], lines 1-5, the data access instruction may explicitly specify (e.g., through one or more fields or a set of bits), or otherwise indicate (e.g., implicitly indicate), a data address 112 associated with desired data 110 to be looked up or otherwise accessed; [0029], lines 14-18, in some embodiments, the data address may be provided by an immediate of the instruction. In other embodiments, the data address may be stored a register (e.g., a general-purpose register) that is explicitly specified or implicitly indicated by the instruction); [0062], lines 14-18, the instruction format also includes a data address specifier 664, which may include bits or one or more fields to specify a data address, or to specify a register (e.g., a general-purpose register) storing the data address). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the aforementioned further teaching of Lee with the previously-explained combination of Wang and Lee in order to increase flexibility and capability via support for a further source operand location.
Consider claim 12, the overall combination entails the method of claim 9 (see above), wherein the instance of the single instruction is executable in a user privilege level (Wang, [0022], lines 1-5, the invention discloses a device and a method that … may read and write a model specific register (MSR) in a user state and a privileged state, so as to make the reading and the writing of the MSR more flexible; [0038], lines 1-4, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible; [0045], lines 7-10, it is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction; Lee, [0028], lines 7-11, in some embodiments, the data access instruction may be a user-level instruction capable of being performed by user-level software (e.g., user-level applications not just the operating system or similar privileged and/or supervisory-level software). For example, the user-level instruction may be performed at ring 3 instead of only at ring 0).
Consider claim 13, the overall combination entails the method of claim 9 (see above), wherein the control and/or status register is a model specific register (Wang, [0022], lines 1-5, the invention discloses a device and a method that … may read and write a model specific register (MSR) in a user state and a privileged state, so as to make the reading and the writing of the MSR more flexible).
Consider claim 14, the overall combination entails the method of claim 9 (see above), wherein the operating system controlled data structure is a bitmap that is to have a plurality of entries (Wang, [0038], line 7, BitMap BM; [0047], lines 1-5, the microprocessor 150 may first search for BitMapLMSRRB and BitMapLMSRWB (the 2KB spaces associated with LWB and LRB), and then search for BitMapHMSRRB and BitMapHMSRWB (the 2KB spaces associated with HWB and HRB)), wherein an entry of the bitmap is to indicate each control and/or status register that is accessible (Wang, [0038], lines 11-22, the read indication bit R of the model specific register space MSPx indicates if an associated model specific register is readable in unprivileged mode, while the write indication bit W of the model specific register space MSPx indicates if an associated model specific register is writable in unprivileged mode. Exemplarily, when the bit value of the read indication bit R is 1, it means that the corresponding model specific register may be read in an unprivileged state. Likewise, when the bit value of the write indication bit W is 1, it indicates that the corresponding model specific register may be written in an unprivileged state; [0039], lines 3-7, BitMap BM totally has 64 bits, which may be divided into 32 groups (each group encompasses a read indication bit R and a write indication bit W) corresponding with the model specific registers with one-by-one manner; [0045], lines 17-18, the read indication value R corresponding to the target instruction TAI; [0045], lines 22-23, the write instruction value W corresponding to the target instruction TAI).
Consider claim 15, the overall combination entails the method of claim 14 (see above), wherein a first portion of the control and/or status register address is to act as a byte offset into the bitmap and a second portion of the control and/or status register address is to act as a bit offset into a byte of an indexed byte of the bitmap (Wang, FIG. 4, for example, wherein a first portion of an MSR is used to select one of byte 63:56, … , and byte 7:0, and a second portion of an MSR is used to select a particular W and/or R bit within that byte that corresponds to that MSR; [0053], line 3, indexing operation shown in FIG. 4; [0054], line 3, indexing operation shown in FIG. 5).
Consider claim 17, Wang discloses a system comprising: memory ([0029], lines 2-3, instruction cache) to store an instance of a single instruction ([0007], lines 6-8, instruction translator is configured to obtain the target instruction from the instruction cache, and decode the target instruction), wherein the instance of the single instruction is to include one or more fields for an opcode ([0036], line 6, opcode; [0036], line 15, opcode), one or more fields for a source operand ([0030], lines 3-4, source operand of the instruction) that is to store a control and/or status register address ([0036], lines 8-9, the first type of target instruction TAI1 may include a model specific register index to point to an address of a model specific register; [0036], lines 17-18, a model specific register index to point to a model specific register), wherein the opcode is to indicate that execution circuitry is to read data from the control and/or status register addressed by the source operand responsive to access to the control and/or status register being allowed ([0038], lines 1-4, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible; [0045], lines 7-10, it is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction), wherein access to the control and/or status register is at least in part determined by data of an operating system controlled data structure indexed by the control and/or status register address ([0038], lines 1-8, when the target instruction TAI is a specific instruction, the microprocessor 150 determines if the model specific register indicated by the target instruction TAI is accessible by searching a continuous model specific register space MSPx (associated with the model specific register set 238 inside the microprocessor 150) defined by a start address ST and a BitMap BM according to the instruction of the target instruction TAI; [0043], lines 4-6, an input/output system (Basic Input/output System, BIOS) may be executed to initialize the BitMap BM; [0051], lines 3-4, the Basic Input/Output System (BIOS) executes to configure the memory BitMap; [0045], lines 6-10, another model specific register space according to an embodiment of the present invention. It is also suitable for determining whether a specific instruction in the unprivileged state has the permission to read and write a model specific register; [0047], lines 1-5, the microprocessor 150 may first search for BitMapLMSRRB and BitMapLMSRWB (the 2KB spaces associated with LWB and LRB), and then search for BitMapHMSRRB and BitMapHMSRWB (the 2KB spaces associated with HWB and HRB); [0038], lines 11-22, the read indication bit R of the model specific register space MSPx indicates if an associated model specific register is readable in unprivileged mode, while the write indication bit W of the model specific register space MSPx indicates if an associated model specific register is writable in unprivileged mode. Exemplarily, when the bit value of the read indication bit R is 1, it means that the corresponding model specific register may be read in an unprivileged state. Likewise, when the bit value of the write indication bit W is 1, it indicates that the corresponding model specific register may be written in an unprivileged state; [0053], line 3, indexing operation shown in FIG. 4; [0054], line 3, indexing operation shown in FIG. 5); decoder circuitry to decode the instance of the single instruction ([0007], lines 6-8, instruction translator is configured to obtain the target instruction from the instruction cache, and decode the target instruction); and the execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0030], lines 2-5, when the instruction is ready to be executed (the source operand of the instruction is ready), this instruction is scheduled and dispatched to the corresponding execution unit; [0031], line 1-4, execution units 216 may include one or more integer execution units, such as integer arithmetic logic units, one or more floating point execution units, memory order buffers (MOB s), and the like; [0059], lines 1-7, when the microprocessor 150 operates in an unprivileged state (for example, the operation is in a user state), it needs to perform an access permission check for the target instruction TAI (which is a specific instruction now). When the target instruction passes the access permission check, the process proceeds to step 760 to complete the specific operation indicated by the specific instruction).
However, Wang does not explicitly disclose the instance of the single instruction includes one or more fields for a destination register operand, wherein the opcode is to indicate that execution circuitry is to write the data into the destination register operand.
On the other hand, Lee explicitly discloses an instance of a single instruction includes one or more fields for a destination register operand, wherein an opcode is to indicate that execution circuitry is to write data into the destination register operand ([0028], line 2, data access instruction; [0028], lines 7-11, in some embodiments, the data access instruction may be a user-level instruction capable of being performed by user-level software (e.g., user-level applications not just the operating system or similar privileged and/or supervisory-level software). For example, the user-level instruction may be performed at ring 3 instead of only at ring 0; [0035], lines 16-18, in some embodiments, the data access instruction may also cause the processor to store the retrieved or otherwise accessed data 110; [0035], lines 21-23, examples of suitable destination storage locations include, but are not limited to, general-purpose registers of the processor; [0035], line 1, execution unit; [0042], lines 1-5, data may be stored in a destination storage location (e.g., an architectural register or other storage location of the processor) indicated by the data access instruction, in response to and/or as a result of the data access instruction; [0062], lines 8-11, the instruction format also includes a destination specifier 662, which may include bits or one or more fields to specify an address of a processor register or other destination storage location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee with the invention of Wang in order to provide increase capability and functionality via supporting storing accessed data to a destination.
Consider claim 18, the overall combination entails the system of claim 17 (see above). In addition, Lee further discloses a source operand is a general purpose register ([0029], lines 1-5, the data access instruction may explicitly specify (e.g., through one or more fields or a set of bits), or otherwise indicate (e.g., implicitly indicate), a data address 112 associated with desired data 110 to be looked up or otherwise accessed; [0029], lines 14-18, in some embodiments, the data address may be provided by an immediate of the instruction. In other embodiments, the data address may be stored a register (e.g., a general-purpose register) that is explicitly specified or implicitly indicated by the instruction); [0062], lines 14-18, the instruction format also includes a data address specifier 664, which may include bits or one or more fields to specify a data address, or to specify a register (e.g., a general-purpose register) storing the data address). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the aforementioned further teaching of Lee with the previously-explained combination of Wang and Lee in order to increase flexibility and capability via support for a further source operand location.
Consider claim 20, the overall combination entails the system of claim 17 (see above), wherein the operating system controlled data structure is a bitmap that is to have a plurality of entries (Wang, [0038], line 7, BitMap BM; [0047], lines 1-5, the microprocessor 150 may first search for BitMapLMSRRB and BitMapLMSRWB (the 2KB spaces associated with LWB and LRB), and then search for BitMapHMSRRB and BitMapHMSRWB (the 2KB spaces associated with HWB and HRB)), wherein an entry of the bitmap is to indicate each control and/or status register that is accessible (Wang, [0038], lines 11-22, the read indication bit R of the model specific register space MSPx indicates if an associated model specific register is readable in unprivileged mode, while the write indication bit W of the model specific register space MSPx indicates if an associated model specific register is writable in unprivileged mode. Exemplarily, when the bit value of the read indication bit R is 1, it means that the corresponding model specific register may be read in an unprivileged state. Likewise, when the bit value of the write indication bit W is 1, it indicates that the corresponding model specific register may be written in an unprivileged state; [0039], lines 3-7, BitMap BM totally has 64 bits, which may be divided into 32 groups (each group encompasses a read indication bit R and a write indication bit W) corresponding with the model specific registers with one-by-one manner; [0045], lines 17-18, the read indication value R corresponding to the target instruction TAI; [0045], lines 22-23, the write instruction value W corresponding to the target instruction TAI).
Claim(s) 3, 11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Lee as applied to claims 1, 9, and 17 above, and further in view of Toll et al. (Toll) (US 7941651 B1).
Consider claim 3, the combination thus far entails the apparatus of claim 1 (see above), wherein the source operand is an immediate that is to encode the control and/or status register address (Wang, [0036], lines 16-18, immediate data of the second type of target instruction TAI2 may also include a model specific register index to point to a model specific register), wherein the instance of the single instruction further comprises a prefix (Wang, [0036], line 15 escape code).
However, the combination thus far does not entail that the immediate is a 32-bit immediate. The combination thus far also does not entail that the prefix is to indicate a use of a 32-bit immediate.
On the other hand, Toll discloses an immediate is a 32-bit immediate (col. 8, line 35, immediate data of 8-, 16-, 32- or 64-bits; col. 8, lines 38-39, 32-bit immediate data) and a prefix is to indicate a use of an immediate (col. 8, lines 50-52, an optional PREFIX 476 beginning with a binary value of 01001 (hexadecimal values 48-4F) may be used to indicate that a 64-bit long immediate data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Toll with the combination of Wang and Lee in order to support operations involving a 32-bit immediate in particular.
Consider claim 11, the combination thus far entails the method of claim 9 (see above), wherein the source operand is an immediate that is to encode the control and/or status register address (Wang, [0036], lines 16-18, immediate data of the second type of target instruction TAI2 may also include a model specific register index to point to a model specific register), wherein the instance of the single instruction further comprises a prefix (Wang, [0036], line 15 escape code).
However, the combination thus far does not entail that the immediate is a 32-bit immediate. The combination thus far also does not entail that the prefix is to indicate a use of a 32-bit immediate.
On the other hand, Toll discloses an immediate is a 32-bit immediate (col. 8, line 35, immediate data of 8-, 16-, 32- or 64-bits; col. 8, lines 38-39, 32-bit immediate data) and a prefix is to indicate a use of an immediate (col. 8, lines 50-52, an optional PREFIX 476 beginning with a binary value of 01001 (hexadecimal values 48-4F) may be used to indicate that a 64-bit long immediate data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Toll with the combination of Wang and Lee in order to support operations involving a 32-bit immediate in particular.
Consider claim 19, the combination thus far entails the system of claim 17 (see above), wherein the source operand is an immediate that is to encode the control and/or status register address (Wang, [0036], lines 16-18, immediate data of the second type of target instruction TAI2 may also include a model specific register index to point to a model specific register), wherein the instance of the single instruction further comprises a prefix (Wang, [0036], line 15 escape code).
However, the combination thus far does not entail that the immediate is a 32-bit immediate. The combination thus far also does not entail that the prefix is to indicate a use of a 32-bit immediate.
On the other hand, Toll discloses an immediate is a 32-bit immediate (col. 8, line 35, immediate data of 8-, 16-, 32- or 64-bits; col. 8, lines 38-39, 32-bit immediate data) and a prefix is to indicate a use of an immediate (col. 8, lines 50-52, an optional PREFIX 476 beginning with a binary value of 01001 (hexadecimal values 48-4F) may be used to indicate that a 64-bit long immediate data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Toll with the combination of Wang and Lee in order to support operations involving a 32-bit immediate in particular.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Lee as applied to claims 1 and 9 above, and further in view of Suginaka (US 20170220795 A1).
Consider claim 8, the combination thus far entails the apparatus of claim 1 (see above), further comprising a control and/or status register that is to provide an address to the operating system controlled data structure (Wang, [0043], lines 2-4, the start address ST and possible offset value are stored in another model specific register). However, the combination thus far does not entail the control and/or status register is to provide an indication of if the instance of the single instruction is enabled to be executed.
On the other hand, Suginaka discloses a control and/or status register is to provide an indication of if an instance of the single instruction is enabled to be executed ([0056], lines 1-4, when the register 121 relating to Syscall instruction in the MSR 12 is Disable (=0), the CPU 11 generates an invalid opcode exception in response to the issuance of a Syscall instruction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Suginaka with the combination of Wang and Lee in order to increase processor capability and/or security in the event that execution of the instruction is undesirable and/or unsafe (Suginaka [0056], line 17).
Consider claim 16, the combination thus far entails the method of claim 9 (see above), wherein a control and/or status register provides an address to the operating system controlled data structure (Wang, [0043], lines 2-4, the start address ST and possible offset value are stored in another model specific register). However, the combination thus far does not entail the control and/or status register is to provide an indication of if the instance of the single instruction is enabled to be executed.
On the other hand, Suginaka discloses a control and/or status register is to provide an indication of if an instance of the single instruction is enabled to be executed ([0056], lines 1-4, when the register 121 relating to Syscall instruction in the MSR 12 is Disable (=0), the CPU 11 generates an invalid opcode exception in response to the issuance of a Syscall instruction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Suginaka with the combination of Wang and Lee in order to increase processor capability and/or security in the event that execution of the instruction is undesirable and/or unsafe (Suginaka [0056], line 17).
Response to Arguments
Applicant on page 15 argues: ‘As noted in MPEP 707.07(d), "[t]he examiner should, as a part of the first Office action on the merits, identify any claims which he or she judges, as presently recited, to be allowable and/or should suggest any way in which he or she considers that rejected claims may be amended to make them allowable." As this was not done in the first Office action on the merits, the Applicant respectfully requests suggestions regarding allowability including claim amendment suggestions in any subsequent action. Providing prescribed guidance is in the interest of compact prosecution.’
However, Examiner has no current suggestions regarding a way that rejected claims may be amended to make them allowable. In the event that Examiner determines a way that rejected claims may be amended to make them allowable, Examiner will immediately convey the way to Applicant’s representative.
Applicant on page 15 argues: “The Office Action objects to the specification because of the alleged informalities. Applicant has amended several paragraphs.”
Various previously presented objections to the specification are withdrawn in view of the amendments to the specification. However, one previously presented objection to the specification remains applicable, and in various cases the amendments to the specification introduce additional objectionable issues — see the specification section above.
Applicant on page 15 argues: “The Office Action objects several drawings. Applicant amends Figures 1, 3, 5, 11, 12, 13, 16, 17A, 17B, 17C, 17D, 18A, 18B, 18C, 19, 20, 23, 32, and 33.”
Various previously presented objections to the drawings are withdrawn in view of the amendments to the drawings. However, other previously presented objections to the drawings remain applicable, and in one case the amendments to the drawings introduce an additional objectionable issue — see the drawings section above.
Applicant on page 15 argues: “With respect to claim 1, wherein is not needed, but Applicant added it because it does not matter.”
In view of the aforementioned amendment, the previously presented objection is withdrawn.
Applicant on page 15 argues: ‘With respect to claim 1, "the data in the destination register operand" is perfectly fine grammatically and in context, however, Applicant has amended the claim to use "into" instead of "in."’
In view of the aforementioned amendment, the previously presented objection is withdrawn.
Applicant across pages 15-16 argues: ‘With respect to claim 6, there is only one "data structure" that this could refer to and there is no reason to require "operating system controlled," but Applicant has added the extra verbiage. Applicant notes that is extremely well settled that "the failure to provide explicit antecedent basis for terms does not always render a claim indefinite. If the scope of a claim would be reasonably ascertainable by those skilled in the art, then the claim is not indefinite" as noted in MPEP 21730.05(e) and that these sort of objects again serve no purpose with respect to compact prosecution as both the examiner and Applicant are forced to deal with something that does not legally, grammatically, or rationally matter.’
In view of the aforementioned amendment, the previously presented objection is withdrawn.
Applicant on page 16 argues: ‘Applicant made similar changes to the claims with similar language in the interest of compact prosecution so that these non-issues are not brought up again.’
In view of the aforementioned similar changes, the associated previously presented objections are withdrawn.
Applicant on page 16 argues: ‘Claims 1-8 and 17-20 stand rejected under 35 U.S.C. § 101 because the claimed invention is allegedly directed to non-statutory subject matter. The Office asserts that the description of HDL indicates that circuitry in the claims is software per se. This "understanding" of HDL as being circuitry is utterly inconsistent with any normal usage by a PHOSITA or even an undergraduate's understanding. This rejection is not in the interest of compact prosecution as it is a waste of the Examiner's, and Applicant's, time to make and respond to a rejection that is devoid of any technical or legal basis. Applicant is not sure is this misunderstanding is a byproduct of the Office's AI tools, but if there is a question as to how a PHOSITA would understand HDL, Applicant respectfully requests a meeting with the examiner and his SPE to discuss with a note that Applicant's representative expects the Office to provide evidence of any person that has obtained a CE or EE degree that has written HDL and then implemented into hardware as believing that HDL is circuitry.’
Examiner first notes that the Office Action did not assert that the circuitry in the claims is software per se; rather, the Office Action conveyed that the circuitry in the claims can be interpreted as software per se. Examiner submits that just as a machine can be a hardware machine or a software machine (e.g., a virtual machine), so too can circuitry be hardware circuitry or software circuitry (e.g., hardware description language). Additionally, as noted, the instant specification further supports this interpretation via instant paragraph [00345] (“Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.”) Just as a dictionary that defines words comprises the words, so too does HDL that defines circuits comprises the circuits.
Examiner further submits that other patent documents in the art support Examiner’s broadest reasonable interpretation. As one example, see Luick (US 8812822 B2) which discloses “Design structure 1120 comprises the circuits described above and shown in FIGS. 1-3, 6 and 10 in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure 1120 may be contained on one or more machine readable medium” (see col. 25, lines 46-51). Luick further claims “A design structure embodied in a non-transitory machine readable storage device for at least one of designing, manufacturing, and testing a design, the design structure comprising: a processor comprising: a level two cache; a level one cache; a cascaded delayed execution pipeline unit having two or more execution pipelines …; and predecoder circuitry configured to …”
In other words, Luick supports Examiner’s position that HDL may be considered to comprise circuitry, and therefore the circuitry recited in the claims is not necessarily hardware. Examiner notes other patents convey analogous subject matter; see, for example, Allen, Jr. (US 8140803 B2) and Cox (US 7752393 B2).
Applicant on page 16 argues: “Applicant has amended claims 1, 9, and 17 with respect to the usage of identity (even though it is clear from context and as noted above that is sufficient).”
In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn.
Applicant on page 17 argues: ‘Applicant is not amending "the execution" circuitry as that is clearly definite.’
Applicant’s argument is unpersuasive.
Applicant on page 18 argues: ‘Applicant respectfully disagrees. The proposed modification is improper because it would render Wang's invention unsatisfactory for its intended purpose and directly contradicts Wang's explicit teachings. A fundamental premise of Wang is that conventional instructions for accessing Model Specific Registers (MSRs) require the use of general-purpose registers. Wang explicitly identifies this as a problem, noting that "accesses to the model specific register needs to be carried out through some general-purpose registers, which means that the current contents of the general-purpose registers need to be saved elsewhere" (Wang, paragraph [0004]). Wang explicitly disparages this requirement as a "time-wasting approach due to the content backup and restoration operations."’ However, Examiner submits that the proposed modification is not improper because it does not render Wang's invention unsatisfactory for its intended purpose and does not directly contradict Wang's explicit teachings. The proposed modification does not revert Wang back to requiring use of general-purpose registers to access Model Specific Registers. Rather, the proposed modification merely provides increased capability and functionality via supporting storing accessed data to a destination (but not requiring that all accesses to Model Specific Registers for whatever purpose use general-purpose registers).
Applicant on page 18 argues: ‘To solve this exact problem, Wang introduces a specific target instruction (TAI) that directly accesses the MSR without using any general-purpose registers. Wang expressly states that with its invention, "it is no longer necessary to read and write the model specific register by means of accessing associated general-purpose registers... so as to avoid frequently switching values of those general-purpose registers" (Wang, paragraph [0058]). Wang repeatedly emphasizes that its target instruction executes "without backing up and restoring the contents of the general-purpose registers" (Wang, paragraphs [0062], [0068]).’
However, as noted above, the proposed modification does not revert Wang back to requiring use of general-purpose registers to access Model Specific Registers. Rather, the proposed modification merely provides increased capability and functionality via supporting storing accessed data to a destination (but not requiring that all accesses to Model Specific Registers for whatever purpose use general-purpose registers). Examiner notes that the overall combination’s support for storing accessed data to a destination does not necessitate that the previous value of the destination is first backed up and then later restored.
Applicant on page 18 argues: ‘Modifying Wang's TAI instruction to include a destination register operand to store the read MSR data, as the Examiner proposes based on Lee, would require the executing program to overwrite a general-purpose register. This would, in turn, force the program to back up and restore that register's contents. Consequently, this modification would directly reintroduce the very "time-wasting" backup and restoration operations that Wang's entire invention was explicitly designed to eliminate.’
However, Examiner submits that a write of MSR data to a destination register does not inherently require a back-up and restoration of that destination register’s contents. Wang discloses MSR access without needing to perform a back-up and restoration; modifying Wang to support the capability of writing MSR data to a destination register if desired by a programmer does not necessitate back-up and restoration of that destination register’s contents, in the same manner as a programmer choosing to implement a MOV R1, R2 instruction does not necessitate that R1 be backed up before the MOV and restored to R1 at some point in the future.
Applicant across pages 18-19 argues: “According to MPEP § 2143.01(V), a proposed modification is improper if it would render the prior art invention being modified unsatisfactory for its intended purpose. Furthermore, a combination is improper if the prior art teaches away from the proposed modification. Because incorporating Lee's destination register operand into Wang's instruction would destroy Wang's stated purpose of eliminating register backup and restore operations, a person of ordinary skill in the art would have been strongly discouraged from making the Examiner's proposed combination. Thus, there is no valid motivation to combine Wang and Lee in the manner claimed.”
However, incorporating Lee’s destination register operand into Wang’s instruction does not destroy Wang's stated purpose of eliminating register backup and restore operations, as the modification of Wang with the teaching of Lee does not entail register backup and restore operations.
Applicant on page 19 argues: “Because the proposed combination is improper and fails to teach or suggest all limitations of independent claim 1, the rejection of claim 1 is traversed. Similar arguments apply to independent claims 9 and 17, which recite corresponding limitations. Claims 2, 4-7, 10, 12-15, 18, and 20 depend from independent claims 1, 9, or 17, and are allowable at least by virtue of their dependence on an allowable base claim.”
Examiner’s responses to arguments with respect to claim 1 are likewise applicable to the arguments directed to the aforementioned further claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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