Prosecution Insights
Last updated: October 01, 2026
Application No. 18/193,295

INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING METAL POSTS THERMALLY COUPLING A DIE TO AN INTERPOSER SUBSTRATE FOR DISSIPATING THERMAL ENERGY OF THE DIE, AND RELATED FABRICATION METHODS

Non-Final OA §102§103
Filed
Mar 30, 2023
Examiner
GONZALES, VICENTE ROLANDO
Art Unit
2800
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
2 (Non-Final)
100%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
3 granted / 3 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
18 currently pending
Career history
28
Total Applications
across all art units

Statute-Specific Performance

§103
66.2%
+26.2% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 3 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed 12/17/2025 has been entered. Applicant’s amendments to the claims have overcome each drawing objection, specification objection, and claim objection previously set forth in the Non-Final Office Action. Claim Objections Claim 18 is objected to because of the following informalities: Claim 18, lines 1-2, “wherein the thermally coupling the first die to the at least one metal post adjacent to the first die, further comprises…” should read “wherein thermally coupling the first die to the at least one metal post adjacent to the first die further comprises…” Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 4-5, 7, 10-12, and 14-17 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Seok et al. (US Patent Pub 20220157757 A1). Regarding Claim 1, Seok teaches (in fig. 1) an integrated circuit (IC) package (10), comprising: a package substrate (Fig. 1, package substrate 100). an interposer substrate extending in a first direction, the interposer substrate comprising (see annotated figure below): a first metal layer comprising one or more first metal interconnects (First metal layer is the layer containing structure 422); and at least one metal post thermally coupled to a first metal interconnect of the one or more first metal interconnects in the interposer substrate (Fig. 1, metal post BP1 thermally coupled to a first metal interconnect (portion of 420 located in layer above 410). Paragraph 0026 of Applicant’s own specification teaches the term “thermally coupled” means that thermal energy is transferred from a heat source to a heat sink or an intermediate conduit of thermal energy to a heat sink. As best understood by the examiner, this means that a material that is connected to the die and can transfer heat generated from the die is thermally coupled. Therefore, BP1, which is formed of thermally conductive material copper (paragraph 0032) is thermally coupled to first metal interconnect 420 (portion of 420 located in layer above 410)); and a first die coupled to the package substrate, the first die disposed between the package substrate and the interposer substrate, the at least one metal post is adjacent to the first die and thermally coupled to the first die (Fig. 1, first die 200 (comprising 210, 220, 230, and 240) coupled to the package substrate. 200 is disposed between the package substrate 100 and the interposer substrate (see annotated figure below). The at least one metal post BP1 is adjacent to the first die 200 and thermally coupled (in contact with the first die 200 and formed of thermally conductive material copper) to the first die). PNG media_image1.png 823 1340 media_image1.png Greyscale Regarding Claim 2, Seok teaches the IC package of claim 1, wherein: the first die comprises a back side, wherein the at least one metal post is adjacent to and thermally coupled to the back side (Fig. 1, first die 200 comprises a back side 220, wherein the at least one metal post BP1 is adjacent to and thermally coupled to the backside (in contact with back side 220 and formed of thermally conductive material copper)). Regarding Claim 4, Seok teaches The IC package of claim 1, wherein the one or more first metal interconnects comprise a first metal plate, the first metal plate thermally coupled to the at least one metal post (Fig. 1, first metal plate 422 (portion of 422 represented in annotated figure above. Paragraph 0040 teaches 422 is formed of thermally conductive material copper) is thermally coupled to metal post BP1 through 422’ (paragraph 0040 teaches 422’ is also formed of copper)). Regarding Claim 5, Seok teaches The IC package of claim 1, wherein the interposer substrate further comprises: a second metal layer comprising one or more second metal interconnects (Fig. 1, layer below 410 (See annotated figure above) comprising second metal interconnects 422’); and an insulating layer disposed between the first metal layer and the second metal layer (Fig. 1, insulating layer 410 disposed between first metal layer (First metal layer is the layer containing structure 422’’) and second metal layer (layer below 410, see annotated figure below); the insulating layer comprising one or more thermal vias each coupling a second metal interconnect of the one or more second metal interconnects to the first metal interconnect of the one or more first metal interconnects (Fig. 1, insulating layer 410 comprises thermal vias (portion of 420 located in insulating layer 410. 420 is formed of copper (paragraph 0040), which conducts heat, therefore the portion of 420 located in insulating layer 410 is a thermal via) coupling second metal interconnect 422’ to the first metal interconnect (portion of 420 located in layer above 410)). Regarding Claim 7, Seok teaches the IC package of claim 2, wherein the at least one metal post contacts the back side of the first die (Fig. 1, metal post BP1 contacts the back side 220 of the first die 200). Regarding Claim 9, Seok teaches the IC package of claim 1, wherein the package substrate further comprises external interconnects disposed on a land side of the package substrate (Fig. 1, external interconnects 130). Regarding Claim 10, Seok teaches the IC package of claim 2, wherein the first die further comprises an active side electrically coupled to the package substrate (Fig. 1, first die 200 comprises an active side (portion of 200 wherein through via (240) vertically penetrates the first die 200) that is electrically coupled to the package substrate 100 by through vias 240). Regarding Claim 11, Seok teaches the IC package of claim 5, wherein the one or more first metal interconnects comprise a first metal plate and the one or more second metal interconnects comprise a second metal plate (Fig. 1, first metal interconnects (portion of 420 located in layer above 410) comprises a first metal plate (portion of first metal interconnect that extends in the direction parallel to the first die 200) and the one or more second metal interconnects 422’ comprise a second metal plate (portion of 422’ that extends in the direction parallel to the first die 200)). Regarding Claim 12, Seok teaches the IC package of claim 1, wherein the at least one metal post has a length between 30 micrometers (µm) and 100 µm, inclusively (Seok, paragraph 0032 teaches that the at least one metal post BP1 can have a length (referred to as thickness in Seok, but is the same parameter as length 152 in applicant’s drawings) of 100 µm, which is within the claimed length range). Regarding Claim 14, Seok teaches the IC package of claim 1, wherein the at least one metal post comprises a plurality of metal posts, wherein an area defined by the plurality of metal posts is at least equal to an area of a back side of the first die (Fig. 1, the at least one metal post comprises a plurality of metal posts (BP1 comprises all structures located within 310 located on top and covering back side 220 of die 200). As best understood by the examiner and based on fig. 1A of Applicant’s drawings, these structures define an area equal to an area of a back side of the first die 200). Regarding Claim 15, Seok teaches the IC package of claim 1, wherein the at least one metal post comprises a plurality of metal posts, wherein the IC package further comprises a molding compound disposed between the plurality of metal posts (Fig. 1, the at least one metal post comprises a plurality of metal posts (BP1 comprises all structures located within 310 located on top and covering back side 220 of die 200). Molding compound 310 is disposed between the plurality of posts). Regarding Claim 16, Seok teaches a method of fabricating an IC package, comprising: providing a package substrate (Fig. 1, package substrate 100); providing an interposer substrate extending in a first direction, the interposer substrate comprising a first metal layer (Fig. 1, see annotated figure below), the first metal layer comprising one or more first metal interconnects (Fig. 1, first metal layer (the first metal layer is the layer containing 422”)); providing at least one metal post thermally coupled to a first metal interconnect of the one or more first metal interconnects (Fig. 1, metal post BP1 thermally coupled to a first metal interconnect (portion of 420 located in layer above 410). Paragraph 0026 of Applicant’s own specification teaches the term “thermally coupled” means that thermal energy is transferred from a heat source to a heat sink or an intermediate conduit of thermal energy to a heat sink. As best understood by the examiner, this means that a material that is connected to the die and can transfer heat generated from the die is thermally coupled. Therefore, BP1, which is formed of thermally conductive material copper (paragraph 0032) is thermally coupled to first metal interconnect 420 (portion of 420 located in layer above 410) (see also annotated figure 2 below)); disposing a first die between the package substrate and the interposer substrate (Fig. 1, first die 200 (comprising 210, 220, 230, and 240) coupled to the package substrate. 200 is disposed between the package substrate 100 and the interposer substrate (see annotated figure below); coupling the first die to the package substrate (Fig. 1, the first die 200 is coupled to the package substrate 100 through structure 220, 122”, and interconnects located in layer above 100); PNG media_image1.png 823 1340 media_image1.png Greyscale and thermally coupling the first die to the at least one metal post adjacent to the first die (The at least one metal post BP1 is adjacent to the first die 200 and thermally coupled (in contact with the first die 200 and formed of thermally conductive material copper) to the first die). Regarding Claim 17, Seok teaches the method of claim 16, wherein the providing the interposer substrate, further comprises: forming one or more second metal interconnects in a second metal layer (Fig. 1, layer below 410 (See annotated figure above) comprising second metal interconnects 422’); forming an insulating layer between the first metal layer and the second metal layer (Fig. 1, insulating layer 410 disposed between first metal layer (layer containing 422”) and second metal layer (layer below 410, see annotated figure above)); and forming thermal vias in the insulating layer coupling the one or more second metal interconnects to the one or more first metal interconnects (Fig. 1, insulating layer 410 comprises thermal vias (portion of 420 located in insulating layer 410. 420 is formed of copper (paragraph 0040), which conducts heat, therefore the portion of 420 located in insulating layer 410 is a thermal via) coupling second metal interconnect 422’ to the first metal interconnect (portion of 420 located in layer above 410)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3, 6, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seok as applied to claims 1-2, 4-5, 7, 10-12, and 14-17 above, and further in view of Hsieh et al. (US Patent Pub 20230048302 A1). Regarding Claim 3, Seok teaches The IC package of claim 2. Seok fails to teach the IC package comprising a thermal interface material on the back side, wherein the at least one metal post is thermally coupled to the thermal interface material. However, Mallik teaches an IC package structure device comprising a thermal interface material on the back side, wherein the at least one metal post is thermally coupled to the thermal interface material (Hsieh, Fig. 1F teaches a thermal interface material 400A on the back side of first die 110 (middle die of 110), wherein the at least one metal post 430 (paragraph 0040 teaches 430 is formed comprises metal) is thermally coupled to the thermal interface material). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hsieh into the method of Seok by forming the package structure comprising a thermal interface material on the back side, wherein the at least one metal post is thermally coupled to the thermal interface material. The ordinary artisan would have been motivated to modify Seok in the manner set forth above for at least the purpose of enhancing the thermal coupling of the package device components (Hsieh, paragraph 0047). Regarding Claim 6, Seok in view of Hsieh teaches the IC package of claim 3, wherein the at least one metal post contacts the thermal interface material (Hsieh, Fig. 1F teaches the at least one metal post 430 contacts both 610 and 410, both of which are a part of the thermal interface material 400A). Regarding Claim 18, Seok teaches the method of claim 16. Seok fails to teach the method wherein thermally coupling the first die to the at least one metal post adjacent to the first die further comprises applying a thermal interface material on a back side of the first die. However, Hsieh teaches a method wherein thermally coupling the first die to the at least one metal post adjacent to the first die further comprises applying a thermal interface material on a back side of the first die (Hsieh, Fig. 1C and paragraph 0041 teaches the method further comprises applying a thermal interface material 430A on a back side of the first die (back side of 110). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hsieh into the method of Seok by forming the package structure method wherein the thermally coupling the first die to the at least one metal post adjacent to the first die further comprises applying a thermal interface material on a back side of the first die. The ordinary artisan would have been motivated to modify Seok in the manner set forth above for at least the purpose of enhancing the thermal coupling of the package device components (Hsieh, paragraph 0047). Regarding Claim 19, Seok teaches the method of claim 18 Seok fails to teach the method wherein the coupling the first die to the package substrate further comprises: positioning the at least one metal post to contact the thermal interface material. However, Hsieh teaches a method of making a package device wherein the coupling the first die to the package substrate further comprises: positioning the at least one metal post to contact the thermal interface material (Hsieh, Fig. 1F teaches the at least one metal post 430 contacts both 610 and 410, both of which are a part of the thermal interface material 400A). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hsieh into the method of Seok by forming the package structure method wherein the coupling the first die to the package substrate further comprises: positioning the at least one metal post to contact the thermal interface material. The ordinary artisan would have been motivated to modify Seok in the manner set forth above for at least the purpose of enhancing the thermal coupling of the package device components (Hsieh, paragraph 0047). Regarding Claim 20, Seok in view of Hsieh teaches the method of claim 18, wherein the coupling the first die to the package substrate, further comprises: positioning the at least one metal post to contact the back side of the first die (Seok, fig. 1 teaches the at least one metal post BP1 contacts the back side 220 of the first die 200). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seok as applied to claims 1-2, 4-5, 7, 10-12, and 14-17 above, and further in view of Shi et al. (US Patent Pub 20190318975 A1). Regarding Claim 13, Seok teaches the IC package of claim 1, wherein at least one metal post comprises a plurality of metal posts (Seok, Fig. 1, the at least one metal post comprises a plurality of metal posts (BP1 comprises all structures located within 310 located on top and covering back side 220 of die 200)). Seok fails to specifically teach the package wherein a pitch between each neighboring metal post of the plurality of metal posts is between 100 micrometers (µm) and 200 µm, inclusively. However, Shi teaches a package device wherein a pitch between each neighboring metal component of the plurality of metal components is between 100 micrometers (µm) and 200 µm (Shi, fig. 4 and paragraph 0041 teaches a pitch D14 between metal components 62 which ranges from 100 µm to 200 µm, matching the claimed pitch range). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Shi into the method of Seok by forming the package device wherein a pitch between each neighboring metal post of the plurality of metal posts is between 100 micrometers (µm) and 200 µm, inclusively. The ordinary artisan would have been motivated to modify Seok in the manner set forth above for at least the purpose of reducing manufacturing costs (Shi, paragraph 0041). Response to Arguments Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive. Regarding arguments pertaining to claim 1, 4, and 9, Applicant argues that Seok does not teach that the structures of Seok are not thermally coupled as claimed. However, this is not persuasive as paragraph 0026 of Applicant’s own specification teaches the term “thermally coupled” means that thermal energy is transferred from a heat source to a heat sink or an intermediate conduit of thermal energy to a heat sink. As best understood by the examiner, this means that a material that is connected to the die and can transfer heat generated from the die is thermally coupled. Therefore, the structures of Seok, which are formed of metals that can conduct heat, are thermally coupled as claimed. Applicant also argues that Seok does not teach or suggest “the first die comprises a back side, wherein the at least one metal post is adjacent to and thermally coupled to the back side… wherein the first die further comprises an active side electrically coupled to the package substrate.” However, this is not persuasive. As best understood by the examiner, the back side of the die is defined as the side of the die adjacent to and thermally coupled to the at least one metal post. There is insufficient structure provided in the claims such that the back side of Seok is not the side of the die labeled as 220 in the office action above. Further, the active side of Seok described in claim 10 above is electrically coupled to the package substrate. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.R.G./Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 30, 2023
Application Filed
Sep 19, 2025
Non-Final Rejection mailed — §102, §103
Dec 17, 2025
Response Filed
Sep 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740486
ELECTRONIC DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD OF MANUFACTURING THE SAME
2y 11m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 3 resolved cases by this examiner. Grant probability derived from career allowance rate.

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