CTFR 18/193,308 CTFR 88888 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment Regarding the amendment filed 12/11/2025: Claims 1-20 are pending. Response to Arguments Rejection Under 35 USC 103 Applicant's arguments regarding the rejection of claims 1-5 and 9-15 under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2012/0274348 A1, heretofore referred to as Shin) in view of Meyer et al (US 2019/0120903 A1, heretofore referred to as Meyer) have been fully considered and are not persuasive. Regarding claim 1, Applicant argues: “Amended claim 1 recites, inter alia, a first circuit coupled to a terminal; a second circuit coupled to the terminal; and a detector circuit coupled to first and second circuits and configurable to output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal." Shin and Meyer fail to teach or suggest at least these claim elements. Specifically, Shin discloses that a voltage driving unit (the alleged first and second circuits) is connected to the through via (the alleged terminal) to receive the input voltage, changes a level of the input voltage in response to a test control signal, and generates a test voltage. The determination unit compares the input voltage with the test voltage to outputs a resultant signal (the alleged fault signal). Shin, Abstract. But Shin does not disclose that the determination unit detects that the voltage driving unit sinks a current from or injects a current into the through via, and outputs a fault signal responsive to the detection. In contrast, claim 1 recites "detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal." For at least these reasons, Shin fails to teach the aforementioned elements of claim 1, and Meyer fails to cure the deficiencies of Shin. To support the § 103 rejection of claim 11, the Office alleges that pull-up driver 210 of Shin corresponds to the claimed first voltage regulator, and pull-down driver 220 of Shin corresponds to the claimed second voltage regulator. Office Action, p. 5. The Office also alleges that PU transistor 414 and PD transistor 416 of Abhishek correspond to the claimed first and second voltage regulators. Office Action, p. 8. Applicant respectfully disagrees, at least because both Shin and Abhishek are completely silent about "voltage regulator". For at least these reasons, Shin and Abhishek fail to teach the aforementioned elements of claims 11 and 16, and Meyer fails to cure the deficiencies of Shin.”. The Examiner respectfully disagrees, Shin teaches “a first circuit (Shin; Fig 2, Element 210 and Par 0025) coupled to a terminal (Shin; Fig 2, Element 100 and Par 0025; Shin teaches the driver is connected to a via to be able to transmit a signal) ; a second circuit coupled to the terminal (Shin; Fig 2, Element 220 and Par 0025) ; and a detector circuit coupled to first and second circuits (Shin; Fig 2, Element 300) and configurable to output a fault signal (Shin; Par 0024 and Par 0026; Shin teaches the driver signal from the terminal is compared with the expected output range) responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal (Shin; Figs 6-8 and Par 0041-0040; Shin teaches outputting a signal when the via is determined to have failed) ”. The Examiner interprets the pull up and pull down circuits as injecting and sinking a current to the determination unit 300 of Shin, which thereby makes its fault determination signal based on the injected or sunk current from the pull up or pull down drivers. Therefore the rejection stands. Applicant's arguments regarding the rejection of claims 16 and 19-20 under 35 U.S.C. 103 as obvious over Abhishek et al (US 2020/0191862 A1, heretofore referred to as Abhishek) in view of Meyer have been fully considered and are not persuasive. Regarding claim 16, Applicant argues: “The Office also alleges that PU transistor 414 and PD transistor 416 of Abhishek correspond to the claimed first and second voltage regulators. Office Action, p. 8. Applicant respectfully disagrees, at least because both Shin and Abhishek are completely silent about "voltage regulator". For at least these reasons, Shin and Abhishek fail to teach the aforementioned elements of claims 11 and 16, and Meyer fails to cure the deficiencies of Shin”. The Examiner respectfully disagrees, a pull-up circuit and pull-down circuit clearly regulate the voltage of the terminal they are connected to as that is their function. Therefore, the rejection stands. Specification 07-28 AIA The amendment filed 12/11/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Claim 1 recites “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal” The specification specifically states “ Accordingly, third reference current I.sub.ref_3 and a fourth reference current I.sub.ref_4 may be very small current values to compare with essentially 0 mirrored current and to assert both HiZ_down and HiZ_up signals if the mirrored current is found to be lower than third reference current I.sub.ref_3 and fourth reference current I.sub.ref_4. Additionally, a capacitance of the tested pin may be measured and, if the measured capacitance is found to be less than a threshold (e.g., a capacitance of 100 pF), Cpin is also asserted. According to some embodiments, the combination of each of HiZ_down, HiZ_up, and Cpin being asserted causes the Pin-float fault signal to be asserted to indicate that the voltage on pin input 302 is floating within a dead-band region (e.g., between the values of Vref_UP and Vref_DN). In some examples, the capacitance is measured and tested against a low threshold to prevent incorrectly asserting the pin-float fault signal on a capacitively loaded pin, which will also conduct no pin current in the dead-band region. ”, in paragraph [0033], with no mention of it being “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal”. Claim 3 further recites “a replica of the first current compare the replica of the first current with a first reference current to generate a first comparison signal; receive a replica of the second current; compare the replica of the second current with a second reference current to generate a second comparison signal; and provide the fault signal responsive to at least one of the first or second comparison signals.” with no mention of the current being a “replica” and only mentions the current is mirrored in Paragraphs [0017] and [0030-[0033] of the original specification. Claim 11 recites “a detector circuit coupled to the first and second voltage regulators and configurable to provide a fault signal responsive to at least one of a state of the first voltage regulator or a state of the second voltage regulator” The specification specifically states “ Accordingly, third reference current I.sub.ref_3 and a fourth reference current I.sub.ref_4 may be very small current values to compare with essentially 0 mirrored current and to assert both HiZ_down and HiZ_up signals if the mirrored current is found to be lower than third reference current I.sub.ref_3 and fourth reference current I.sub.ref_4. Additionally, a capacitance of the tested pin may be measured and, if the measured capacitance is found to be less than a threshold (e.g., a capacitance of 100 pF), Cpin is also asserted. According to some embodiments, the combination of each of HiZ_down, HiZ_up, and Cpin being asserted causes the Pin-float fault signal to be asserted to indicate that the voltage on pin input 302 is floating within a dead-band region (e.g., between the values of Vref_UP and Vref_DN). In some examples, the capacitance is measured and tested against a low threshold to prevent incorrectly asserting the pin-float fault signal on a capacitively loaded pin, which will also conduct no pin current in the dead-band region. ”, in paragraph [0033], with no mention of it being “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal” . Applicant is required to cancel the new matter in the reply to this Office Action. 07-44 AIA The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 1 recites ““output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal” The specification specifically states “ Accordingly, third reference current I.sub.ref_3 and a fourth reference current I.sub.ref_4 may be very small current values to compare with essentially 0 mirrored current and to assert both HiZ_down and HiZ_up signals if the mirrored current is found to be lower than third reference current I.sub.ref_3 and fourth reference current I.sub.ref_4. Additionally, a capacitance of the tested pin may be measured and, if the measured capacitance is found to be less than a threshold (e.g., a capacitance of 100 pF), Cpin is also asserted. According to some embodiments, the combination of each of HiZ_down, HiZ_up, and Cpin being asserted causes the Pin-float fault signal to be asserted to indicate that the voltage on pin input 302 is floating within a dead-band region (e.g., between the values of Vref_UP and Vref_DN). In some examples, the capacitance is measured and tested against a low threshold to prevent incorrectly asserting the pin-float fault signal on a capacitively loaded pin, which will also conduct no pin current in the dead-band region. ”, in paragraph [0033], with no mention of it being “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal” . Claim 3 further recites “a replica of the first current compare the replica of the first current with a first reference current to generate a first comparison signal; receive a replica of the second current; compare the replica of the second current with a second reference current to generate a second comparison signal; and provide the fault signal responsive to at least one of the first or second comparison signals.” with no mention of the current being a “replica” and only mentions the current is mirrored in Paragraphs [0017] and [0030-[0033] of the original specification. Claim 11 recites “a detector circuit coupled to the first and second voltage regulators and configurable to provide a fault signal responsive to at least one of a state of the first voltage regulator or a state of the second voltage regulator” The specification specifically states “ Accordingly, third reference current I.sub.ref_3 and a fourth reference current I.sub.ref_4 may be very small current values to compare with essentially 0 mirrored current and to assert both HiZ_down and HiZ_up signals if the mirrored current is found to be lower than third reference current I.sub.ref_3 and fourth reference current I.sub.ref_4. Additionally, a capacitance of the tested pin may be measured and, if the measured capacitance is found to be less than a threshold (e.g., a capacitance of 100 pF), Cpin is also asserted. According to some embodiments, the combination of each of HiZ_down, HiZ_up, and Cpin being asserted causes the Pin-float fault signal to be asserted to indicate that the voltage on pin input 302 is floating within a dead-band region (e.g., between the values of Vref_UP and Vref_DN). In some examples, the capacitance is measured and tested against a low threshold to prevent incorrectly asserting the pin-float fault signal on a capacitively loaded pin, which will also conduct no pin current in the dead-band region. ”, in paragraph [0033], with no mention of it being “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal”. Applicant is required to cancel the new matter in the reply to this Office Action . Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 AIA Claim s 1-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal” The specification specifically states “ Accordingly, third reference current I.sub.ref_3 and a fourth reference current I.sub.ref_4 may be very small current values to compare with essentially 0 mirrored current and to assert both HiZ_down and HiZ_up signals if the mirrored current is found to be lower than third reference current I.sub.ref_3 and fourth reference current I.sub.ref_4. Additionally, a capacitance of the tested pin may be measured and, if the measured capacitance is found to be less than a threshold (e.g., a capacitance of 100 pF), Cpin is also asserted. According to some embodiments, the combination of each of HiZ_down, HiZ_up, and Cpin being asserted causes the Pin-float fault signal to be asserted to indicate that the voltage on pin input 302 is floating within a dead-band region (e.g., between the values of Vref_UP and Vref_DN). In some examples, the capacitance is measured and tested against a low threshold to prevent incorrectly asserting the pin-float fault signal on a capacitively loaded pin, which will also conduct no pin current in the dead-band region. ”, in paragraph [0033], with no mention of it being “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal”. Claim 3 further recites “a replica of the first current compare the replica of the first current with a first reference current to generate a first comparison signal; receive a replica of the second current; compare the replica of the second current with a second reference current to generate a second comparison signal; and provide the fault signal responsive to at least one of the first or second comparison signals.” with no mention of the current being a “replica” and only mentions the current is mirrored in Paragraphs [0017] and [0030-[0033] of the original specification. Claims 2-10 are rejected for depending on rejected base claim 1. Claim 11 recites “a detector circuit coupled to the first and second voltage regulators and configurable to provide a fault signal responsive to at least one of a state of the first voltage regulator or a state of the second voltage regulator” The specification specifically states “ Accordingly, third reference current I.sub.ref_3 and a fourth reference current I.sub.ref_4 may be very small current values to compare with essentially 0 mirrored current and to assert both HiZ_down and HiZ_up signals if the mirrored current is found to be lower than third reference current I.sub.ref_3 and fourth reference current I.sub.ref_4. Additionally, a capacitance of the tested pin may be measured and, if the measured capacitance is found to be less than a threshold (e.g., a capacitance of 100 pF), Cpin is also asserted. According to some embodiments, the combination of each of HiZ_down, HiZ_up, and Cpin being asserted causes the Pin-float fault signal to be asserted to indicate that the voltage on pin input 302 is floating within a dead-band region (e.g., between the values of Vref_UP and Vref_DN). In some examples, the capacitance is measured and tested against a low threshold to prevent incorrectly asserting the pin-float fault signal on a capacitively loaded pin, which will also conduct no pin current in the dead-band region. ”, in paragraph [0033], with no mention of it being “output a fault signal responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal”. Claims 12-15 are rejected for depending on rejected base claim 11 . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 4, 11-12, and 15 are rejected under 35 U.S.C. 102( a)(1) and 102(a)(2 ) as being anticipated by Shin et al (US 2012/0274348 A1, heretofore referred to as Shin) . Regarding claim 1 , Shin teaches an apparatus (Shin; Fig 2, Element 1 and Par 0023) , comprising: a first circuit (Shin; Fig 2, Element 210 and Par 0025) coupled to a terminal (Shin; Fig 2, Element 100 and Par 0025; Shin teaches the driver is connected to a via to be able to transmit a signal) ; a second circuit coupled to the terminal (Shin; Fig 2, Element 220 and Par 0025) ; and a detector circuit coupled to first and second circuits (Shin; Fig 2, Element 300) and configurable to output a fault signal (Shin; Par 0024 and Par 0026; Shin teaches the driver signal from the terminal is compared with the expected output range) responsive to at least one of: detecting that the first circuit injects a first current to the terminal, or detecting the second circuit sinks a second current from the terminal (Shin; Figs 6-8 and Par 0041-0040; Shin teaches outputting a signal when the via is determined to have failed and further the pull up and pull down circuits are injecting and sinking a current to the determination unit 300, which thereby makes its fault determination signal based on the injected or sunk current from the pull up or pull down drivers) . Regarding claim 2 , Shin teaches the apparatus of claim 1. Shin further teaches wherein the first circuit includes a first transistor coupled to the terminal (Shin; Fig 3, Element P1 and Par 0030) , and the second driver circuit includes a second transistor coupled to the terminal (Shin; Fig 3, Element N1 and Par 0030) . Regarding claim 4 , Shin teaches the apparatus of claim 1. Shin further teaches wherein the terminal is a first terminal (Shin; Fig 9, Element 100a and Par 0046) and the apparatus further comprises a second terminal adjacent to the first terminal (Shin; Fig 9, Element 100b and Par 0046) , and wherein the fault signal is indicative of a short-circuit between the first terminal and the second terminal (Shin; Par 0047; Shin teaches that the fault signal can occur when the two vias are connected through a bump connection between chips) . Regarding claim 11 , Shin teaches an integrated circuit (Shin; Fig 2 and Par 0023) , comprising: a terminal (Shin; Fig 2, Element 100 and Par 0025; Shin teaches the driver is connected to a via to be able to transmit a signal) ; and a first voltage regulator coupled to the terminal (Shin; Fig 2, Element 210 and Par 0025) , a second voltage regulator coupled to the terminal (Shin; Fig 2, Element 220 and Par 0025) , and a detector circuit (Shin; Fig 2, Element 300) coupled to the first and second voltage regulators and configurable to provide a fault signal (Shin; Par 0024 and Par 0026; Shin teaches the driver signal from the terminal is compared with the expected output range) responsive to at least one of a state of the first voltage regulator or a state of the second voltage regulator (Shin; Figs 6-8 and Par 0041-0040; Shin teaches outputting a signal when the via is determined to have failed and further the pull up and pull down circuits are injecting and sinking a current to the determination unit 300, which thereby makes its fault determination signal based on the injected or sunk current from the pull up or pull down drivers) . Regarding claim 12 , Shin teaches the integrated circuit of claim 11. Shin further teaches wherein the first voltage regulator is a series voltage regulator (Shin; Fig 2, Element 220 and Par 0025; Shin teaches the first voltage regulator is series connected to the voltage source VDD) , and the second voltage regulator is a shunt voltage regulator (Shin; Fig 2, Element 220 and Par 0025; Shin teaches that the second voltage regulator shunts the signal to a VSS ground voltage) . Regarding claim 15 , the combination of Shin and Meyer teaches the integrated circuit of claim 11. Shin further teaches further comprising: a fault response block (Shin; Fig 2, Element 500 and Par 0028; Shin teaches an output unit) configurable to receive the at least one fault signal and determine a fault response responsive to receiving the at least one fault signal (Shin; Fig 2, Element 500 and Par 0028; Shin teaches the output unit determines the fault response) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 5, 9-10, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2012/0274348 A1, heretofore referred to as Shin) in view of Meyer et al (US 2019/0120903 A1, heretofore referred to as Meyer) . Regarding claim 5 , Shin teaches the apparatus of claim 4. Shin is silent on wherein the detector circuit is configurable to provide the fault signal responsive to a comparison between a first current on the first terminal during a first time period and a second current on the first terminal during a second adjacent time period, wherein a voltage applied to one or more driver circuits coupled to the second terminal changes between the first time period and the adjacent second time period. Meyer teaches wherein the detector circuit is configurable to provide the fault signal responsive to a comparison (Meyer; Par 0038; Meyer teaches the output is a logic high or low depending on the comparison) between a first current on the first terminal during a first time period (Meyer; Fig 6, Element 604 and Par 0041; Meyer teaches a first current at a first time) and a second current on the first terminal during a second adjacent time period (Meyer; Fig 6, Element 606 and Par 0041; Meyer teaches a second current at a second time) , wherein a voltage applied to one or more driver circuits coupled to the second terminal changes between the first time period and the adjacent second time period (Meyer; Fig 6, Element 612 and Par 0041; Meyer teaches a signal 612 that causes the current to change) . Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the system of Shin with the fault signal of Meyer in order to identify a wider range of faults in the system (Meyer; Par 0003). Regarding claim 9 , Shin teaches the apparatus of claim 1. Shin is silent on wherein the detector circuit is configurable to: provide the fault signal indicating a first type of fault responsive to detecting that the first circuit injects a first current to the terminal; and provide the fault signal indicating a second type of fault responsive to detecting that the second circuit sinks a second current from the terminal driver circuit. Meyer further teaches wherein the detector circuit is configurable (Meyer; Fig 5, Elements 508, 510, and 512 and Par 0039; Meyer teaches at least three comparator circuits) to: provide the fault signal indicating a first type of fault responsive to detecting that the first circuit injects a first current to the terminal (Meyer; Par 0029; Meyer teaches mirroring the current); and provide the fault signal indicating a second type of fault responsive to detecting that the second circuit sinks a second current from the terminal driver circuit (Meyer; Par 0038; Meyer teaches the output is a logic high or low depending on the comparisons, marking different types of faults) . Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the system of Shin with the fault signal of Meyer in order to identify a wider range of faults in the system (Meyer; Par 0003). Regarding claim 10 , the combination of Shin and Meyer teaches the apparatus of claim 9. Shin further teaches wherein the first type of fault is a grounded terminal fault, wherein the second type of fault is a a shorted to a supply terminal fault (Shin; Fig 4C, Fig 4D, and Par 0034; Shin teaches it may be a shorted fault either to ground or other circuit) . Regarding claim 13 , Shin teaches the integrated circuit of claim 11. Shin is silent on further comprising a plurality of fault comparison blocks, each of the fault comparison blocks configurable to receive a current from the first voltage regulator and/or the second voltage regulator, and wherein each of the fault comparison blocks is configurable to output a different fault signal associated with a different type of fault. Meyer further teaches further comprising a plurality of fault comparison blocks (Meyer; Fig 5, Elements 508, 510, and 512 and Par 0039; Meyer teaches at least three comparator circuits) , each of the fault comparison blocks configurable to receive a current from the first voltage regulator and/or the second voltage regulator (Meyer; Par 0029; Meyer teaches mirroring the current) , and wherein each of the fault comparison blocks is configurable to output a different fault signal associated with a different type of fault (Meyer; Par 0038; Meyer teaches the output is a logic high or low depending on the comparisons, marking different types of faults) . Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the system of Shin with the fault signal of Meyer in order to identify a wider range of faults in the system (Meyer; Par 0003). Regarding claim 14 , the combination of Shin and Meyer teaches the integrated circuit of claim 13. Shin further teaches wherein at least one of the fault comparison blocks is configurable to compare the received mirrored current (Meyer; Par 0029; Meyer teaches mirroring the current) to a reference current (Meyer; Par 0034-35; Meyer teaches the mirrored current is compared against a reference current source) and output the corresponding fault signal responsive to the comparison (Meyer; Par 0038; Meyer teaches the output is a logic high or low depending on the comparison) . Claims 16 and 19-20 are rejected under 35 U.S.C. 103 as obvious over Abhishek et al (US 2020/0191862 A1, heretofore referred to as Abhishek) in view of Meyer. Regarding claim 16 , Abhishek teaches an integrated circuit (Abhishek; Fig 1, Element 100 and Par 0011) , comprising: a plurality of pins (Abhishek; Fig 1, Elements 120-128 and Par 0012) ; a multiplexer having inputs coupled to corresponding pins of the plurality of pins (Abhishek; Fig 1, Element 110 and Par 0011) ; and a pin fault detector (Abhishek; Fig 4, Element 400 and Par 0011) having a pin input coupled to an output of the multiplexer (Abhishek; Fig 4, Element DOUT and Par 0025) and configurable to output at least one fault signal associated with one pin of the plurality of pins as selected by the multiplexer (Abhishek; Par 0028) , wherein the pin fault detector includes: a first voltage regulator coupled to the pin input (Abhishek; Fig 4, Element PU and Par 0028) , a second voltage regulator coupled to the pin input (Abhishek; Fig 4, Element PD and Par 0028) , and at least one fault comparison block configurable to receive a signal from the first voltage regulator and/or the second voltage regulator (Abhishek; Fig 4, Element 428 and Par 0028) , and output fault signal responsive to the signal (Abhishek; Par 0028; Abhishek teaches the signal is compared to a reference signal to determine if there is a fault) . Meyer teaches the signal is a current (Meyer; Par 0029 and Par 0034-0036; Meyer teaches mirroring a current for fault comparison and that the driver current for testing a driver is monitored to determine when a fault occurs) . Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the system of Shin with the driver current of Meyer in order to identify a wider range of faults in the system (Meyer; Par 0003). Regarding claim 19 , the combination of Abhishek and Meyer teaches the integrated circuit of claim 16. Abhishek further teaches wherein the integrated circuit includes a plurality of fault comparison blocks (Meyer; Fig 5, Elements 508, 510, and 512 and Par 0039; Meyer teaches at least three comparator circuits) , each of the fault comparison blocks configurable to receive a current from the first voltage regulator and/or the second voltage regulator (Meyer; Par 0029; Meyer teaches mirroring the current) , and wherein each of the fault comparison blocks is configurable to output a different fault signal associated with a different type of fault (Meyer; Par 0038; Meyer teaches the output is a logic high or low depending on the comparisons, marking different types of faults) . Regarding claim 20 , Abhishek teaches the integrated circuit of claim 16. Abhishek further teaches further comprising a fault response block configurable to receive the at least one fault signal and determine a fault response responsive to receiving the at least one fault signal (Abhishek; Par 0029; Abhishek teaches the fault may be determined by the portion of the range of the reference signal the fault is in) . Comments The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claims 3 and 6-8. Therefore, no prior art rejection for claim 3 is presented in this action. However, claims 3 and 6-8 are rejected under 35 U.S.C. 112. It is suggested to contact the Examiner for any clarification with respect the rejection . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 17, the prior art of record alone or in combination does not teach “wherein the plurality of pins is a first plurality of pins, the multiplexer is a first multiplexer, and the pin fault detector is a first pin fault detector, the integrated circuit further comprising: a second plurality of pins; a second multiplexer having inputs coupled to corresponding pins of the second plurality of pins; and a second pin fault detector having a pin input coupled to an output of the second multiplexer and configurable to output at least one fault signal associated with one pin of the plurality of second pins as selected by the second multiplexer”. Claim 18 is objected to for depending from objected claim 17. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. -Sakurai et al teaches a power supply circuit with fault detection. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S CLARKE whose telephone number is (571)270-3792. The examiner can normally be reached M-F 8am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADAM S CLARKE/Examiner, Art Unit 2858 /JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858 Application/Control Number: 18/193,308 Page 2 Art Unit: 2858 Application/Control Number: 18/193,308 Page 3 Art Unit: 2858 Application/Control Number: 18/193,308 Page 4 Art Unit: 2858 Application/Control Number: 18/193,308 Page 5 Art Unit: 2858 Application/Control Number: 18/193,308 Page 6 Art Unit: 2858 Application/Control Number: 18/193,308 Page 7 Art Unit: 2858 Application/Control Number: 18/193,308 Page 8 Art Unit: 2858 Application/Control Number: 18/193,308 Page 9 Art Unit: 2858 Application/Control Number: 18/193,308 Page 10 Art Unit: 2858 Application/Control Number: 18/193,308 Page 11 Art Unit: 2858 Application/Control Number: 18/193,308 Page 12 Art Unit: 2858 Application/Control Number: 18/193,308 Page 13 Art Unit: 2858 Application/Control Number: 18/193,308 Page 14 Art Unit: 2858 Application/Control Number: 18/193,308 Page 15 Art Unit: 2858 Application/Control Number: 18/193,308 Page 16 Art Unit: 2858 Application/Control Number: 18/193,308 Page 17 Art Unit: 2858 Application/Control Number: 18/193,308 Page 18 Art Unit: 2858 Application/Control Number: 18/193,308 Page 19 Art Unit: 2858
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