Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Analysis for Independent Claims (Dependent Claim Analysis will follow)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao (Liao, US 2015/0357422).
In regards to independent claim 1, Liao teaches an integrated circuit, comprising:
a transistor (Liao, FET, [0005]) having an insulator layer (Liao, Fig. 1F figure inserted below, Item 340, [0032]) over a substrate that includes gallium nitride (GaN) (Liao, Item 310, Fig. 1F, [0030], GaN and AlGaN);
first and second openings in the insulator layer that respectively define a drain region and a source region of the transistor (Liao, Fig. 1F, Item 344 drain hole, 342 source hole);
a gate electrode extending into the insulator layer between the source region and the drain region (Liao, Fig. 1F, Item 330 gate electrode);
a metal layer that includes a drain via and a source via, the drain via extending through the first opening to the drain region, and the source via extending through the second opening to the source region (Liao, Fig. 1F, Item 360 drain electrode, Item 350 source electrode); and
a source field plate in the metal layer (Liao, Fig. 1F Item 370, field plate, [0036]), the source field plate extending over the gate electrode and providing a contiguous electrically conductive path to the source region (Liao, Fig. 1F Item 374, extending region, [0036]).
In regards to independent claim 7, Liao teaches a transistor, comprising:
an insulator layer (Liao, Fig. 1F, Item 340, [0032]) over a substrate including a semiconductor layer comprising aluminum, gallium and nitrogen (Liao, Item 310, Fig. 1F, [0030], GaN and AlGaN);
a first opening extending through the insulator layer and into the semiconductor layer defining a drain region (Liao, Fig. 1F, Item 344 drain hole);
a second opening extending through the insulator layer and into the semiconductor layer defining a source region (Liao, Fig. 1F, Item 342 source hole);
a gate electrode extending into the insulator layer between the source region and the drain region (Liao, Fig. 1F, Item 330 gate electrode); and
a metal layer including noncontiguous first and second portions, the first portion extending into the first opening and touching the semiconductor layer (Liao, Fig. 1F Item 360, drain electrode) and the second portion extending from the semiconductor layer over the gate electrode to form a source field plate (Liao, Fig. 1F Item 370, field plate, 374, extending region, [0036]).
In regards to independent claim 14, Liao teaches a method comprising:
forming a first opening extending through a first insulating layer to a substrate including gallium nitride (GaN), the first opening defining a drain of a transistor (Liao, Fig. 1E, [0033], Fig. 1F, Item 344 drain hole);
forming a second opening extending through the first insulating layer to the substrate, the second opening defining a source the transistor (Liao, Fig. 1E, [0033], Fig. 1F, Item 342 source hole);
forming a gate of the transistor extending into the first insulating layer (Liao, Fig. 1C, [0031], Fig. 1F, Item 330 gate electrode);
forming a first metal layer over the first insulating layer, the first metal layer having (Liao, Fig. 1F, [0034]):
a first via extending through the first opening to the substrate (Liao, Fig. 1F Item 360, drain electrode);
a second via extending through the second opening to the substrate (Liao, Fig. 1F Item 350, source electrode); and
a first source field plate over the gate, the first source field plate and the second via being contiguous portions of the first metal layer (Liao, Fig. 1F Item 370, field plate, 374, extending region, [0036]).
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Claim Analysis for Dependent Claims
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, 3, 5, 6, 15 is/are rejected under 35 U.S.C. 103 as being obvious over Liao in view of Lee et al. (hereinafter Lee, US 2023/0101543).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
In regards to dependent claim 2, Liao teaches wherein the metal layer is a first metal layer and the source field plate is a first source field plate. Liao fails to teach fails to explicitly teach further comprising a second source field plate in a second metal layer located over the first source field plate (Liao, Fig. 1F, [0034]).
Lee teaches further comprising a second source field plate in a second metal layer located over the first source field plate (Lee, 218).
It would have been obvious to one of ordinary skill in the art, having the teachings of Liao and Lee before him before the effective filing date of the claimed invention, to modify the source field plate taught by Liao to include a second source field plate of Lee in order to obtain a multiple source field plate transistor. One would have been motivated to make such a combination because it can better mitigate the deleterious effects of internal electric fields.
In regards to dependent claim 3, Liao fails to explicitly teach wherein the second metal layer includes a second via over the source via, the second via and the second source field plate contiguously connected. Lee teaches wherein the second metal layer includes a second via over the source via, the second via and the second source field plate contiguously connected (Lee, 218). It would have been obvious to one of ordinary skill in the art, having the teachings of Liao and Lee before him before the effective filing date of the claimed invention, to modify the source field plate taught by Liao to include a second source field plate of Lee in order to obtain a multiple source field plate transistor. One would have been motivated to make such a combination because it can better mitigate the deleterious effects of internal electric fields.
In regards to dependent claim 5, Liao fails to explicitly teach an insulator layer between the first and second metal layers, the insulator layer having a substantially planar surface in contact with the second metal layer. Lee teaches an insulator layer between the first and second metal layers, the insulator layer having a substantially planar surface in contact with the second metal layer (Lee, [0056]). It would have been obvious to one of ordinary skill in the art, having the teachings of Liao and Lee before him before the effective filing date of the claimed invention, to modify the source field plate taught by Liao to include a second source field plate of Lee in order to obtain a multiple source field plate transistor. One would have been motivated to make such a combination because it can better mitigate the deleterious effects of internal electric fields.
In regards to dependent claim 6, Liao fails to explicitly teach a silicon nitride layer between the first and second metal layers. Lee teaches a silicon nitride layer between the first and second metal layers (Lee, [0037]). It would have been obvious to one of ordinary skill in the art, having the teachings of Liao and Lee before him before the effective filing date of the claimed invention, to modify the source field plate taught by Liao to include a second source field plate of Lee in order to obtain a multiple source field plate transistor. One would have been motivated to make such a combination because it can better mitigate the deleterious effects of internal electric fields.
In regards to dependent claim 15, Liao fails to explicitly teach a second metal layer over the first metal layer, the second metal layer having a second source field plate over the gate, wherein forming the second metal layer includes depositing the second metal layer on a planarized surface of an insulator layer. Lee teaches forming a second metal layer over the first metal layer, the second metal layer having a second source field plate over the gate, wherein forming the second metal layer includes depositing the second metal layer on a planarized surface of an insulator layer (Lee, 218). It would have been obvious to one of ordinary skill in the art, having the teachings of Liao and Lee before him before the effective filing date of the claimed invention, to modify the source field plate taught by Liao to include a second source field plate of Lee in order to obtain a multiple source field plate transistor. One would have been motivated to make such a combination because it can better mitigate the deleterious effects of internal electric fields.
Allowable Subject Matter
Claims 4, 8-13, 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812