DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 5/18/2026. Claims 1-20 are pending and have been examined. Claims 7 and 16 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “An apparatus” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…a multiplication, a round, addition and/or subtraction, a round” which describe a process that under its broadest reasonable interpretation encompasses mathematical calculations. That is other than reciting generic computing components (e.g. decoder circuitry and execution circuitry to execute instructions) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses performing multiplication of values, followed by rounding of multiplication results, followed by addition and/or subtraction of values with the rounded multiplication results, and finally the addition/subtracted results are rounded to generate a final result (see paragraph [0023] of applicant’s specification), thus the limitation encompasses mathematical calculations (MPEP 2106.04(a)(2)(I)(C)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include at least having one or more fields for an opcode and location information for three packed data source operands, wherein the opcode is to indicate execution circuitry is to perform, per packed data element position… using the three packed data source operands…and execution circuitry to execute the decoded instance of the single instruction according to the opcode.
and storage into a corresponding packed data element location of an identified destination location
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)); the use of packed data operands can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector processing) (MPEP 2106.05(h))) and (b) recites insignificant extra-solution activity (i.e. data outputting) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); the use of packed data operands can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector processing) (MPEP 2106.05(h))). Furthermore, using computer components such as decoder and execution circuitry can be viewed as well-understood, routine and conventional because it is well-known in computer architecture to process instructions by using a pipeline which include decodes and execute instructions (See NPL reference “Computer Architecture A Quantitative Approach”, pages C-34 to C-35 and 232). While, (b) recites insignificant extra-solution activity of data outputting (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, dependent upon claim 1, further recites “…wherein one of the three source operands is the identified destination location”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, dependent upon claim 1 further recites “…wherein the execution circuitry further comprises broadcast circuitry to broadcast an element of one of the source operands to be operated” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Further, the limitation states “broadcast an element” which can be the insignificant extra-solution activity of data gathering and/or outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4, dependent upon claim 1, further recites “…wherein at least one of the source operands is memory”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, dependent upon claim 1, further recites “…wherein the rounds are to be performed by rounding circuitry”, which ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, dependent upon claim 1 further recites “…wherein the instance of the single instruction is to further include one or more fields to identify a writemask, wherein the execution circuitry is to use the identified writemask to determine which packed data element locations of the identified destination location to store to” which recites further abstract ideas including mental processes (e.g. the claimed determining). The further additional limitations tie the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)); also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)).Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, dependent upon claim 1 further recites “…wherein the rounds are one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero” which recites further abstract ideas including mathematical concepts. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 8, dependent upon claim 1 further recites “…wherein odd packed data element positions are to be subjected to addition and even packed data elements positions are to be subjected to subtraction” which recites further abstract ideas including mathematical concepts. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 9, dependent upon claim 1 further recites “…wherein even packed data element positions are to be subjected to addition and odd packed data elements positions are to be subjected to subtraction” which recites further abstract ideas including mathematical concepts. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claims 10 and 19 are similarly rejected on the same basis as claim 1 above.
Claims 11-18 and 20 are similarly rejected on the same basis as claims 11-18 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 10 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Samudrala, PGPUB No. 2017/0039033.
In regards to claim 1, Samudrala discloses An apparatus (See Fig. 4B: processor core (element 490)) comprising: decoder circuitry to decode an instance of a single instruction ([0095 and 0102] decoder decodes instructions) the instance of the single instruction to include at least having one or more fields for an opcode and location information for three packed data source operands ([0092 and 0095-0096]: wherein a double rounded combined floating-point and add operation includes fields for opcode and location information for three packed source operands Vmm2-Vmm4 (opcode VFCMADD) (See Figs. 3G-H)) wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, a round, using the three packed data source operands and storage into a corresponding packed data element location of an identified destination location ([0096 and 0138]: wherein a double rounded combined floating-point and add operation (opcode VFCMADD) is executed using source operands Vmm2, Vmm3, Vmm4 by multiplying elements of Vmm2 by Vmm3, and then rounding and adding the products to elements of Vmm4, then rounds and stores results in Vmm1) and execution circuitry to execute the decoded instance of the single instruction according to the opcode. ([0103 and 0138]: wherein execution circuitry executes the double rounded combined floating-point and add operation according to the opcode)
Claim 10 is similarly rejected on the same basis as claim 1 above as claim 10 is the method corresponding to the apparatus of claim 1 above. (Note claim 10 includes additional limitations stating “…translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture”. However, Samudrala discloses “…translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture”. ([0135-0137 and Fig. 13]))
In regards to claim 5, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the rounds are to be performed by rounding circuitry. ([0138-0140 and 0141]: wherein the rounds are performed by rounding circuitry (See Figs. 14A-B))
Claim 14 is similarly rejected on the same basis as claim 5 above as claim 14 is the method corresponding to the apparatus of claim 5 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 6-9, 11, 13 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Samudrala, and further in view of NPL reference, “Intel Architecture Instruction Set Extensions Programming Reference”, hereby referred to as Intel.
In regards to claim 2, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein one of the three source operands is the identified destination location.
Intel discloses wherein one of the three source operands is the identified destination location. (see pages 5-256 to 5-257: wherein a first source operand xmm1 is the identified destination location)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector instruction of Samudrala, which uses three source operands and a separate destination operand location, to use one of the source operands as a destination location as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a source operand as a identifier for a source operand location and a destination operand location as taught in Intel) for another (using separate source and destination operand locations as taught in Samudrala) to yield predictable results (vector instructions which use an operand identifier to identify a register as both a source and destination operand) (MPEP 2143, Example B). Furthermore, it would have been obvious because using a single register as both a source and destination register can be used for the benefit of saving register file space.
Claim 11 is similarly rejected on the same basis as claim 2 above as claim 11 is the method corresponding to the apparatus of claim 2 above.
In regards to claim 4, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein at least one of the source operands is memory.
Intel discloses wherein at least one of the source operands is memory. (see pages 5-256 to 5-257: wherein a third source operand is a 512/256/128-bit memory location)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector instruction of Samudrala, which use three vector registers as source operands, to use at least one memory source operand as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a memory source operand to perform vector instructions as taught in Intel) for another (using register source operand as Samudrala) to yield predictable results (vector instructions which use at least one memory source operand) (MPEP 2143, Example B). Furthermore, it would have been obvious because using memory source operands can be used for the benefit of saving register file space.
Claim 13 is similarly rejected on the same basis as claim 4 above as claim 13 is the method corresponding to the apparatus of claim 4 above.
In regards to claim 6, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein the instance of the single instruction is to further include one or more fields to identify a writemask, wherein the execution circuitry is to use the identified writemask to determine which packed data element locations of the identified destination location to store to.
Intel discloses wherein the instance of the single instruction is to further include one or more fields to identify a writemask, wherein the execution circuitry is to use the identified writemask to determine which packed data element locations of the identified destination location to store to. (pages 5-256 to 5-257: wherein a destination location is conditionally updated based on a writemask (k1) indicated by a single instruction)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector instruction of Samudrala, to include a writemask operand as the vector instruction of Intel. It would have been obvious to one of ordinary skill in the art because using mask in vector instructions to conditionally update destination locations can be used for the benefit of added programming flexibility and reducing instruction overhead/improving execution speed (e.g. by avoiding the need to explicitly read and write back the unchanged parts of a vector).
Claim 15 is similarly rejected on the same basis as claim 6 above as claim 15 is the method corresponding to the apparatus of claim 6 above.
In regards to claim 7, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein the rounds are one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero.
Intel discloses wherein the rounds are one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero. (pages 2-8 to 2-9 and 5-256 to 5-258)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the rounding in the vector instruction of Samudrala, to include one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero as taught in Intel) for another (using generic rounding as disclosed in Samudrala) to yield predictable results (vector instructions which perform rounds using one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero) (MPEP 2143, Example B).
Claim 16 is similarly rejected on the same basis as claim 7 above as claim 16 is the method corresponding to the apparatus of claim 7 above.
In regards to claim 8, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein odd packed data element positions are to be subjected to addition and even packed data elements positions are to be subjected to subtraction. Samudrala does generally disclose fusing and performing fused operations including multiplies, additions and subtractions ([0038 and 0141]), however Samudrala has not explicitly disclosed performing fused multiply-alternating add/subtract operations.
Intel discloses wherein odd packed data element positions are to be subjected to addition and even packed data elements positions are to be subjected to subtraction. (see pages 5-256 to 5-257: wherein odd packed data elements are added and even packed data elements are subjected)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector double rounded fused multiply and add or subtract instructions of Samudrala, to perform fused multiply-alternating add/subtract operations as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a vector instruction to perform fused multiply-alternating add/subtract operations as taught in Intel) for another (using a vector instruction to perform fused multiply and add or subtract operations as Samudrala) to yield predictable results (vector instructions which perform fused multiply-alternating add/subtract operations) (MPEP 2143, Example B). Furthermore, it would have been obvious because it would add programming flexibility.
Claim 17 is similarly rejected on the same basis as claim 8 above as claim 17 is the method corresponding to the apparatus of claim 8 above.
In regards to claim 9, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein even packed data element positions are to be subjected to addition and odd packed data elements positions are to be subjected to subtraction. Samudrala does generally disclose fusing and performing fused operations including multiplies, additions and subtractions ([0038 and 0141]), however Samudrala has not explicitly disclosed performing fused multiply-alternating subtract/add operations.
Intel discloses wherein even packed data element positions are to be subjected to addition and odd packed data elements positions are to be subjected to subtraction. (see pages 5-263 to 5-264: wherein even packed data elements are added and odd packed data elements are subjected)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector double rounded fused multiply and add or subtract instructions of Samudrala, to perform fused multiply-alternating subtract/add operations as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a vector instruction to perform fused multiply-alternating subtract/add operations as taught in Intel) for another (using a vector instruction to perform fused multiply and add or subtract operations as Samudrala) to yield predictable results (vector instructions which perform fused multiply-alternating subtract/add operations) (MPEP 2143, Example B). Furthermore, it would have been obvious because it would add programming flexibility.
Claim 18 is similarly rejected on the same basis as claim 9 above as claim 18 is the method corresponding to the apparatus of claim 9 above.
In regards to claim 19, Samudrala discloses An apparatus (See Fig. 4B: processor core (element 490)) comprising: decoder circuitry to decode an instance of a single instruction ([0095 and 0102] decoder decodes instructions) the instance of the single instruction to include at least having one or more fields for an opcode and location information for three packed data source operands ([0092 and 0095-0096]: wherein a double rounded combined floating-point and add operation includes fields for opcode and location information for three packed source operands Vmm2-Vmm4 (opcode VFCMADD) (See Figs. 3G-H)) wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, a round, using the three packed data source operands and storage into a corresponding packed data element location of an identified destination location ([0096 and 0138]: wherein a double rounded combined floating-point and add operation (opcode VFCMADD) is executed using source operands Vmm2, Vmm3, Vmm4 by multiplying elements of Vmm2 by Vmm3, and then rounding and adding the products to elements of Vmm4, then rounds and stores results in Vmm1) and execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0096, 0103 and 0138]: wherein execution circuitry executes the double rounded combined floating-point and add operation according to the opcode) wherein the execution circuitry comprises multiplication circuitry to perform the multiplication coupled to rounding circuitry coupled to addition and/or subtraction circuitry coupled to rounding circuitry. (see Fig. 14A: wherein execution circuitry comprises multiplication circuitry (processing block 1403) coupled to rounding circuitry (processing block 1404) coupled to addition and/or subtraction circuitry (processing block 1405) coupled to rounding circuitry (processing block 1406) ([0138-0141])
Samudrala does not disclose wherein which packed data element positions are to be added and subtracted is defined by the opcode. Samudrala does generally disclose fusing and performing fused operations including multiplies, additions and subtractions ([0038 and 0141]), however Samudrala has not explicitly disclosed performing fused multiply-alternating add/subtract operations, wherein which element positions are added and subtracted is defined by opcode.
Intel discloses wherein which packed data element positions are to be added and subtracted is defined by the opcode (see pages 5-256 to 5-257 and 5-263 to 5-264: wherein fused multiply-alternating add and subtract instruction opcodes indicate which element positions are added and subtracted. For example, VFMSUBADD opcode subtracts odd elements and adds even elements, while VFMADDSUB opcode adds odd elements and subtracts even elements)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector double rounded fused multiply and add or subtract instructions of Samudrala, to perform fused multiply-alternating add/subtract operations as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a vector instruction to perform fused multiply-alternating add/subtract operations as taught in Intel) for another (using a vector instruction to perform fused multiply and add or subtract operations as Samudrala) to yield predictable results (vector instructions which perform fused multiply-alternating add/subtract operations) (MPEP 2143, Example B). Furthermore, it would have been obvious because it would add programming flexibility.
In regards to claim 20, the combination of Samudrala and Intel discloses The apparatus of claim 19 (see rejection of claim 19 above) further comprising memory to store the instance of the single instruction. (Samudrala [0102 and Fig. 4B))
Claim(s) 3 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Samudrala, and further in view of Urbanski, PGPUB No. 2019/0205131.
In regards to claim 3, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein the execution circuitry further comprises broadcast circuitry to broadcast an element of one of the source operands to be operated.
Urbanski discloses wherein the execution circuitry further comprises broadcast circuitry to broadcast an element of one of the source operands to be operated. ([0031 and 0037])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify execution circuitry of Samudrala to include broadcast circuitry to broadcast an element of a source operand as taught in Urbanski. It would have been obvious to one of ordinary skill in the art because using broadcast circuitry to broadcast selected elements from source operands allows programmers to pack frequently used constants in packed data (also known as vector or SIMD) registers and then use an embedded broadcast to a particular constant as need in a computational instruction. This typically results in a reduction in cache pressure, cache/memory bandwidth, as well as register pressure (Urbanski [0026]).
Claim 12 is similarly rejected on the same basis as claim 3 above as claim 12 is the method corresponding to the apparatus of claim 3 above.
Response to Arguments
Applicant’s arguments, see page 7 of the remarks, filed on 5/18/2026, with respect to previous 35 USC 112 have been fully considered and are persuasive. Therefore, the previous 35 USC 112 rejections have been withdrawn.
Applicant's arguments, see pages 5-6 of the remarks filed on 5/18/2026, with regards to the 35 USC 101 rejections have been fully considered but they are not persuasive. Thus, the rejections have been maintained.
Applicant first argues the 35 USC 101 rejections, on pages 5-6 of the remarks, in the substance that:
“The Examiner asserts that the claims describe a process that, under its broadest reasonable interpretation, encompasses mathematical calculations and mental processes. Applicant respectfully disagrees. The claims explicitly recite "decoder circuitry to decode an instance of a single instruction" comprising an opcode and "location information for three packed data source operands," and "execution circuitry" that executes the instruction "per packed data element position." A human being cannot practically decode hardware-level machine instructions or execute parallel SIMD (packed data) operations in their mind. As recognized by the courts, when the human mind is not equipped to perform the claimed data processing steps, the claim cannot be classified as a mental process. See, e.g., SRI Int'l, Inc. v. Cisco Sys., Inc., 930 F.3d 1295 (Fed. Cir. 2019) and CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366 (Fed. Cir. 2011). Because the claims cannot be practically performed in the human mind, they are not directed to a mental process under MPEP 2106.04(a)(2)(III)(A).
Regarding the Examiner's assertion that the claims encompass "mathematical
calculations," Applicant respectfully submits that the claims are directed to a specific processor microarchitecture and instruction decoder, not a mathematical formula or concept per se. While the claimed execution circuitry inherently performs arithmetic (multiplication, rounding, and addition/subtraction), the claim as a whole is not directed to a mathematical concept. Instead, the claim is directed to a specific apparatus (e.g., decoder circuitry and execution circuitry) that handles a specific packed-data instruction format having "one or more fields for an opcode and location information for three packed data source operands." Under MPEP 2106.04(a)(2)(I)(C), a claim is not directed to a mathematical concept if it merely uses mathematics to achieve a technical result. Here, the claim uses arithmetic operations to define the specific execution flow of a hardware processor pipeline, not to preempt a mathematical truth.”
The examiner first clarifies that the rejection does not state that the claims recite a mental process, but that the claims recite a mathematical calculation because the claims explicitly recite math (e.g., multiplication, a round, addition and/or subtraction, and a round). Contrary to applicants statements above MPEP 2106.04(a)(2)(I(C) states “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation…”. Thus, it is clear that the claims do encompass a mathematical concept.
The applicant appears to further arguing that the claims are directed towards a specific microprocessor architecture and instruction. Thus, it appears that the applicant is arguing that the mathematical concept is performed on a particular machine as defined in MPEP 2106.05(b). However, this would not take away that the claim still recites math, and therefore includes an abstract idea (e.g. a mathematical concept), contrary to applicants’ assertions. Furthermore, MPEP 2106.05(b) states “…It is important to note that a general-purpose computer that applies a judicial exception, such as an abstract idea, by use of conventional computer functions does not qualify as a particular machine. Ultramercial, Inc. v. Hulu, LLC, 772 F.3d 709, 716-17, 112 USPQ2d 1750, 1755-56 (Fed. Cir. 2014)….If applicant amends a claim to add a generic computer or generic computer components and asserts that the claim recites significantly more because the generic computer is 'specially programmed' (as in Alappat, now considered superseded) or is a 'particular machine' (as in Bilski), the examiner should look at whether the added elements integrate the exception into a practical application or provide significantly more than the judicial exception. Merely adding a generic computer, generic computer components, or a programmed computer to perform generic computer functions does not automatically overcome an eligibility rejection.” Thus, including a specific instruction, a decoder to decode said specific instruction and an execution circuit to execute specific instructions does not add significantly more nor integrate the abstract idea into a practical application because it would be seen as a programmed computer to perform generic computer functions because fundamentally machine instructions must be decoded and executed in a processor. Therefore, decoding and executing instructions are generic computer functions so having programmable decoders and execution circuits to perform an instruction is applying the abstract idea to a computer. (See MPEP 2106.05(f) reciting at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea)
Applicant then argues the 35 USC 101 rejections, on page 6 of the remarks, in the substance that:
“Even if the claims were found to recite an abstract idea, they integrate the operations into a practical application by providing a specific microarchitectural improvement that solves a known issue in prior fused multiply-add (FMA) instructions. The Examiner states that the claim uses "mere instructions to implement the abstract idea" and evaluates the claims at a high level of generality. However, claims directed to an improvement in computer functionality are not abstract. See Enfish, LLC v. Microsoft Corp., 822 F.3d 1327 (Fed. Cir. 2016); see also Ex parte Desjardins, Appeal No. 2024-000567. As explained in the specification at paragraphs [0020]- [0021], prior fused multiply-add (FMADD) and fused multiply-subtract (FMSUB) instructions performed rounding only at the final step (the addition or subtraction), which causes a lack of bitwise reproducibility and may not be what software is expecting. The claimed invention solves this technological problem by defining novel instruction logic that forces an intermediate round between the multiplication and the addition/subtraction, followed by a final round. This specific logical structure improves the functioning of the processor itself by providing bitwise reproducible floating-point calculations. Moreover, there is not some magical "generic" computing component that can decode and execute the claimed instruction as the Office is very well aware. However, if the Office has evidence of universal decoding circuitry, Applicant would appreciate the Office providing a citation as required after Berkheimer instead of only providing what appear to be insincere assertions.”
It appears the applicant is arguing above that the claims recite an improvement to the functioning of the computer as discussed in MPEP 2106.05(a), and would integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. However, the examiner respectfully disagrees because the applicant describes above an improvement to a mathematical algorithm and not a computer. For example, applicant is stating that previous instructions only performed a final round, and thus adding an intermediate round would provide bitwise reproducible floating-point calculations. Thus, the improvement is to the abstract idea itself, and not the computer (e.g. adding an intermediate round (more math) to the previous mathematical algorithm improves mathematical results).
MPEP 2106.04(I) states “The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions. For example, the mathematical formula in Flook…Flook, 437 U.S. at 591-92, 198 USPQ2d at 198 ("the novelty of the mathematical algorithm is not a determining factor at all"). While, MPEP 2106.04(a)(2) states “…The Court’s rationale for identifying these "mathematical concepts" as judicial exceptions is that a ‘‘mathematical formula as such is not accorded the protection of our patent laws,’’ Diehr, 450 U.S. at 191, 209 USPQ at 15 (citing Benson, 409 U.S. 63, 175 USPQ 673), and thus ‘‘the discovery of [a mathematical formula] cannot support a patent unless there is some other inventive concept in its application.’’ Flook, 437 U.S. at 594, 198 USPQ at 199”. Therefore, it is clear that the addition of an intermediate round to the previous algorithm cannot provide an improvement to functioning of a computer (See MPEP 2106.05(a) “…It is important to note, the judicial exception alone cannot provide the improvement… However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology.) Rather, the argued improvement provides a novel or improved mathematical algorithm.
Furthermore, as examiner has asserted above in section 22, the additional claim elements of a decoder and execution circuitry can be viewed as generic computing components of a computer and thus the abstract idea is applied to a generic computer with a programmable decoder and execute circuit to perform generic computer functions (See MPEP 2106.05(f)). Additionally, examiner has cited above a NPL reference in the 35 USC 101 section to a reference to indicate that decoding and executing instructions in computer architecture are generic computer functions that are performed by computer hardware and thus are well-understood, routine and conventional activities/components. (See MPEP 2106.05(d))
Thus, there are no limitations in the claims that would integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Applicant's arguments, see pages 7-8 of the remarks filed on 5/18/2026, with regards to the 35 USC 102 and 103 prior art rejections have been fully considered but they are not persuasive. Thus, the prior art rejections of independent claims 1, 10 and 19 have been maintained.
Claims 2-9, 11-18 and 20 are argued at least based upon their dependencies on one of the independent claims and thus remain rejected at least based upon their dependencies.
Applicant argues the prior art rejections, on pages 7-8 of the remarks, in the substance that:
“The Examiner asserts that Samudrala anticipates the execution circuitry performing "a multiplication, a round, addition and/or subtraction, a round" (see Office Action, page 10). Applicant respectfully submits that anticipation under 35 U.S.C. 102 requires strict identity, meaning that every element of the claimed invention must be found in a single prior art reference, arranged as in the claim (MPEP 2131). While Samudrala's VFCMADD instruction may architecturally define a "double rounded" result, Samudrala's cited execution hardware (e.g., Fig. 14A, apparatus 1401) is a fused multiply-add architecture. Samudrala calculates parallel sums using carry-save adders (CSA1 1440, CSA2 1442) and relies on a single final rounding stage (rounding stage 1464). In cited FIG. 14, the output of the multiplier is fed to a CSA along with "rounding inputs" which are not rounded outputs of the multiplier.
For at least this rationale, Samudrala, as cited, does not appear to describe claim 1.”
The examiner respectfully disagrees with the applicants’ assertions above. The examiner disagrees because the limitations that the applicant argues above are not in the claim language. The claims do not require execution circuitry to perform a multiplication, a round, addition and/or subtraction, a round, by outputting a product of a multiplier to a rounding circuit which rounds the product, without a carry save adder, and then later sends that rounded product to some adder circuitry. In fact, the claims do not mention “rounded outputs of a multiplier” nor “a multiplier”. The claim only requires “execution circuitry to perform a multiplication, a round, addition and/or subtraction, a round” and give no indication how the circuitry accomplishes the operations. Thus, in the Samudrala reference it performs a VFCMADD instruction and the table on page 10 of the reference explicitly states the instruction performs “Multiply floating-point elements from Vmm2 by Vmm3, round and add to elements from Vmm4, then round and store results in Vmm1.” Thus, it is clear that the execution circuitry to perform said instruction performs a multiplication, a round, addition, and a round.
It does appear in Fig. 14A as asserted by applicant that the execution circuitry uses rounding inputs as to allow the carry-save adders to perform a round functionality on the products of the multiplier. However, two rounds as claimed do occur in the Samudrala reference and are performed by the execution circuits of Figs. 14A-B. Thus, the reference discloses the above argued limitations.
Based on applicant arguments above regarding the Samudrala reference, the examiner suggests amending the claims to detail the differences in the circuits used to perform the claimed instruction from the circuit used to perform the double round floating point add or subtract instructions of Samudrala (e.g. how the circuit element 105 of applicants Fig. 1 performs an intermediate round compared to the use of rounding inputs used to perform an intermediate round on products in Samudrala).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lupon, PGPUB No. 2014/0281419 for teaching a cumulative multiply add (CMA) ALU that includes a FP multiplier (element 310) that outputs a product to a CMA rounding unit (element 312) that produces an intermediate rounding product. The intermediate rounding product then is input to a FP adder (element 314) to be added to another input and the summation is sent to a subsequent rounding unit (element 316)
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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