DETAILED ACTION
This communication is responsive to the application filed on 3/30/2023. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “An apparatus” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…a multiplication, a round, addition and/or subtraction, a round” which describe a process that under its broadest reasonable interpretation encompasses mathematical calculations. That is other than reciting generic computing components (e.g. decoder circuitry and execution circuitry to execute instructions) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses performing multiplication of values, followed by rounding of multiplication results, followed by addition and/or subtraction of values with the rounded multiplication results, and finally the addition/subtracted results are rounded to generate a final result (see paragraph [0023] of applicant’s specification), thus the limitation encompasses mathematical calculations (MPEP 2106.04(a)(2)(I)(C)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include at least having one or more fields for an opcode and location information for three packed data source operands, wherein the opcode is to indicate execution circuitry is to perform, per packed data element position… using the three packed data source operands…and execution circuitry to execute the decoded instance of the single instruction according to the opcode.
and storage into a corresponding packed data element location of an identified destination location
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)); the use of packed data operands can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector processing) (MPEP 2106.05(h))) and (b) recites insignificant extra-solution activity (i.e. data outputting) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); the use of packed data operands can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector processing) (MPEP 2106.05(h))). Furthermore, using computer components such as decoder and execution circuitry can be viewed as well-understood, routine and conventional because it is well-known in computer architecture to process instructions by using a pipeline which include decodes and execute instructions (See NPL reference “Computer Architecture A Quantitative Approach”, pages C-34 to C-35 and 232). While, (b) recites insignificant extra-solution activity of data outputting (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, dependent upon claim 1, further recites “…wherein one of the three source operands is the identified destination location”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, dependent upon claim 1 further recites “…wherein the execution circuitry further comprises broadcast circuitry to broadcast an element of one of the source operands to be operated” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Further, the limitation states “broadcast an element” which can be the insignificant extra-solution activity of data gathering and/or outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4, dependent upon claim 1, further recites “…wherein at least one of the source operands is memory”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, dependent upon claim 1, further recites “…wherein the rounds are to be performed by rounding circuitry”, which ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, dependent upon claim 1 further recites “…wherein the instance of the single instruction is to further include one or more fields to identify a writemask, wherein the execution circuitry is to use the identified writemask to determine which packed data element locations of the identified destination location to store to” which recites further abstract ideas including mental processes (e.g. the claimed determining). The further additional limitations tie the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)); also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)).Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, dependent upon claim 1 further recites “…wherein the round is one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero” which recites further abstract ideas including mathematical concepts. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 8, dependent upon claim 1 further recites “…wherein odd packed data element positions are to be subjected to addition and even packed data elements positions are to be subjected to subtraction” which recites further abstract ideas including mathematical concepts. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 9, dependent upon claim 1 further recites “…wherein even packed data element positions are to be subjected to addition and odd packed data elements positions are to be subjected to subtraction” which recites further abstract ideas including mathematical concepts. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claims 10 and 19 are similarly rejected on the same basis as claim 1 above.
Claims 11-18 and 20 are similarly rejected on the same basis as claims 11-18 above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 7, line 1 the limitation stating “the round” lacks clarity. The limitation lacks clarity because it is unclear if the round is referring to the first recitation of “a round” of claim 1, line 6 or the second recitation of “a round” of claim 1, line 6? For purposes of examination the examiner will interpret the limitation to be referring to the second recitation of “a round” of claim 1.
In regards to claim 16, line 1 the limitation stating “the round” lacks clarity. The limitation lacks clarity because it is unclear if the round is referring to the first recitation of “a round” of claim 10, line 7 or the second recitation of “a round” of claim 10, line 8? For purposes of examination the examiner will interpret the limitation to be referring to the second recitation of “a round” of claim 10, line 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 10 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Samudrala, PGPUB No. 2017/0039033.
In regards to claim 1, Samudrala discloses An apparatus (See Fig. 4B: processor core (element 490)) comprising: decoder circuitry to decode an instance of a single instruction ([0095 and 0102] decoder decodes instructions) the instance of the single instruction to include at least having one or more fields for an opcode and location information for three packed data source operands ([0092 and 0095-0096]: wherein a double rounded combined floating-point and add operation includes fields for opcode and location information for three packed source operands Vmm2-Vmm4 (opcode VFCMADD) (See Figs. 3G-H)) wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, a round, using the three packed data source operands and storage into a corresponding packed data element location of an identified destination location ([0096 and 0138]: wherein a double rounded combined floating-point and add operation (opcode VFCMADD) is executed using source operands Vmm2, Vmm3, Vmm4 by multiplying elements of Vmm2 by Vmm3, and then rounding and adding the products to elements of Vmm4, then rounds and stores results in Vmm1) and execution circuitry to execute the decoded instance of the single instruction according to the opcode. ([0103 and 0138]: wherein execution circuitry executes the double rounded combined floating-point and add operation according to the opcode)
Claim 10 is similarly rejected on the same basis as claim 1 above as claim 10 is the method corresponding to the apparatus of claim 1 above. (Note claim 10 includes additional limitations stating “…translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture”. However, Samudrala discloses “…translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture”. ([0135-0137 and Fig. 13]))
In regards to claim 5, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the rounds are to be performed by rounding circuitry. ([0138-0140 and 0141]: wherein the rounds are performed by rounding circuitry (See Figs. 14A-B))
Claim 14 is similarly rejected on the same basis as claim 5 above as claim 14 is the method corresponding to the apparatus of claim 5 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 6-9, 11, 13 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Samudrala, and further in view of NPL reference, “Intel Architecture Instruction Set Extensions Programming Reference”, hereby referred to as Intel.
In regards to claim 2, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein one of the three source operands is the identified destination location.
Intel discloses wherein one of the three source operands is the identified destination location. (see pages 5-256 to 5-257: wherein a first source operand xmm1 is the identified destination location)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector instruction of Samudrala, which uses three source operands and a separate destination operand location, to use one of the source operands as a destination location as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a source operand as a identifier for a source operand location and a destination operand location as taught in Intel) for another (using separate source and destination operand locations as taught in Samudrala) to yield predictable results (vector instructions which use an operand identifier to identify a register as both a source and destination operand) (MPEP 2143, Example B). Furthermore, it would have been obvious because using a single register as both a source and destination register can be used for the benefit of saving register file space.
Claim 11 is similarly rejected on the same basis as claim 2 above as claim 11 is the method corresponding to the apparatus of claim 2 above.
In regards to claim 4, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein at least one of the source operands is memory.
Intel discloses wherein at least one of the source operands is memory. (see pages 5-256 to 5-257: wherein a third source operand is a 512/256/128-bit memory location)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector instruction of Samudrala, which use three vector registers as source operands, to use at least one memory source operand as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a memory source operand to perform vector instructions as taught in Intel) for another (using register source operand as Samudrala) to yield predictable results (vector instructions which use at least one memory source operand) (MPEP 2143, Example B). Furthermore, it would have been obvious because using memory source operands can be used for the benefit of saving register file space.
Claim 13 is similarly rejected on the same basis as claim 4 above as claim 13 is the method corresponding to the apparatus of claim 4 above.
In regards to claim 6, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein the instance of the single instruction is to further include one or more fields to identify a writemask, wherein the execution circuitry is to use the identified writemask to determine which packed data element locations of the identified destination location to store to.
Intel discloses wherein the instance of the single instruction is to further include one or more fields to identify a writemask, wherein the execution circuitry is to use the identified writemask to determine which packed data element locations of the identified destination location to store to. (pages 5-256 to 5-257: wherein a destination location is conditionally updated based on a writemask (k1) indicated by a single instruction)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector instruction of Samudrala, to include a writemask operand as the vector instruction of Intel. It would have been obvious to one of ordinary skill in the art because using mask in vector instructions to conditionally update destination locations can be used for the benefit of added programming flexibility and reducing instruction overhead/improving execution speed (e.g. by avoiding the need to explicitly read and write back the unchanged parts of a vector).
Claim 15 is similarly rejected on the same basis as claim 6 above as claim 15 is the method corresponding to the apparatus of claim 6 above.
In regards to claim 7, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein the round is one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero.
Intel discloses wherein the round is one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero. (pages 2-8 to 2-9 and 5-256 to 5-258)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the rounding in the vector instruction of Samudrala, to include one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero as taught in Intel) for another (using generic rounding as disclosed in Samudrala) to yield predictable results (vector instructions which perform a round using one of a round to nearest even, round to down toward negative infinity, round to up toward positive infinity, and round to down toward zero) (MPEP 2143, Example B).
Claim 16 is similarly rejected on the same basis as claim 7 above as claim 16 is the method corresponding to the apparatus of claim 7 above.
In regards to claim 8, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein odd packed data element positions are to be subjected to addition and even packed data elements positions are to be subjected to subtraction. Samudrala does generally disclose fusing and performing fused operations including multiplies, additions and subtractions ([0038 and 0141]), however Samudrala has not explicitly disclosed performing fused multiply-alternating add/subtract operations.
Intel discloses wherein odd packed data element positions are to be subjected to addition and even packed data elements positions are to be subjected to subtraction. (see pages 5-256 to 5-257: wherein odd packed data elements are added and even packed data elements are subjected)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector double rounded fused multiply and add or subtract instructions of Samudrala, to perform fused multiply-alternating add/subtract operations as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a vector instruction to perform fused multiply-alternating add/subtract operations as taught in Intel) for another (using a vector instruction to perform fused multiply and add or subtract operations as Samudrala) to yield predictable results (vector instructions which perform fused multiply-alternating add/subtract operations) (MPEP 2143, Example B). Furthermore, it would have been obvious because it would add programming flexibility.
Claim 17 is similarly rejected on the same basis as claim 8 above as claim 17 is the method corresponding to the apparatus of claim 8 above.
In regards to claim 9, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein even packed data element positions are to be subjected to addition and odd packed data elements positions are to be subjected to subtraction. Samudrala does generally disclose fusing and performing fused operations including multiplies, additions and subtractions ([0038 and 0141]), however Samudrala has not explicitly disclosed performing fused multiply-alternating subtract/add operations.
Intel discloses wherein even packed data element positions are to be subjected to addition and odd packed data elements positions are to be subjected to subtraction. (see pages 5-263 to 5-264: wherein even packed data elements are added and odd packed data elements are subjected)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector double rounded fused multiply and add or subtract instructions of Samudrala, to perform fused multiply-alternating subtract/add operations as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a vector instruction to perform fused multiply-alternating subtract/add operations as taught in Intel) for another (using a vector instruction to perform fused multiply and add or subtract operations as Samudrala) to yield predictable results (vector instructions which perform fused multiply-alternating subtract/add operations) (MPEP 2143, Example B). Furthermore, it would have been obvious because it would add programming flexibility.
Claim 18 is similarly rejected on the same basis as claim 9 above as claim 18 is the method corresponding to the apparatus of claim 9 above.
In regards to claim 19, Samudrala discloses An apparatus (See Fig. 4B: processor core (element 490)) comprising: decoder circuitry to decode an instance of a single instruction ([0095 and 0102] decoder decodes instructions) the instance of the single instruction to include at least having one or more fields for an opcode and location information for three packed data source operands ([0092 and 0095-0096]: wherein a double rounded combined floating-point and add operation includes fields for opcode and location information for three packed source operands Vmm2-Vmm4 (opcode VFCMADD) (See Figs. 3G-H)) wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, a round, using the three packed data source operands and storage into a corresponding packed data element location of an identified destination location ([0096 and 0138]: wherein a double rounded combined floating-point and add operation (opcode VFCMADD) is executed using source operands Vmm2, Vmm3, Vmm4 by multiplying elements of Vmm2 by Vmm3, and then rounding and adding the products to elements of Vmm4, then rounds and stores results in Vmm1) and execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0096, 0103 and 0138]: wherein execution circuitry executes the double rounded combined floating-point and add operation according to the opcode) wherein the execution circuitry comprises multiplication circuitry to perform the multiplication coupled to rounding circuitry coupled to addition and/or subtraction circuitry coupled to rounding circuitry. (see Fig. 14A: wherein execution circuitry comprises multiplication circuitry (processing block 1403) coupled to rounding circuitry (processing block 1404) coupled to addition and/or subtraction circuitry (processing block 1405) coupled to rounding circuitry (processing block 1406) ([0138-0141])
Samudrala does not disclose wherein which packed data element positions are to be added and subtracted is defined by the opcode. Samudrala does generally disclose fusing and performing fused operations including multiplies, additions and subtractions ([0038 and 0141]), however Samudrala has not explicitly disclosed performing fused multiply-alternating add/subtract operations, wherein which element positions are added and subtracted is defined by opcode.
Intel discloses wherein which packed data element positions are to be added and subtracted is defined by the opcode (see pages 5-256 to 5-257 and 5-263 to 5-264: wherein fused multiply-alternating add and subtract instruction opcodes indicate which element positions are added and subtracted. For example, VFMSUBADD opcode subtracts odd elements and adds even elements, while VFMADDSUB opcode adds odd elements and subtracts even elements)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vector double rounded fused multiply and add or subtract instructions of Samudrala, to perform fused multiply-alternating add/subtract operations as the vector instructions of Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a vector instruction to perform fused multiply-alternating add/subtract operations as taught in Intel) for another (using a vector instruction to perform fused multiply and add or subtract operations as Samudrala) to yield predictable results (vector instructions which perform fused multiply-alternating add/subtract operations) (MPEP 2143, Example B). Furthermore, it would have been obvious because it would add programming flexibility.
In regards to claim 20, the combination of Samudrala and Intel discloses The apparatus of claim 19 (see rejection of claim 19 above) further comprising memory to store the instance of the single instruction. (Samudrala [0102 and Fig. 4B))
Claim(s) 3 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Samudrala, and further in view of Urbanski, PGPUB No. 2019/0205131.
In regards to claim 3, Samudrala discloses The apparatus of claim 1 (see rejection of claim 1 above).
Samudrala does not disclose wherein the execution circuitry further comprises broadcast circuitry to broadcast an element of one of the source operands to be operated.
Urbanski discloses wherein the execution circuitry further comprises broadcast circuitry to broadcast an element of one of the source operands to be operated. ([0031 and 0037])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify execution circuitry of Samudrala to include broadcast circuitry to broadcast an element of a source operand as taught in Urbanski. It would have been obvious to one of ordinary skill in the art because using broadcast circuitry to broadcast selected elements from source operands allows programmers to pack frequently used constants in packed data (also known as vector or SIMD) registers and then use an embedded broadcast to a particular constant as need in a computational instruction. This typically results in a reduction in cache pressure, cache/memory bandwidth, as well as register pressure (Urbanski [0026]).
Claim 12 is similarly rejected on the same basis as claim 3 above as claim 12 is the method corresponding to the apparatus of claim 3 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183