DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed July 9, 2026.
Claims 1-2, 4, 6-8, 10-13 and 15 are pending. Claims 1, 7 and 12 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on May 16, 2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-8, 10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Guo (U.S. 2023/0148366) in view of Hwang et al. (U.S. 2022/0051739; hereinafter “Hwang”).
Regarding independent claim 1, Guo teaches a memory device (Fig. 7), comprising:
a plurality of memory cells (Fig. 5: 112) configured to be programmed to any one of a plurality of program states (see page 1, par. 0006);
a peripheral circuit (Fig. 5: 130) configured to perform a plurality of program loops on the plurality of memory cells (see page 3, par. 0037); and
a program operation controller (Fig. 9A: 321) configured to control the peripheral circuit (Fig. 5: 130) such that a verify operation for a first program state among the plurality of program states is performed and a verify operation for a second program state among the plurality of program states is performed (see page 3, par. 0037 and Table 1),
wherein the verify operation for the second program state is scheduled, prior to the verify operation for the first program state, to be performed from a first program loop after the verify operation for the first program state is performed (“The start loop of a program verification can be defined by the number of programming pulses that have been applied before executing the program verification,” see page 3, par. 0039, see also different scheduling for the verify operation of the second program state in page 4, par. 0049 and 0054).
However, Guo is silent with respect to wherein, when the verify operation for the first program state has passed in a program loop earlier than the first program loop, the verify operation for the second program state is performed from the next program loop after the program loop in which the verify operation for the first program state has passed.
Similar to Guo, Hwang teaches a memory device (Fig. 2) comprising a plurality of memory cells (Fig. 2: 110) configured to be programmed to any one of a plurality of program states (Fig. 5), and a program operation controller (Fig. 2: 130) configured to control the peripheral circuit (Fig. 2: 120) such that a verify operation for a first program state among the plurality of program states is performed and a verify operation for a second program state among the plurality of program states is performed (Fig. 4).
Furthermore, Hwang teaches wherein, when the verify operation for the first program state has passed in a program loop earlier than the first program loop, the verify operation for the second program state is performed from the next program loop after the program loop in which the verify operation for the first program state has passed (Fig. 13 shows a method operation that performs a program loop and a verify operation for a first program state in steps S110 and S120 and multiple program loops for the first program state are performed until the verify operation for the first program state passed. As soon the verify operation for the first program state passed, the verify operation for the second program state will be performed in step S160, i.e. the starting point for the verify operation of second program state is adjustable based on the moment that the verification operation for the first program state passed).
Since Hwang and Guo are from the same field of endeavor, the teachings described by Hwang would have been recognized in the pertinent art of Guo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hwang with the teachings of Guo for the purpose of reduce program operation time, see Hwang’s page 14, par. 0286.
Regarding claim 2, Guo in combination with Hwang teaches the limitations with respect to claim 1.
Furthermore, Guo teaches wherein the first program state has a threshold voltage lower than a threshold voltage of the second program state (see Fig. 1 and page 4, par. 0046).
Regarding claim 4, Guo in combination with Hwang teaches the limitations with respect to claim 1.
Furthermore, Guo teaches wherein the program operation controller determines whether the verify operation for the first program state has passed before the first program loop is performed (see page 3, par. 0039).
Regarding independent claim 7, Guo teaches a method of operating a memory device (Fig. 7), comprising:
applying a program voltage (see page 3, par. 0034) to a plurality of memory cells in a program loop among a plurality of program loops (see page 3, par. 0037); and
performing a verify operation for a first program state among a plurality of program states distinguished based on threshold voltages, and performing a verify operation for a second program state among the plurality of program states (see Fig. 1, page 3, par. 0037 and Table 1),
wherein the verify operation for the second program state is scheduled, prior to the verify operation for the first program state, to be performed from a first program loop after the verify operation for the first program state is performed (“The start loop of a program verification can be defined by the number of programming pulses that have been applied before executing the program verification,” see page 3, par. 0039, see also different scheduling for the verify operation of the second program state in page 4, par. 0049 and 0054).
However, Guo is silent with respect to wherein, when the verify operation for the first program state has passed in a program loop earlier than the first program loop, the verify operation for the second program state is performed from the next program loop after the program loop in which the verify operation for the first program state has passed.
Similar to Guo, Hwang teaches a method of operating (Fig. 13) a memory device (Fig. 2) comprising applying a program voltage to a plurality of memory cells in a program loop among a plurality of program loops (Fig. 4).
Furthermore, Hwang teaches wherein, when the verify operation for the first program state has passed in a program loop earlier than the first program loop, the verify operation for the second program state is performed from the next program loop after the program loop in which the verify operation for the first program state has passed (Fig. 13 shows a method operation that performs a program loop and a verify operation for a first program state in steps S110 and S120 and multiple program loops for the first program state are performed until the verify operation for the first program state passed. As soon the verify operation for the first program state passed, the verify operation for the second program state will be performed in step S160, i.e. the starting point for the verify operation of second program state is adjustable based on the moment that the verification operation for the first program state passed).
Since Hwang and Guo are from the same field of endeavor, the teachings described by Hwang would have been recognized in the pertinent art of Guo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hwang with the teachings of Guo for the purpose of reduce program operation time, see Hwang’s page 14, par. 0286.
Regarding claim 8, Guo in combination with Hwang teaches the limitations with respect to claim 1.
Furthermore, Guo teaches wherein the first program state has a threshold voltage lower than a threshold voltage of the second program state (see Fig. 1 and page 4, par. 0046).
Regarding claim 10, Guo in combination with Hwang teaches the limitations with respect to claim 1.
Furthermore, Guo teaches before the first program loop is performed, determining whether the verify operation for the first program state has passed (see page 3, par. 0039).
Regarding independent claim 12, Guo teaches a memory device (Fig. 7), comprising:
a plurality of memory cells (Fig. 5: 112) configured to be programmed to any one of a plurality of program states (see page 1, par. 0006);
a peripheral circuit (Fig. 5: 130) configured to perform a plurality of program loops on the plurality of memory cells (see page 3, par. 0037); and
a program operation controller (Fig. 9A: 321) configured to control the peripheral circuit (Fig. 5: 130) such that a verify operation for a second program state having a threshold voltage higher than a threshold voltage for a first program state (see Fig. 1 and page 4, par. 0046) among the plurality of program states is scheduled, prior to the verify operation for the first program state, to be performed from a first program loop among the plurality of program loops (“The start loop of a program verification can be defined by the number of programming pulses that have been applied before executing the program verification,” see page 3, par. 0039, see also different scheduling for the verify operation of the second program state in page 4, par. 0049 and 0054) and such that a program loop in which the verify operation for the second program state is to be performed is changed depending on whether the verify operation for the first program state has passed (see pages 5-6, par. 0072).
However, Guo is silent with respect to wherein, when the verify operation for the first program state has passed in a program loop earlier than the first program loops, the verify operation for the second program state is performed from the next program loop after the program loop in which the verify operation for the first program state has passed.
Similar to Guo, Hwang teaches a memory device (Fig. 2) comprising a plurality of memory cells (Fig. 2: 110) configured to be programmed to any one of a plurality of program states (Fig. 5).
Furthermore, Hwang teaches wherein, when the verify operation for the first program state has passed in a program loop earlier than the first program loop, the verify operation for the second program state is performed from the next program loop after the program loop in which the verify operation for the first program state has passed (Fig. 13 shows a method operation that performs a program loop and a verify operation for a first program state in steps S110 and S120 and multiple program loops for the first program state are performed until the verify operation for the first program state passed. As soon the verify operation for the first program state passed, the verify operation for the second program state will be performed in step S160, i.e. the starting point for the verify operation of second program state is adjustable based on the moment that the verification operation for the first program state passed).
Since Hwang and Guo are from the same field of endeavor, the teachings described by Hwang would have been recognized in the pertinent art of Guo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hwang with the teachings of Guo for the purpose of reduce program operation time, see Hwang’s page 14, par. 0286.
Regarding claim 13, Guo in combination with Hwang teaches the limitations with respect to claim 12.
Furthermore, Guo teaches wherein the program operation controller controls the peripheral circuit such that, when the verify operation for the first program state has passed after a program loop after the first program loop, the verify operation for the second program state is performed from the first program loop among the plurality of program loops (see pages 5-6, par. 0072).
Claims 6, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Guo and Hwang as applied to claim 1 above, and further in view of Kim et al. (U.S. 2022/0189557; hereinafter “Kim”).
Regarding claim 6, Guo in combination with Hwang teaches the limitations with respect to claim 1.
However, the combination is silent with respect to wherein the program operation controller controls the peripheral circuit such that a verify voltage for verifying the first program state is not generated after the verify operation for the first program state has passed.
Similar to Guo and Hwang, Kim teaches a memory device (Fig. 2), comprising a plurality of memory cells (Fig. 3: MCs) configured to be programmed to any one of a plurality of program state (Fig. 4: P1-P7), a peripheral circuit (Fig. 2: 120) and a program operation controller (Fig. 2: 131).
Furthermore, Kim teaches wherein the program operation controller controls the peripheral circuit such that a verify voltage for verifying the first program state is not generated after the verify operation for the first program state has passed (Fig. 8: shows that Vfym(1) is not generated after verification success).
Since Kim, Hwang and Guo are from the same field of endeavor, the teachings described by Kim would have been recognized in the pertinent art of Guo in combination with Hwang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim with the teachings of Guo in combination with Hwang for the purpose of enhances reliability, see Kim’s page 1, par. 0005.
Regarding claim 11, Guo in combination with Hwang teaches the limitations with respect to claim 7.
However, the combination is silent with respect to wherein a verify voltage for verifying the first program state is not generated in a program loop after the verify operation for the first program state has passed.
Similar to Guo and Hwang, Kim teaches a method of operating a memory device (see page 1, par. 0007), comprising applying a program voltage to a plurality of memory cells in a program loop among a plurality of program loops (Fig. 1: Vpgm P1 Final Program Operation).
Furthermore, Kim teaches wherein a verify voltage for verifying the first program state is not generated in a program loop after the verify operation for the first program state has passed (Fig. 8: shows that Vfym(1) is not generated after verification success).
Since Kim, Hwang and Guo are from the same field of endeavor, the teachings described by Kim would have been recognized in the pertinent art of Guo in combination with Hwang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim with the teachings of Guo in combination with Hwang for the purpose of enhances reliability, see Kim’s page 1, par. 0005.
Regarding claim 15, Guo in combination with Hwang teaches the limitations with respect to claim 12.
However, the combination is silent with respect to wherein the program operation controller controls the peripheral circuit such that, after the verify operation for the first program state has passed, a verify voltage for verifying the first program state is not generated.
Similar to Guo and Hwang, Kim teaches a memory device (Fig. 2), comprising a plurality of memory cells (Fig. 3: MCs) configured to be programmed to any one of a plurality of program state (Fig. 4: P1-P7), a peripheral circuit (Fig. 2: 120) and a program operation controller (Fig. 2: 131).
Furthermore, Kim teaches wherein the program operation controller controls the peripheral circuit such that, after the verify operation for the first program state has passed, a verify voltage for verifying the first program state is not generated (Fig. 8: shows that Vfym(1) is not generated after verification success).
Since Kim, Hwang and Guo are from the same field of endeavor, the teachings described by Kim would have been recognized in the pertinent art of Guo in combination with Hwang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim with the teachings of Guo in combination with Hwang for the purpose of enhances reliability, see Kim’s page 1, par. 0005.
Response to Arguments
Applicant's arguments filed with respect to claims 1, 7 and 12 have been fully considered but they are not persuasive.
With respect to independent claims 1, 7 and 12, Applicant asserts that both references are directed to reduce programming time and this general objective alone is insufficient to establish a motivation to combine the references in view of the specific teachings of the references. In addition, Applicant asserts that the Office Action does not provide specific technical rationale explaining why or how the verification scheduling of Guo would have been modified in view of Hwang to arrive at the claims, see Applicant’s Remarks pages 6-7. These particular remarks are not considered persuasive.
MPEP cites different rationales to support a conclusion of obviousness that can be relies upon by Office personnel, for example, the rationale used in the applied rejection: MPEP 2143(I)(G) “Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.” A teaching, suggestion, or motivation to combine references that is found in the prior art is an appropriate rationale for determining obviousness.
The teaching, suggestion or motivation test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Further, the teaching, suggestion, or motivation test is flexible and an explicit suggestion to combine the prior art is not necessary, see MPEP 2143(I)(G).
Furthermore, Applicant asserts that the Examiner appear to use Applicant’s disclosure as a roadmap and the rejection relies on hindsight reconstruction, see Applicant’s Remarks pages 7-8. This particular remark is not considered persuasive.
The rejection at issue did not simply rely upon Guo for the rejection of claims 1, 7 and 12. The rejection also relied upon Hwang. As recited above, Hwang teaches a method operation that performs a program loop and a verify operation for a first program state in steps S110 and S120 and multiple program loops for the first program state are performed until the verify operation for the first program state passed. As soon the verify operation for the first program state passed, the verify operation for the second program state will be performed in step S160, i.e. the starting point for the verify operation of second program state is adjustable based on the moment that the verification operation for the first program state passed to provide a program operation time reduction. The motivation adjust the verify operation of second program state based on the moment that the verify operation for the first program state passed was not gleaned only from Applicant’s disclosure of the invention, but was taught by the prior art.
For the above reasons, the previously applied rejection is considered proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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