Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: P202203319US01 (45061)
Filling Date: 03/30/2023
Inventor: Niskayuna et al
Examiner: Bilkis Jahan
DETAILED ACTION
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
2. Applicant’s election without traverse of Group I, claims 1-12, 20 in the reply filed on 06/18/26 is acknowledged.
Claims 13-18 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1, 3, 7-8, 9-11 and 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al (US 2024/0088148 A1).
Regarding claim 1, Chen discloses a semiconductor device (Fig. 1C), comprising: a substrate 100 (Para. 39); a vertical insulator pillar 104 (Para. 41) extending from the substrate 100; a first stack of horizontal sheets of a first channel device (see annotated figure) coupled to a lateral first side of the vertical insulator pillar 104; a second stack of horizontal sheets of a second channel device (see annotated device) coupled to a lateral second side of the vertical insulator pillar 104, opposite the first stack of horizontal sheets; a first gate stack G4 (Para. 42, see annotated figure) wrapped around the first stack of horizontal sheets; a second gate stack G4 (see annotated figure) wrapped around the second stack of horizontal sheets; a first gate extension (see annotated figure) coupled to a center portion of the first gate stack and extending laterally away from the second gate stack; and a second gate extension (see annotated figure) coupled to a center portion of the second gate stack and extending laterally away from the first gate stack (Fig. 1C, annotated figure)..
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Regarding claim 3, Chen further discloses the semiconductor device of claim 1, wherein at least a portion of the vertical insulator pillar 104 is embedded in the substrate 100.
Regarding claim 7, Chen further discloses the semiconductor device of claim 1, wherein the first stack and the second stack of horizontal sheets each comprise a Silicon Germanium (SiGe) nanosheet stack 202, NS02 (Fig. 2, Para. 48).
Regarding claim 8, Chen further discloses the semiconductor device of claim 1, wherein: a lateral side width of the first gate stack (annotated figure) overlapping from the first stack of horizontal sheets NS02 (Para. 41, right side) is substantially similar to a gap between each of the sheets of the first stack of horizontal sheets; and a lateral side width of the second gate stack (annotated figure) overlapping from the second stack of horizontal sheets NS02 (left side of 104) is substantially similar to a gap between each of the sheets of the second stack of horizontal sheets (Fig. 1C).
Regarding claim 9, Chen further discloses the semiconductor device of claim 1, further comprising a shallow trench isolation (STI) 108 (Para. 39) extending from the substrate to a middle portion of the first gate stack and the second gate stack (Fig. 1C, horizontally extending).
Regarding claim 10, Chen further discloses the semiconductor device of claim 1, wherein: the semiconductor device is a forksheet device (Fig. 1C); the first channel device is a p-channel field effect transistor (pFET); and the second channel device is an n-channel field effect transistor (nFET) (Para. 45, CMOS has PFET and NFET).
Regarding claim 11, Chen further discloses the semiconductor device of claim 1, wherein a width of the vertical insulator pillar is below 10 nm 216 (Para. 54, Fig. 7C).
Regarding claim 12, Chen further discloses the semiconductor device of claim 1, wherein the first gate stack (annotated figure) is not directly coupled to the second gate stack (annotated figure) and is separated by the vertical insulator pillar 104.
Allowable Subject Matter
5. Claims 2, 4-5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. Claim 20 is allowed.
7. The following is an examiner’s statement of reasons for allowance:
8. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed forksheet device, comprising: a first gate extension coupled to a center portion of the first gate stack and extending laterally away from the second gate stack; and a second gate extension coupled to a center portion of the second gate stack and extending laterally away from the first gate stack in combination with all other limitations as recited in claim 1.
9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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