DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 10, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (United States Patent Application Publication No. US 2015/0214150 A1, hereinafter “Chang”).
In reference to claim 1, Chang discloses a device which meets the claim. Fig. 1-11 of Chang disclose a semiconductor device which comprises a plurality of horizontal conductive layers (102) that are oriented horizontally in a direction parallel to a surface of a lower structure (20, 70). The examiner notes the use of the term, “coupled,” in lines 5 and 8 of the claim. The examiner also notes that the currently filed specification also states (p. 8, paragraph 23, lines 15-16), “The data storage element CAP may be coupled to bit line BL through the switching element TR.” Thus the examiner has interpreted the term, “coupled,” to mean that there may be intervening objects between two objects that are “coupled” to each other. Therefore in fig. 1-11 of Chang, a vertical conductive line (note unlabeled vias in direct contact with (102)) is commonly coupled to first-side ends of the horizontal conductive layers (102) that are vertically stacked over the lower structure (20, 70) and extends in a direction perpendicular to the surface of the lower structure (20, 70). A plurality of capacitors (22a-22d, 86, 88, 90) are respectively coupled to second-side ends of the horizontal conductive layers (102) and are vertically stacked over the lower structure (20, 70). Chang does not explicitly label the capacitors (22a-22d, 86, 88, 90) as being reservoir capacitors. The applicant defines a reservoir capacitor as a capacitor which stabilizes a voltage from noise (p. 7, paragraph 20, lines 20-22 of the currently filed specification). Chang discloses that the capacitors (22a-22d, 86, 88, 90) stabilize the voltage from noise (p. 2, paragraph 17); thus the capacitors (86, 88, 90) are reservoir capacitors.
With regard to claim 2, as noted above in claim 1, the examiner has interpreted the term, “coupled,” to mean that there may be intervening objects between two objects that are “coupled” to each other. Thus in fig. 1-11 of Chang, each of the reservoir capacitors (22a-22d, 86, 88, 90) includes storage nodes (86) respectively coupled to the second-side ends of the horizontal conductive layers (102), a dielectric layer (88) suitable for covering the storage nodes (86), and a plate node (90) over the dielectric layer (88).
In reference to claim 3, there is a plate line (94) vertically oriented in a direction perpendicular to the surface of the lower structure (20, 70), wherein the plate nodes (90) of the reservoir capacitors are commonly coupled to the plate line (94).
With regard to claim 4, Chang discloses that the horizontal conductive layers (102) are formed by a damascene process (p. 3, paragraph 33) which is understood to include the use of copper. Thus the horizontal conductive layers (102) are made of metal in the form of copper thereby meeting the claim.
In reference to claim 6, Chang discloses that the vias are formed by a damascene process (p. 3, paragraph 33) which is understood to include the use of copper. Thus the vertical conductive line (note unlabeled vias in direct contact with (102)) are made of metal in the form of copper thereby meeting the claim.
With regard to claim 10, the lower structure (20, 70) includes a control circuit (24a-24d, 32) suitable for controlling the reservoir capacitors (22a-22d, 86, 88, 90).
In reference to claim 11, Chang discloses (p. 1, paragraph 14) a memory cell array (30) that is disposed over the lower structure (20, 70) and arranged horizontally from the reservoir capacitors (22a-22d, 86, 88, 90).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Murayama (USPN 5,099,308, hereinafter “Murayama”).
In reference to claim 5, Chang does not disclose that the horizontal conductive layers (102) are made of a silicon material doped with an N-type impurity. However Murayama discloses the known use of polycrystalline silicon doped with an N-type impurity as a conductive wiring material (column 1, lines 20-24). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use polycrystalline silicon doped with an N-type impurity as the material for the horizontal conductive layers (102) in the Chang device.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chang.
In reference to claim 9, in fig. 1-11 of Chang, a vertical conductive line (note unlabeled vias in direct contact with (102)) includes a pillar portion which is oriented vertically in a direction perpendicular to the surface of the lower structure (20, 70). Chang does not disclose that the vertical conductive line (note unlabeled vias in direct contact with (102)) is shaped to have extended portions extending horizontally from the pillar portion. Although Chang does not teach the exact shape of the vertical conductive line as that claimed by Applicant:
A difference in shape is considered an obvious design choice and is not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Therefore this limitation is not patentable over Chang.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Park (United States Patent Application Publication No. US 2009/0236908 A1, hereinafter “Park”).
In reference to claim 18, Chang does not disclose that the memory cell array (30) is a DRAM memory cell array. However Park discloses the need for reservoir capacitors to reduce/stabilize noise from a power supply voltage in order to prevent errors in a DRAM memory cell array (p. 1, paragraphs 3-4). In view of Park, it would therefore be obvious to implement the reservoir capacitors of Chang (22a-22d, 86, 88, 90 – fig. 1-11 of Chang) with a DRAM memory cell array.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Yano et al. (USPN 5,600,163, hereinafter “Yano”).
In reference to claim 19, in fig. 1-11 of Chang, it is understood that there are peripheral circuits which support the operation of the memory cell array (30). Chang does not disclose that the peripheral circuits are disposed at a lower level or a higher level than the memory cell array (30) and the reservoir capacitors (22a-22d, 86, 88, 90). However Yano discloses that stacking peripheral circuits under a memory cell array increases the integration density of the device (column 17, lines 47-50). Yano further discloses that a higher integration density is a known goal in the art (column 1, lines 64-67, column 2, lines 1-3). In view of Yano, it would therefore be obvious to implement the peripheral circuits at a lower level than the memory cell array (30) and the reservoir capacitors (22a-22d, 86, 88, 90) in the Chang device.
Allowable Subject Matter
Claims 7, 8, and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device which comprises a plurality of horizontal conductive layers that are oriented horizontally in a direction parallel to a surface of a lower structure, a vertical conductive line that is commonly coupled to first-side ends of the horizontal conductive layers which extends in a direction perpendicular to the surface of the lower structure, a plurality of reservoir capacitors respectively coupled to second-side ends of the horizontal conductive layers and vertically stacked over the lower structure in combination with the first and second contact nodes as required by the applicant in claim 7. Although parent claim 1 has been amended, the reasons for the allowability of claims 12-17 that were discussed in the previous Office action remain the same.
Response to Arguments
The examiner notes amended 2, 4, 5, and 7, and thus withdraws the rejection of claims 2, 4, 5, 7, and 8 under 35 U.S.C. 112(b) made in the previous Office action.
Applicant's arguments filed February 10, 2026 have been fully considered but they are not persuasive. The applicant has amended claim 1 to indicate that the horizontal conductive layers are “vertically stacked over the substrate.” However as noted in the above Office action, the horizontal conductive layers (102) of Chang are vertically stacked over the substrate (20, 70). The applicant also argues (p. 11 of the response), “Claim 1, as amended, recites ‘a single vertical conductive line that is commonly coupled to first side ends of a plurality of horizontal conductive lavers that are vertically stacked over a lower structure.’" The applicant further argues that this single vertical conductive line acts as shared node that simultaneously connects to multiple horizontally oriented conductive layers arranged in a vertical stack (p. 11 of the response). However amended claim 1 does not claim a single vertical conductive line and still merely describes, “a vertical conductive line.” As noted in the previous Office action and the above Office action, fig. 1-11 of Chang disclose the claimed vertical conductive line (note unlabeled vias in direct contact with (102)) in claim 1. Amended claim 1 also does not recite a shared node. The applicant is reminded that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore claim 1 and dependent claims 2-6, 9-11, 18, and 19 stand rejected in the above Office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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