DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over OKUMURA (US 20190140095) in view of WEHRHAHN-KILIAN (US 20190296143).
Regarding claim 1, OKUMRUA discloses a silicon carbide semiconductor device, comprising:
a semiconductor substrate (the SiC substrate comprising 1, 2 and 6, see fig 1, para 63 and 65) containing silicon carbide (see para 63) and having a first main surface (the upper surface of 2 and 6, see fig 1) and a second main surface (the lower surface of 1, see fig 1) that are opposite to each other,
the semiconductor substrate having
an active region (fig 1, 101, para 37) at the center of the semiconductor substrate, and
a termination region (fig 1, 102, para 37) that surrounds a periphery of the active region (102 surrounds 101, see para 37);
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate, and spanning the active region and the termination region (n-type drift layer 2 and 3, see fig 1, para 38 and 41);
a device structure (the transistor device structure including 6, 8, 9, 10 and 4y, see fig 1, para 38-41), including:
a second semiconductor region of a second conductivity type (fig 1, 6, para 38), provided in the semiconductor substrate, between the first main surface and the first semiconductor region (6 is between the top surface of 6 and 2, see fig 1) and in the active region to thereby form a pn junction between the first semiconductor region and the second semiconductor region (6 and 3 form a pn junction, see fig 1), a current that passes through the pn junction flowing through the device structures (the current channel allows for vertical current flow from 6 to 3, see fig 1, para 46),
a third semiconductor region of the first conductivity type (fig 1, 8, para 38), selectively provided in the semiconductor substrate and between the first main surface and the second semiconductor region (8 is between a top surface and 6, see fig 1),
a trench (trench 25, see fig 1, para 39) penetrating through the third semiconductor region and the second semiconductor region, and reaching the first semiconductor region (25 goes through 8 and 6 to reach 3, see fig 1),
a gate electrode (gate electrode 10, see fig 1, para 40) provided in the trench via a gate insulating film (fig 1, 9, para 40), and
a plurality of second-conductivity-type high-concentration regions (p+ regions 4x and 4y, see fig 1, para 41), selectively provided in the semiconductor substrate and between the first semiconductor region and the second semiconductor region (4x and 4y are between 6 and 2, see fig 1), so as to be closer to the second main surface of the semiconductor substrate than is a bottom of the trench (4y extends below the bottom of the trench 25, see fig 1), the plurality of second- conductivity-type high-concentration regions having an impurity concentration that is higher than an impurity concentration of the second semiconductor region (4y is a p+ region and 6 is a p region, see fig 1, para 41);
a second-conductivity-type outer peripheral region (the portions of 4, 5, 6 and 7c formed around the border between 101 and 102, see fig 1, para 42) formed at the periphery of the active region, the second-conductivity-type outer peripheral region being provided between the first main surface and the first semiconductor region (4, 5, 6 and 7c are between the top surface and 2, see fig 1), and between the device structure and the termination region (the portions are near the border between 101 and 102, see fig 1);
a voltage withstanding structure configured by a plurality of second-conductivity-type voltage withstanding regions (the plurality of p- regions 21 and 22, see fig 1, para 49 and 52), provided between the first main surface and the first semiconductor region and in the termination region (22 are between the top surface and 2, see fig 1, para 52), the plurality of second-conductivity-type voltage withstanding regions being provided apart from one another in a width direction that is parallel to the first main surface, in concentric shapes surrounding the periphery of the active region (22 are in concentric regions spaced apart, see fig 1, para 54);
a plurality of first electrodes electrically connected to the second semiconductor region, the third semiconductor region, and the second-conductivity-type outer peripheral region, the plurality of first electrodes being provided at the first main surface (the electrodes 13, 14, 15 and 16, see fig 1, para 43-44); and
a second electrode electrically connected to the first semiconductor region (fig 1, 17, para 45), the second electrode being provided on the second main surface of the semiconductor substrate (17 is on a bottom surface of 1, see fig 1),
wherein the second-conductivity-type outer peripheral region has a plurality of outer peripheral regions that include:
a first outer peripheral region closest to the first main surface and in contact with an inner end of the voltage withstanding structure (7c is closest to the top surface and is in direct contact with 21, see fig 1, para 38), the first outer peripheral region having a first surface (the top surface of 7c, see fig 1) and a second surface (the bottom surface of 7c, see fig 1) that are opposite to each other, the second surface of the first outer peripheral region facing the second main surface of the semiconductor substrate (the bottom surface of 7c faces the bottom surface, see fig 1),
a second outer peripheral region that is a portion of the second semiconductor region (the portion of 6 that overlaps with 7c is part of base region 6, see fig 1, para 38), and that is closer to the end of the semiconductor substrate than is the device structure (the portion of 6 in 102 is closer to the edge of the substrate than the portion of 6 near the trench 25, see fig 1), the second outer peripheral region being adjacent to the second surface of the first outer peripheral region (the top surface of 6 is in direct contact with 7c, see fig 1), and having a first surface and a second surface that are opposite to each other (6 has a top and a bottom surface, see fig 1), the second surface of the second outer peripheral region facing the second main surface of the semiconductor substrate (the bottom surface of 6 faces the bottom surface, see fig 1),
a third outer peripheral region adjacent to the second surface of the second outer peripheral region (fig 1, 5, para 42), and having a first surface and a second surface that are opposite to each other (5 has a top and a bottom surface, see fig 1), the second surface of the third outer peripheral region facing the second main surface of the semiconductor substrate (the bottom surface of 5 faces the bottom surface, see fig 1), and
a fourth outer peripheral region adjacent to the second surface of the third outer peripheral region (fig 1, 4, para 42), a lower surface of the fourth outer peripheral region and a lower surface of each of the plurality of second-conductivity-type high-concentration regions being at a same depth (lower surfaces of 4, 4x and 4y are at a same depth, see fig 1).
OKUMRUA fails to explicitly disclose a device wherein an entire area of the first main surface being flat from a center to an end of the semiconductor substrate, and
the first to fourth outer peripheral regions being arranged to form, at an outer end of the second- conductivity-type outer peripheral region, a plurality of steps that are recessed stepwise toward the center of the semiconductor substrate, so as to be in an ascending order of proximity to the center of the semiconductor substrate, in a depth direction from the first main surface to the second main surface of the semiconductor substrate, each of the plurality of steps having a same width in the width direction.
WEHRHAHN-KILIAN teaches a device wherein an entire area of the first main surface being flat from a center to an end of the semiconductor substrate (the entire top surface of the substrate 100 can be flat, see fig 11A and 8, para 111 and 126), and
the first to fourth outer peripheral regions being arranged to form, at an outer end of the second- conductivity-type outer peripheral region, a plurality of steps that are recessed stepwise toward the center of the semiconductor substrate, so as to be in an ascending order of proximity to the center of the semiconductor substrate, in a depth direction from the first main surface to the second main surface of the semiconductor substrate (the p-type regions 220 and 290 form a series of steps which increase in proximity to the center of 100 with increasing depth from the top surface of 100, see fig 11A, 290 and 220, para 126), each of the plurality of steps having a same width in the width direction.
OKUMURA and WEHRHAHN-KILIAN are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the substrate and doped circumferential region shapes of WEHRHAHN-KILIAN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the substrate and doped circumferential region shapes of WEHRHAHN-KILIAN in order so that the side surface of the substrate can be field-free (see WEHRHAHN-KILIAN para 59).
Additionally, parameters such as the width of doped regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust width of the steps to make them equal in the device of WEHRAHN-KILIAN so that the side surface of the substrate can be field-free (see WEHRHAHN-KILIAN para 59).
Regarding claim 2, OKUMRUA and WEHRHAHN-KILIAN disclose the silicon carbide semiconductor device according to claim 1.
OKUMRUA further discloses, wherein
an impurity concentration of the third outer peripheral region is lower than the impurity concentration of the plurality of second-conductivity-type high-concentration regions (the high concentration regions 4 can be doped to 2E19 per cc, and the third outer peripheral region 5 can be doped to a maximum of 1E19 per cc, see para 51).
Regarding claim 3, OKUMRUA and WEHRHAHN-KILIAN disclose the silicon carbide semiconductor device according to claim 2.
OKUMRUA further discloses, wherein
the impurity concentration of the third outer peripheral region is within a range of 0.1 times to 0.5 times the impurity concentration of the plurality of second-conductivity-type high-concentration regions (the high concentration regions 4 can be doped to 2E19 per cc, and the third outer peripheral region 5 can be doped to a maximum of 1E19 per cc, see para 51).
Regarding claim 4, OKUMRUA and WEHRHAHN-KILIAN disclose the silicon carbide semiconductor device according to claim 1.
OKUMRUA further discloses, wherein
an impurity concentration of the fourth outer peripheral region is equal to the impurity concentration of the plurality of second-conductivity-type high-concentration regions (the fourth outer peripheral region 4 and the high concentration regions 4x and 4y both include portions of layer 4 which can have a doping concentration of 2E19 per cc, see fig 1 and 3, para 51).
Regarding claim 6, OKUMRUA and WEHRHAHN-KILIAN disclose the silicon carbide semiconductor device according to claim 1.
OKUMRUA further discloses, wherein
the plurality of second-conductivity-type high-concentration regions includes:
a first second-conductivity-type high-concentration region selectively provided in the semiconductor substrate and between the first semiconductor region and the second semiconductor region, the first second-conductivity-type high-concentration region facing the bottom of the trench and having an impurity concentration that is higher than the impurity concentration of the second semiconductor region (p+ region 4y is directly on the bottom of the trench 25, has a higher doping concentration than p-region 6, and a line can be drawn from 6 to 2 that passes through 4y, see fig 1, para 41), and
a second second-conductivity-type high-concentration region selectively provided in the semiconductor substrate and between the first semiconductor region and the second semiconductor region (the p+ region composing 4x and 5x, see fig 1, para 41), so as to be in contact with the second semiconductor region while being apart from the trench and the first second-conductivity-type high-concentration region (5x is in contact with a bottom of 6, and is spaced apart from 25 and 4y, see fig 1), the second second-conductivity-type high-concentration region being closer to the second main surface than is the bottom of the trench (the bottom of 4x is closer to the bottom of 1 than is the bottom of 25, see fig 1), and having an upper surface (the upper surface of 5x) and a lower surface (the lower surface of 4x), a lower portion of the second second-conductivity-type high-concentration region facing the second main surface (a lower portion of 4x faces the bottom of 1, see fig 1), an impurity concentration of the second second-conductivity-type high-concentration region being higher than the impurity concentration of the second semiconductor region (4x is a p+ region and 6 is a p region, see fig 1);
the first surface of the third outer peripheral region and the upper surface of second second-conductivity-type high-concentration region are at a same depth (both are upper surfaces of 5, which will be formed at the same level, see fig 1 and 5, para 64), an impurity concentration of the third outer peripheral region being lower than the impurity concentration of the second second-conductivity-type high-concentration region (the third outer peripheral region is part of 5, which can have a maximum doping concentration of 1E19, and the second high concentration region includes part of 4 which can have a doping concentration of 2E19, see fig 1, para 51); and an impurity concentration of the fourth outer peripheral region being equal to that of the lower portion of the second second-conductivity-type high-concentration region (the fourth outer peripheral region and the lower portion are both portions of 4, see fig 1, para 51).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over OKUMURA (US 20190140095) in view of WEHRHAHN-KILIAN (US 20190296143) and further in view of ARAOKA (US 20200328301).
Regarding claim 5, OKUMRUA and WEHRHAHN-KILIAN disclose the silicon carbide semiconductor device according to claim 1.
OKUMRUA and WEHRHAHN-KILIAN fail to explicitly disclose, wherein
the width of the plurality of steps at the outer end of the second-conductivity-type outer peripheral region is in a range of 1μm to 4μm.
ARAOKA teaches a device, wherein
the width of the plurality of steps at the outer end of the second-conductivity-type outer peripheral region is in a range of 1μm to 4μm (the horizontal width of the outer peripheral region comprising 35', 32, 62b' and 62a' is at least d5, which is 26 microns, and so steps can be defined in that region which have a width of 1 micron, see fig 3, para 79).
OKUMURA, WEHRHAHN-KILIAN and ARAOKA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA and WEHRHAHN-KILIAN with the specific step width of ARAOKA of because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA and WEHRHAHN-KILIAN with the specific step width of ARAOKA in order to prevent dielectric breakdown (see ARAOKA para 108).
Additionally, parameters such as the width of doped regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust width of the steps to make them equal in the device of WEHRAHN-KILIAN so that the side surface of the substrate can be field-free (see WEHRHAHN-KILIAN para 59).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811