DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election of Species I, claims 1-12 in the reply filed on 1/21/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Species II and III, claims 13-20 are non-elected.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2022-0101150 filed in Korean Intellectual Property Office (KIPO) on 08/12/2022 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 03/31/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0104611; hereinafter ‘Yu’) in view of Chang et al. (US 2021/0376155; hereinafter ‘Chang’).
Regarding claim 1, Yu teaches a semiconductor device (FIGS. 2 and 3, [0079]), comprising:
a first cell region (a first cell defined by I1b and including CR1, CR2, and a portion of I1b on a first side thereof, [0033, 0035]; hereinafter ‘C1’) and a second cell region (a second cell defined by I1b and including CR3, and another portion of I1b on an opposite side thereof; hereinafter ‘C2’) adjacent to the first cell region (C1) in a first horizontal direction (X, FIG. 2);
a substrate (100, FIG. 3, [0081]) comprising a first surface (a surface of 100 facing F1, [0084]; hereinafter ‘100a’) and a second surface (a surface of 100 facing away from F1; hereinafter ‘100b’) opposite to the first surface (100a);
first, second and third active patterns (F1, F2, F3 in C1, [0085]; hereinafter ‘F11, F21, F31’) extending in the first horizontal direction (X, FIG. 1) on the first surface of the substrate (100a) in the first cell region (C1), the first, second and third active patterns (F11, F21, F31) are sequentially spaced apart from each other in a second horizontal direction (Y) different from the first horizontal direction (X);
a fourth active pattern (F2 in CR3; hereinafter ‘F22’) extending in the first horizontal direction (X, FIG. 1) on the first surface of the substrate (100a) in the second cell region (C2), the fourth active pattern (F22) is aligned with the second active pattern (F21) in the first horizontal direction (X);
a first active cut (I1b) separating the second active pattern (F21) and the fourth active pattern (F22), the first active cut (I1b) is in contact with each of the second active pattern (F21) and the fourth active pattern (F22, FIGS. 2 and 3);
a first source/drain region (160, FIG. 3, [0100]; hereinafter ‘160_1’) disposed on the second active pattern (F21, FIGS. 2 and 3);
a first buried rail (VDD, [0037]; hereinafter ‘VDD_1’) extending in the first horizontal direction (X); and
a first lower source/drain contact (CA12, [0044]) electrically connects the first source/drain region (160_1, [0109]) to the first buried rail (VDD_1, [0054]).
Yu does not teach the semiconductor device comprising: a first buried rail on the second surface of the substrate, the first buried rail overlaps each of the second and fourth active patterns in a vertical direction; and a first lower source/drain contact penetrating the substrate and the second active pattern in the vertical direction.
Chang teaches a semiconductor device (Fig. 30C, [0103]) comprising:
a first buried rail (134 and 136, [0100-0101]; hereinafter ‘BR_1’) on the second surface of the substrate (a backside surface of 50 facing BPR, [0016]; hereinafter ‘50b’), the first buried rail (BR_1) overlaps the second active pattern (the active pattern; hereinafter ‘AP2’) in a vertical direction (shown in Fig. 30C); and
a first lower source/drain contact (130, [0101]; hereinafter ‘130_1’) penetrating the substrate (the substrate; hereinafter ‘SUBChang’) and the second active pattern (AP2) in the vertical direction (shown in Fig. 30C).
Note: In Chang, the semiconductor substrate 50 includes both a lower bulk semiconductor portion and an upper active region portion in which fin structures are formed. For purposes of the present analysis, the bulk semiconductor portion beneath the fin structures is referred to as the substrate portion, while the fin structures and the semiconductor regions immediately surrounding the source/drain region 92 are referred to as an active pattern portion formed on the substrate. Accordingly, references to the substrate 50 in Chang are interpreted as including (i) a lower substrate portion beneath the source/drain region 95 and (ii) an upper active pattern portion in which the fin structures and the source/drain region 92 are formed.
Chang does not explicitly teach the semiconductor device comprising a first buried rail overlaps each of the second and fourth active patterns.
Chang, however, teaches a backside buried rial 134/136 electrically coupled to plural source/drain regions 92 via respective backside vias 130 [0096, 0099-0101]. Accordingly, one of ordinarily skill in the art would have understood that backside power rail necessarily overlaps multiple active patterns in the vertical direction in order to electrically connect to the plural source/drain regions, as shown in Fig. 30C.
As taught by Chang, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the semiconductor device comprising: a first buried rail on the second surface of the substrate, the first buried rail overlaps each of the second and fourth active patterns in a vertical direction; and a first lower source/drain contact penetrating the substrate and the second active pattern in the vertical direction as claimed, because a backside power rail is not constrained by front-side routing limitations, allowing formation of a continuous conductive rail, and placing the power rail on the backside shortens the power delivery path to the source/drain regions [0096].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chang in combination with Yu due to above reason.
Regarding claim 2, Yu in view of Chang teaches a semiconductor of claim 1, further comprising:
a first gate electrode (Yu: G1, FIG. 2, [0037]) extending in the second horizontal direction (Y) on the first active pattern of the first cell region (F11);
a second gate electrode (G2) extending in the second horizontal direction (Y) on the first active pattern of the first cell region (F11), the second gate electrode (G2) is spaced apart from the first gate electrode (G1) in the first horizontal direction (X); and
a third gate electrode (G3) extending in the second horizontal direction (Y) on the first active pattern of the second cell region (F11 in CR3), the third gate electrode (G3) is spaced apart from the second gate electrode (G2) in the first horizontal direction (X),
wherein the first active pattern (F11) continuously extends in the first horizontal direction (X) in each of the first (C1) and second cell regions (C2), and
wherein a pitch in the first horizontal direction between a center of the second gate electrode and a center of the third gate electrode is equal to or greater than a pitch in the first horizontal direction between a center of the first gate electrode and a center of the second gate electrode (a pitch between G2 ang G3 is greater than a pitch between G1 and G2, FIG. 2).
Regarding claim 3, Yu in view of Chang teaches a semiconductor of claim 1, further comprising:
a second source/drain region (Yu: 160, FIG. 3, [0100]; hereinafter ‘160_2’) disposed on the first active pattern (F1, FIG. 2);
a third source/drain region (160; hereinafter ‘160_3’) disposed on the third active pattern (F3, FIGS. 2 and 3);
a second buried rail (VDD, [0037]; hereinafter ‘VDD_2’) extending in the first horizontal direction (X, FIG. 2);
a third buried rail (VDD; hereinafter ‘VDD_3’) extending in the first horizontal direction (X);
a second lower source/drain contact (CA22, [0037]) electrically connects the second source/drain region (160_2, [0109]) to the second buried rail (VDD_2, [0054]); and
a third lower source/drain contact (CA32) electrically connects the third source/drain region (160_3) to the third buried rail (VDD_3).
Yu does not teach the semiconductor device comprising: a second buried rail on the second surface of the substrate, the second buried rail overlaps the first active pattern in the vertical direction; a third buried rail on the second surface of the substrate, the third buried rail overlaps the third active pattern in the vertical direction; a second lower source/drain contact penetrating the substrate and the first active pattern in the vertical direction; and a third lower source/drain contact penetrating the substrate and the third active pattern in the vertical direction.
Chang teaches the semiconductor device comprising:
a second buried rail (134 and 136, Fig. 30C, [0100-101]; hereinafter ‘BR2’) on the second surface of the substrate (50b), the second buried rail (BR_2) overlaps the first active pattern (the active pattern; hereinafter ‘AP1’) in the vertical direction (shown in Fig. 30C);
a third buried rail (134 and 136; hereinafter ‘BR3’) on the second surface of the substrate (50b), the third buried rail (BR3) overlaps the third active pattern (the active pattern; hereinafter ‘AP3’) in the vertical direction (shown in Fig. 30C);
a second lower source/drain contact (130, [0101]; hereinafter ‘130_2’) penetrating the substrate (SUBChang) and the first active pattern (AP1) in the vertical direction (shown in Fig. 30C); and
a third lower source/drain contact (130; hereinafter ‘130_3’) penetrating the substrate (SUBChang) and the third active pattern (AP3) in the vertical direction (shown in Fig. 30C).
Chang does not explicitly teach that the buried power rails are repeated beneath each source/drain region.
Chang, however, discloses plural source/drain regions electrically coupled through plural lower source/drain contact 130 to power rails 134/136, and does not limit the number or arrangement of such power rails. Accordingly, one of ordinary skill in the art would have understood that the buried power rail structure shown in Fig. 30C is replicated for different active patterns corresponding to different source/drain regions [0012-0013, 0015].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Chang to obtain and achieve the semiconductor device comprising: a second buried rail on the second surface of the substrate, the second buried rail overlaps the first active pattern in the vertical direction; a third buried rail on the second surface of the substrate, the third buried rail overlaps the third active pattern in the vertical direction; a second lower source/drain contact penetrating the substrate and the first active pattern in the vertical direction; and a third lower source/drain contact penetrating the substrate and the third active pattern in the vertical direction as claimed, because it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 4, Yu in view of Chang teaches a semiconductor of claim 3, wherein the first buried rail is a power rail (Yu:VDD_1 is a power supply wiring, [0053]).
Yu does not teach the semiconductor device, wherein each of the second buried rail and the third buried rail is a ground rail.
Chang teaches the semiconductor device, wherein each of the second buried rail and the third buried rail is a ground rail (BR provides ground connection, [0104]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Chang to obtain and achieve the semiconductor device, wherein each of the second buried rail and the third buried rail is a ground rail as claimed, because source/drain region require both a supply voltage and a reference potential, and assigning separate buried rails as power and ground provides a defined return path for current in a backside power delivery configuration [0100].
Regarding claim 5, Yu in view of Chang teaches a semiconductor of claim 3, wherein each of the second buried rail and the third buried rail is a power rail (Yu:VDD_2 and VDD_3 is a power supply wiring, [0053]).
Yu does not teach the semiconductor device, wherein the first buried rail is a ground rail.
Chang teaches the semiconductor device, wherein the first buried rail is a ground rail (BR provides ground connection, [0104]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Chang to obtain and achieve the semiconductor device, wherein the first buried rail is a ground rail as claimed, because source/drain region require both a supply voltage and a reference potential, and assigning separate buried rails as power and ground provides a defined return path for current in a backside power delivery configuration [0100].
Regarding claim 6, Yu in view of Chang teaches a semiconductor of claim 1, further comprising:
a first gate electrode (Yu: G3, FIG. 2, [0037]) extending in the second horizontal direction (Y) on the second active pattern (F21);
a second gate electrode (G4 in CR3, corresponding to an additional gate electrode located in a cell region, FIG. 18, [0155-0156]; hereinafter ‘G4CR3’) extending in the second horizontal direction (Y) on the second active pattern (F21), the second gate electrode (G4CR3) is spaced apart from the first gate electrode (G3) in the first horizontal direction (X);
a third gate electrode (G1) extending in the second horizontal direction (Y) on the fourth active pattern (F22), the third gate electrode (G1) is spaced apart from the second gate electrode (G4CR3) in the first horizontal direction (X);
a fourth gate electrode (G2) extending in the second horizontal direction (Y) on the fourth active pattern (F22), the fourth gate electrode (G2) is spaced apart from the third gate electrode (G1) in the first horizontal direction (X);
a first pull-up transistor (a PFET formed on F21 and gated by G1 in AR1, FIG. 2, [0039]; hereinafter ‘T1’) formed where the second active pattern (F21) and the first gate electrode (G3) intersect;
a second pull-up transistor (a PFET formed on F21 and gated by G4CR3 in AR1; hereinafter ‘T2’) formed where the second active pattern (F21) and the second gate electrode (G4CR3) intersect;
a third pull-up transistor (a PFET formed on F22 and gated by G1 in AR1; hereinafter ‘T3’) formed where the fourth active pattern (F22) and the third gate electrode (G1) intersect; and
a fourth pull-up transistor (a PFET formed on F22 and gated by G2 in AR1; hereinafter ‘T4’) formed where the fourth active pattern (F22) and the fourth gate electrode (G2) intersect,
wherein each of the first to fourth pull-up transistors (T1, T2, T3, and T4) is aligned in the first horizontal direction (X).
Regarding claim 7, Yu in view of Chang teaches a semiconductor of claim 1, further comprising:
a fifth active pattern (Yu: F1 in C2, FIG. 2, [0085]; hereinafter ‘F12’) extending in the first horizontal direction (X) on the first surface of the substrate (100a) in the second cell region (C2), the fifth active pattern (F12) is spaced apart from the first active pattern (F11) in the first horizontal direction (X); and
a sixth active pattern (F3 in C2; hereinafter ‘F32’) extending in the first horizontal direction (X) on the first surface of the substrate (100a) in the second cell region (C2), the sixth active pattern (F32) is spaced apart from the third active pattern (F31) in the first horizontal direction (X),
wherein the first active cut (I1b) extends in the second horizontal direction (Y), the first active cut (I1b, FIG. 3) separates the first active pattern (F11) from the fifth active pattern (F12), the first active cut separates (I1b) the third active pattern (F31) from the sixth active pattern (F32), the first active cut (I1b) is in contact with the first active pattern (F11), the third active pattern (F31), the fifth active pattern (F12), and the sixth active pattern (F32).
Regarding claim 9, Yu in view of Chang teaches a semiconductor of claim 1, wherein
each of the first and third active patterns (Yu: F11 and F31, FIG. 2) continuously extends in the first horizontal direction (X) in each of the first and second cell regions (F1 and F3 in C1 and C2; hereinafter F1 and F3 in C2 are referred to as ‘F12’ and ‘F32’, respectively), and
the fourth active pattern (F22) is disposed between the first active pattern and the third active pattern in the second cell region (F12 and F32).
Regarding claim 10, Yu in view of Chang teaches a semiconductor of claim 1, wherein the first active cut (Yu: I1b, FIG. 2) is disposed on a boundary between the first cell region (C1) and the second cell region (C2).
Claims 1 and 11-12 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0104611) in view of Chang (US 2021/0376155).
Regarding claim 1, Yu teaches a semiconductor device (FIGS. 2 and 3, [0079]), comprising:
a first cell region (a first cell defined by I1b and including CR3, and a portion of I1b on a first side thereof, [0033, 0035]; hereinafter ‘C1’) and a second cell region (a second cell defined by I1b and including CR1, CR2, and another portion of I1b on an opposite side thereof; hereinafter ‘C2’) adjacent to the first cell region (C1) in a first horizontal direction (X, FIG. 2);
a substrate (100, FIG. 3, [0081]) comprising a first surface (a surface of 100 facing F1, [0084]; hereinafter ‘100a’) and a second surface (a surface of 100 facing away from F1; hereinafter ‘100b’) opposite to the first surface (100a);
first, second and third active patterns (F1, F2, F3 in C1, [0085]; hereinafter ‘F11, F21, F31’) extending in the first horizontal direction (X, FIG. 1) on the first surface of the substrate (100a) in the first cell region (C1), the first, second and third active patterns (F11, F21, F31) are sequentially spaced apart from each other in a second horizontal direction (Y) different from the first horizontal direction (X);
a fourth active pattern (F2 in CR1; hereinafter ‘F22’) extending in the first horizontal direction (X, FIG. 1) on the first surface of the substrate (100a) in the second cell region (C2), the fourth active pattern (F22) is aligned with the second active pattern (F21) in the first horizontal direction (X);
a first active cut (I1b) separating the second active pattern (F21) and the fourth active pattern (F22), the first active cut (I1b) is in contact with each of the second active pattern (F21) and the fourth active pattern (F22, FIGS. 2 and 3);
a first source/drain region (160, FIG. 3, [0100]; hereinafter ‘160_1’) disposed on the second active pattern (F21, FIGS. 2 and 3);
a first buried rail (VDD, [0037]; hereinafter ‘VDD_1’) extending in the first horizontal direction (X); and
a first lower source/drain contact (CA12, [0044]) electrically connects the first source/drain region (160_1, [0109]) to the first buried rail (VDD_1, [0054]).
Yu does not teach the semiconductor device comprising: a first buried rail on the second surface of the substrate, the first buried rail overlaps each of the second and fourth active patterns in a vertical direction; and a first lower source/drain contact penetrating the substrate and the second active pattern in the vertical direction.
Chang teaches a semiconductor device (Fig. 30C, [0103]) comprising:
a first buried rail (134 and 136, [0100-0101]; hereinafter ‘BR_1’) on the second surface of the substrate (a backside surface of 50 facing BPR, [0016]; hereinafter ‘50b’), the first buried rail (BR_1) overlaps the second active pattern (the active pattern; hereinafter ‘AP2’) in a vertical direction (shown in Fig. 30C); and
a first lower source/drain contact (130, [0101]; hereinafter ‘130_1’) penetrating the substrate (the substrate; hereinafter ‘SUBChang’) and the second active pattern (AP2) in the vertical direction (shown in Fig. 30C).
Note: In Chang, the semiconductor substrate 50 includes both a lower bulk semiconductor portion and an upper active region portion in which fin structures are formed. For purposes of the present analysis, the bulk semiconductor portion beneath the fin structures is referred to as the substrate portion, while the fin structures and the semiconductor regions immediately surrounding the source/drain region 92 are referred to as an active pattern portion formed on the substrate. Accordingly, references to the substrate 50 in Chang are interpreted as including (i) a lower substrate portion beneath the source/drain region 95 and (ii) an upper active pattern portion in which the fin structures and the source/drain region 92 are formed.
Chang does not explicitly teach the semiconductor device comprising a first buried rail overlaps each of the second and fourth active patterns.
Chang, however, teaches a backside buried rial 134/136 electrically coupled to plural source/drain regions 92 via respective backside vias 130 [0096, 0099-0101]. Accordingly, one of ordinarily skill in the art would have understood that backside power rail necessarily overlaps multiple active patterns in the vertical direction in order to electrically connect to the plural source/drain regions, as shown in Fig. 30C.
As taught by Chang, one of ordinary skill in the art would utilize and modify the above teaching into Yu to obtain and achieve the semiconductor device comprising: a first buried rail on the second surface of the substrate, the first buried rail overlaps each of the second and fourth active patterns in a vertical direction; and a first lower source/drain contact penetrating the substrate and the second active pattern in the vertical direction as claimed, because a backside power rail is not constrained by front-side routing limitations, allowing formation of a continuous conductive rail, and placing the power rail on the backside shortens the power delivery path to the source/drain regions [0096].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chang in combination with Yu due to above reason.
Regarding claim 11, Yu in view of Chang teaches a semiconductor of claim 1, further comprising:
a fifth active pattern (Yu: F2 in CR2, FIG. 2, [0085]; hereinafter ‘F23’) extending in the first horizontal direction (X) on the first surface of the substrate (100a) in the second cell region (C2), the fifth active pattern (F23) is spaced apart from the fourth active pattern (F22) in the first horizontal direction (X); and
a second active cut (I1a, [0035]) separating the fourth active pattern (F22) from the fifth active pattern (F23), the second active cut (I1a) is in contact with each of the fourth active pattern (F22) and the fifth active pattern (F23),
wherein the fourth active pattern (F22) extends in the first horizontal direction (X) in each of the first and second cell regions (C1 and C2),
wherein the first active cut (I1b) is disposed in the first cell region (C1), and
wherein the second active cut (I1a) is disposed in the second cell region (C2).
Regarding claim 12, Yu in view of Chang teaches a semiconductor of claim 11, further comprising:
a first gate electrode (Yu: G3, FIG. 2, [0037]) extending in the second horizontal direction (Y) on the second active pattern (F21);
a second gate electrode (G1) extending in the second horizontal direction (Y) on the fourth active pattern (F22), the second gate electrode (G1) is spaced apart from the first gate electrode (G3) in the first horizontal direction (X);
a third gate electrode (G4, FIG. 18, [0155]) extending in the second horizontal direction (Y) on the fourth active pattern (F22), the third gate electrode (G4) is spaced apart from the second gate electrode (G1) in the first horizontal direction (X);
a fourth gate electrode (G2) extending in the second horizontal direction (Y) on the fifth active pattern (F23), the fourth gate electrode (G2) is spaced apart from the third gate electrode (G4) in the first horizontal direction (X);
a first pull-up transistor (a PFET formed on F21 and gated by G3 in AR1, FIG. 2, [0039]; hereinafter ‘T1R’) formed where the second active pattern (F21) and the first gate electrode (G3) intersect;
a second pull-up transistor (a PFET formed on F22 and gated by G1 in AR1; hereinafter ‘T2R’) formed where the fourth active pattern (F22) and the second gate electrode (G1) intersect;
a third pull-up transistor (a PFET formed on F22 and gated by G4 in AR1; hereinafter ‘T3R’) formed where the fourth active pattern (F22) and the third gate electrode intersect (G4); and
a fourth pull-up transistor (a PFET formed on F23 and gated by G2 in AR1; hereinafter ‘T4R’) formed where the fifth active pattern (F23) and the fourth gate electrode intersect (G2),
wherein each of the first to fourth pull-up transistors (T1R, T2R, T3R, and T4R) is aligned in the first horizontal direction (X).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0104611) in view of Chang (US 2021/0376155), further in view of Baek et al. (US 2021/0074697; hereinafter ‘Baek’).
Regarding claim 8, Yu in view of Chang teaches a semiconductor of claim 7, further comprising:
a dummy structure (Yu: a dummy structure including DG2, 120, 140, and 150, FIGS. 3 and 4, [0092, 0096-0099]; hereinafter ‘DS’) disposed on the second and fourth active patterns (F21 and F22, FIG. 2), the dummy structure (DS) are disposed on a sidewall of the first active cut in the first horizontal direction (a sidewall of I1b facing X; hereinafter ‘I1bside’);
a dummy gate electrode (DG2) disposed on the sidewall of the first active cut in the first horizontal direction (I1bside); and
a dummy gate spacer (140) extending in the second horizontal direction (Y) along the sidewall of the first active cut in the first horizontal direction (I1bside), the dummy gate spacer (140) is in contact with the sidewall of the first active cut in the first horizontal direction (140 is in contact with I1bside through 120).
Yu in view of Chang does not teach that the dummy structure comprises a plurality of stacked dummy nanosheets that are spaced apart from each other in the vertical direction; a dummy gate electrode disposed between the plurality of dummy nanosheets; and a dummy gate spacer disposed on the plurality of dummy nanosheets.
Back teaches a semiconductor device (FIG. 16, [0105]) wherein a dummy structure (125_1 and 125_2, [0106]) comprises a plurality of stacked dummy nanosheets (122NS, [0036]) that are spaced apart from each other in the vertical direction (shown in FIG. 16), a dummy gate electrode (122, FIG. 2, [0107]) disposed between the plurality of dummy nanosheets (122NS), and a dummy gate spacer (126) disposed on the plurality of dummy nanosheets (122NS).
As taught by Back, one of ordinary skill in the art would utilize and modify the above teaching into Yu in view of Chang to obtain and achieve the semiconductor device wherein a dummy structure comprises a plurality of stacked dummy nanosheets that are spaced apart from each other in the vertical direction, a dummy gate electrode disposed between the plurality of dummy nanosheets, and a dummy gate spacer disposed on the plurality of dummy nanosheets as claimed, because a dummy gate stack is placed at standard-cell boundaries to electrically separate adjacent standard cells, while maintaining a gate-stack-like pattern consistent with predefined standard-cell layout rules and a standard-cell library [0106-0108].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Back in combination with Yu in view of Chang due to above reason.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/9/26