Prosecution Insights
Last updated: July 17, 2026
Application No. 18/193,845

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Mar 31, 2023
Priority
Apr 20, 2022 — RE 10-2022-0049031
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
669 granted / 931 resolved
+3.9% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
62 currently pending
Career history
1009
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
83.7%
+43.7% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 01/29/2026 have been fully considered but they are not persuasive. PNG media_image1.png 740 775 media_image1.png Greyscale Fig. 17 of Yang as labeled by examiner above discloses the claimed invention. PNG media_image2.png 487 497 media_image2.png Greyscale Furthermore, fig. 16 of Yang discloses wherein the recessed portion has, on a plane, a closed line shape (see fig. 16 showing NTA3 has four lines and has rectangle shape which is closed line shape) surrounding the active region. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 11, 18-19 and 21are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. 20210320150. PNG media_image1.png 740 775 media_image1.png Greyscale Regarding claim 1, fig. 17 of Yang disclose a display device comprising: a first substrate SUB1 including an active region DA and a peripheral region NDA adjacent to the active region; a circuit element layer TFTL (par [0080] and fig. 12) disposed on the first substrate and including a plurality of insulating layers (OC/PAS/ILD/GI) and at least one transistor; a display element layer (EL layer) disposed on the circuit element layer and including: a pixel-defining layer having an opening defined therein (as labeled by examiner above), and overlapping the active region; a light-emitting element including a first electrode at least partially exposed by the opening, a second electrode, and a light-emitting layer (par [0092]) disposed between the first and second electrodes; and a partition wall (left most member of PDL in fig. 17) overlapping the peripheral region; a sub partition wall (as labeled by examiner above – portion on left of dotted line which sub of partition) disposed between the pixel-defining layer and the partition wall, and overlapping the peripheral region (see dotted showing division between NDA and DA and overlapping); a second substrate 300 disposed on the display element layer; a sealing member 500 disposed between the circuit element layer and the second substrate to define an inner space, and overlapping the peripheral region; and a filling member 700/TFE disposed in the inner space, wherein a recessed portion (see recessed portion of CAP3 under NTA3) overlapping the peripheral region is defined in a rear surface of the second substrate facing the display element layer, a valley region located between the partition wall and the sub partition wall, the valley region having a recessed space (as labeled by examiner above) that overlaps the recessed portion, a part of the filling member is disposed in the recessed portion (portion of 700 which is part of 700/TFE) and the recessed space of the valley region (TFE portion which is part of 700/TFE). Regarding claim 18, fig. 17 of Yang discloses a display device comprising: a first substrate SUB1 including an active region DA and a peripheral region NDA adjacent to the active region; a plurality of insulating layers (OC/PAS/ILD/GI) disposed on the first substrate; a pixel-defining layer PDL having an opening defined therein, and overlapping the active region; a partition wall (left most member of PDL in fig. 17) disposed on a layer the same as that of the pixel-defining layer, and overlapping the peripheral region; a sub partition wall (as labeled by examiner above – portion on left of dotted line which sub of partition) disposed between the pixel-defining layer and the partition wall, and overlapping the peripheral region (see dotted showing division between NDA and DA and overlapping); a light-emitting element EL (par [0092]) disposed on the first substrate and including a first electrode at least partially exposed by the opening, a second electrode, and a light-emitting layer disposed between the first and second electrodes; a second substrate 300 disposed on the light-emitting element and having therein a recessed portion (see recessed portion of CAP3 under NTA3) overlapping the peripheral region; a sealing member 500 overlapping the peripheral region, and disposed between one of the insulating layers and the second substrate to define an inner space; a valley region located between the partition wall and the sub partition wall, the valley region having a recessed space (as labeled by examiner above) that overlaps the recessed portion, a filling member 700/TFE disposed in the inner space and filling the recessed portion (portion of 700 which is part of 700/TFE) and the recessed space of the valley region (TFE portion which is part of 700/TFE), wherein on a plane, the recessed portion (recessed portion of CAP3 under NTA3), the partition wall (left most member of PDL in fig. 17), and the sealing member 500 are adjacent to the active region DA in this order. Regarding claim 2, fig. 17 of Yang discloses wherein on a plane, the recessed portion, the partition wall, and the sealing member are adjacent to the active region in this order. Regarding claim 3, fig. 17 of Yang discloses wherein the second electrode CAT overlaps the active region and the peripheral region, and covers the partition wall. Regarding claims 11 and 19, fig. 16 of Yang discloses wherein the recessed portion has, on a plane, a closed line shape (see fig. 16 showing NTA3 has four lines and has rectangle shape which is closed line shape) surrounding the active region. PNG media_image2.png 487 497 media_image2.png Greyscale Regarding claim 21 (see rejection of claims 1 and 11 above), fig. 17 of Yang disclose a display device comprising: a first substrate including an active region and a peripheral region adjacent to the active region; a circuit element layer disposed on the first substrate and including a plurality of insulating layers and at least one transistor; a display element layer disposed on the circuit element layer and including: a pixel-defining layer having an opening defined therein, and overlapping the active region; a light-emitting element including a first electrode at least partially exposed by the opening, a second electrode, and a light-emitting layer disposed between the first and second electrodes; anda partition wall overlapping the peripheral region; a second substrate disposed on the display element layer;a sealing member disposed between the circuit element layer and the second substrate to define an inner space, and overlapping the peripheral region; and a filling member disposed in the inner space, wherein a recessed portion overlapping the peripheral region is defined in a rear surface of the second substrate facing the display element layer, and has, on a plane, a closed line shape surrounding the active region (claim 11 rejection above), and a part of the filling member is disposed in the recessed portion. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lee et al. 20210202896. Regarding claim 4, fig. 17 of Yang discloses further comprising an upper layer TFE disposed on the second electrode, and overlapping the active region and the peripheral region, wherein the upper layer is in contact with the filling member. Yang does not disclose that the upper layer TFE is organic layer. PNG media_image3.png 294 456 media_image3.png Greyscale However, fig. 3 of Lee discloses upper organic layer disposed on a second electrode, and overlapping the active region, wherein the upper organic layer is in contact with a filling member 148. In view of such teaching, it would have been obvious to form a device of Yang further comprsing wherein upper layer is organic layer such as taught by Lee in order to form a planarization protection layer above the light emitting element. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Boekholtz et al. 20180237682. Regarding claim 16, Yang discloses claim 1, but does not disclose of wherein the sealing member comprises any one among silicone, epoxy, and an acryl-based thermosetting material, and has a viscosity of about 3000 cps to about 40000 cps. Howvever, par [0019] Boekholtz discloses providing a sealing fluid comprising a hardenable or polymerizable epoxy composition comprising an epoxy resin and a hardener characterised by a density of 0.97-1.08 g/cm.sup.3 @ 80° C., an initial mixed viscosity of 5000-50000 cP @ 80° C. and, a setting time of 2-30 minutes. In view of such teaching, it would have been obvious to form a device of Yang comprising wherein the sealing member comprises any one among silicone, epoxy, and an acryl-based thermosetting material, and has a viscosity of about 3000 cps to about 40000 cps such as taught by Boekholtz in order to use prior art processing technology. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Park et al. 20210376291. Regarding claim 17, Yang discloses claim 1, but does not discloses further comprising a floating pattern disposed on a layer the same as that of one of electrodes included in a transistor and overlapping the peripheral region, wherein the floating pattern is in contact with the sealing member. PNG media_image4.png 504 642 media_image4.png Greyscale However, fig. 12 of Park discloses a floating pattern (portion of 171) disposed on a layer 117 the same as that of one of electrodes included in a transistor and overlapping the peripheral region NDA, wherein the floating pattern is in contact with a sealing member 50. In view of such teaching, it would have been obvious to form a device of Yang further comprising a floating pattern disposed on a layer the same as that of one of electrodes included in a transistor and overlapping the peripheral region, wherein the floating pattern is in contact with the sealing member such as taught by Park in order to form a better sealing structure. Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang Regarding claim 14, Yang discloses claim 1. Yang does not disclose wherein the recessed portion has a thickness of about 5 μm to about 20 μm. However, although Yang is silent about the claimed thickness range, it should be noted that a thickness does exist as shown in fig. 17.) Therefore, while the structure of Yang does not quantitatively state thickness range, the courts have held that when the only difference between the claimed invention and the prior art is a size/proportion, then a prima facie case of obviousness exists [See MPEP 2144.04(IV)(A)]. Therefore, it would have been obvious to one of ordinary skill to form a device Yang wherein the recessed portion has a thickness of about 5 μm to about 20 μm in order to have thickness to prevent the colored lights emitted through the first, second, and third transparent areas TA1, TA2, and TA3 from being mixed with one another. Regarding claim 15, Yang discloses claim 1. Yang does not disclose wherein the partition wall has a thickness of about 3 μm to about 5 μm, a width of the partition wall in one direction is about 10 μm to about 50 μm, and a width of the recessed portion in the one direction is greater than the width of the partition wall. However, In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. As such it would have been obvious to form a device of Yang comprising wherein the partition wall has a thickness of about 3 μm to about 5 μm, a width of the partition wall in one direction is about 10 μm to about 50 μm, and a width of the recessed portion in the one direction is greater than the width of the partition wall in order to meet the applicant specification. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Mar 31, 2023
Application Filed
Sep 24, 2025
Non-Final Rejection mailed — §102, §103
Dec 03, 2025
Response Filed
Dec 17, 2025
Final Rejection mailed — §102, §103
Jan 29, 2026
Response after Non-Final Action
Feb 24, 2026
Request for Continued Examination
Mar 03, 2026
Response after Non-Final Action
Jun 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.6%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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