CTNF 18/193,861 CTNF 91278 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 6, 12 and 19 are objected to because of the following informalities: Claims 6, 12 and 19 recite the term ‘singleton transistor’, which is not an art-recognized term, but appears to refer to a single one of a plurality of transistors. Accordingly, the Examiner suggests the following amendment: “…a singleton single transistor…”.” The Examiner suggests the following amendment to correct a further informality of claim 12: “…wherein a singleton transistor is transistor a transistor within the logic gate…” Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites “ coupling the voltage dividing transistor when the voltage dividing transistor is within the guard-band” in lines 4-5 (emphasis added). It is unclear if the term ‘when’ is intended to limit the transistor coupling to occur under certain conditions, or at a certain time. Claim 4 depends on claim 1, which is directed to a method of forming a logic gate. Claims 1 and its dependents are not particularly limited to the type of logic gate formation, such as physically assembling the circuit, or designing the layout of the circuit. If the method is related to physically forming the circuit, then it appears the term ‘when’ refers to a timing limitation, such that the transistor coupling is performed while the circuit is in operation (“when the voltage dividing transistor is within the guard-band”). This would require connecting the voltage dividing transistor to voltage inputs such that the transistor is withing a guard-band, then performing the coupling. If, on the other hand, the method is related to virtually forming the circuit, then it appears the term ‘when’ refers to a contingent limitation, such that the transistor coupling is performed only under certain guard-band conditions (“when the voltage dividing transistor is within the guard-band”). As such the coupling is a contingent limitation, which would not be performed is the transistor is outside the guard-band. For the purpose of compact prosecution, the Examiner has interpreted claim 4 to mean virtually forming the circuit, such that the term ‘when’ refers to a contingent limitation. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 5, 7-9, 14-16 and 18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Ns et al. (Patent No. US 10,128,248 B1) Regarding claim 1 , Ns teaches a method for forming a logic gate with reduced aging (col. 1 lines 43-44: 420), the method comprising: positioning a plurality of transistors (fig, 4B: transistors MP1, MP2, MN1 and/or MN2 positioned in circuit 420) to provide a logic function for the logic gate (col. 5 line 47: NAND function); and coupling a voltage dividing transistor (col. 6 lines 5-12 & fig. 4B: MNfb) to at least one transistor in the plurality of transistors (fig. 4B: MNfb directly or indirectly coupled to at least one of MP1, MP2, MN1 and MN2), the voltage dividing transistor operable to: reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor (col. 6 lines 24-34 & fig. 5: MNfb reduces voltage across MN2). Regarding claim 2 , Ns teaches the method of claim 1, further comprising: identifying a transistor in the logic gate having an output to either a ground or a voltage source as the at least one transistor (fig. 4B: at least one transistor in 420 outputs to either a ground or to a voltage source). Regarding claim 3 , Ns teaches the method of claim 1, further comprising: measuring a voltage output swing at each of the plurality of transistors in the logic function to identify the at least one transistor having a voltage swing above a predetermined threshold (fig. 5); and identifying a transistor with a highest voltage output swing as the at least one transistor (fig. 5: one transistor includes a highest voltage output swing). Regarding claim 5 , Ns teaches the method of claim 1, wherein the coupling the voltage dividing transistor to the at least one transistor further comprises: coupling the voltage dividing transistor across a transistor drain and source (Vds) by stacking the transistor (fig. 4B: MNfb coupled across Vds of MN1 in a stacked manner). Regarding claim 7 , Ns teaches at least one non-transitory computer readable medium comprising computer readable instructions to cause processor circuitry to at least: position a plurality of transistors to provide a logic function for a logic gate (fig. 4B: MP1, MP2, MN1, and MN2 positioned to provide logic circuit 420); and insert a voltage dividing transistor (MNfb) coupled to at least one transistor of the plurality of transistors (fig. 4B: MNfb coupled to MN2), the voltage dividing transistor operable to reduce a voltage across the at least one transistor (col. 6 lines 24-34 & fig. 5: MNfb reduces voltage across MN2). Regarding claim 8 , Ns teaches the at least one non-transitory computer readable medium of claim 7, wherein the transistor in the logic gate comprises an output to either a ground or a voltage source (fig. 4B: output of at least one transistor connected to either ground or voltage source). Regarding claim 9 , Ns teaches the at least one non-transitory computer readable medium of claim 7, wherein a voltage output swing at each of the plurality of transistors in the logic function is associated with identifying a transistor, of the plurality of transistors, having a voltage swing above a predetermined threshold is the transistor (implicit: transistors inherently have predetermined deign tolerances). As understood by the Examiner, all transistors have particular design tolerance, such that operating outside that tolerance would result in unpredictable functioning of the device. As such, a person of ordinary skill in the art would design the circuit to prevent transistors from operating outside this predetermined tolerance. Regarding claim 11 , Ns teaches the method of claim 7, wherein the voltage dividing transistor is coupled across a transistor drain and source (Vds) by stacking the transistor (fig. 4B: MNfb coupled across Vds of MN1 in a stacked manner). Regarding claim 14 , Ns teaches a standard cell comprising: a plurality of CMOS transistors (fig, 4B: transistors MP1, MP2, MN1 and/or MN2 positioned in circuit 420) organized to provide a logic function for a logic gate (col. 5 line 47: NAND function); and a voltage dividing transistor (col. 6 lines 5-12 & fig. 4B: MNfb) coupled to at least one transistor of a plurality of transitors (fig. 4B: MNfb directly or indirectly coupled to at least one of MP1, MP2, MN1 and MN2), the voltage dividing transistor operable to: reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor thereby reducing aging of the logic gate (col. 6 lines 24-34 & fig. 5: MNfb reduces voltage across MN2). Regarding claim 15 , Ns teaches the standard cell of claim 14, wherein the at least one transistor has an output to either a ground or a voltage source (fig. 4B: at least one transistor in 420 outputs to either a ground or to a voltage source). Regarding claim 16 , Ns teaches the standard cell of claim 14 wherein a measured voltage output swing between each of the plurality of transistors in the logic gate identifies a transistor with a highest voltage output swing as the at least one transistor (fig. 5: one transistor includes a highest voltage output swing). Regarding claim 18 , Ns teaches the standard cell of claim 14 wherein the voltage dividing transistor coupled to the at least one transistor is stacked across a transistor drain and source (Vds) (fig. 4B: MNfb coupled across Vds of MN1 in a stacked manner) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim s 4, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ns as applied to claim s 7 and 14 above, and further in view of Alpert et al. (PG Pub. No. US 2013/0346938 A1) . Regarding claim 4 , Ns teaches the method of claim 1, further comprising: determining a guard-band associated with each of the plurality of transistors to add to a nominal voltage (fig. 5); and coupling the voltage dividing transistor when the voltage dividing transistor is within the guard-band (see 35 USC 112 rejection above: coupling is a contingent limitation invoked only under certain conditions, and is not given patentable weight). Ns is silent to the method further including the guard-band avoids timing constraints on the logic gate. Alpert teaches a method including determining a guard-band associated with transistors of a logic gate to add to a nominal voltage to avoid timing constraints on the logic gate (¶ 0035: data processing system performs detailed routing of a logic gate to create a topology that meets design constrains used to assure goals for timing). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the logic gate of Ns to include consideration of timing constraints, as a means to avoid capacitive coupling, and minimize power consumption, among other design goals (Alpert, ¶ 0035). Regarding claim 10 , Ns teaches the at least one non-transitory computer readable medium of claim 7, wherein a guard-band associated with each of the plurality of transistors is configured (fig. 5), and wherein the voltage dividing transistor is coupled when the voltage dividing transistor is within the guard-band (coupling is a contingent limitation invoked only under certain guard-band conditions, and is not given patentable weight). Ns is silent to the method further including the guard-band avoids timing constraints on the logic gate. Alpert teaches a method including determining a guard-band associated with transistors of a logic gate to add to a nominal voltage to avoid timing constraints on the logic gate (¶ 0035: data processing system performs detailed routing of a logic gate to create a topology that meets design constrains used to assure goals for timing). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the logic gate of Ns to include consideration of timing constraints, as a means to avoid capacitive coupling, and minimize power consumption, among other design goals (Alpert, ¶ 0035). Regarding claim 17 , Ns teaches the standard cell of claim 14 wherein each of the plurality of transistors forming the standard cell has a nominal voltage and a guard-band associated with each of the plurality of transistors (col. 5 line 58 through col. 6 line 34 & fig. 5: transistors of figs. 4A-4B have operating voltage guard-bands). Ns is silent to the method further including the guard-band defining timing constraints on the logic gate and the voltage dividing transistor is within the guard-band. Alpert teaches a method including determining a guard-band associated with transistors of a logic gate to add to a nominal voltage to avoid timing constraints on the logic gate (¶ 0035: data processing system performs detailed routing of a logic gate to create a topology that meets design constrains used to assure goals for timing). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the voltage dividing transistor logic gate of Ns to include consideration of a timing constraint guard-band, as a means to avoid capacitive coupling, and minimize power consumption, among other design goals (Alpert, ¶ 0035) . 07-22-aia AIA Claim s 6, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ns as applied to claim s 7 and 14 above, and further in view of Ge et al. (PG Pub. No. US 2017/0069639 A1) . Regarding claim 6 , Ns teaches the method of claim 1, further comprising: Identifying a singleton transistor subject to aging effects as the at least one transistor (col. 5 lines 47-57 & col. 6 lines 20-23: MN2 subject to reliability degradation). Ns is silent to the aging comprising hot carrier effects. Ge teaches a circuit (fig. 3) including a single transistor subject to aging effects such as hot carrier (¶ 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Ns to include minimizing, reducing and/or avoiding hot carrier effects, as a means to prevent reduced performance or even non-functionality (Ge, ¶ 0033), improving circuit reliability. Regarding claim 12 , Ns teaches the at least one non-transitory computer readable medium of claim 7, wherein a singleton transistor is transistor within the logic gate and is subject to aging effects (col. 5 lines 47-57 & col. 6 lines 20-23: MN2 subject to reliability degradation). Ns is silent to the aging comprising hot carrier effects. Ge teaches a circuit (fig. 3) including a transistor subject to aging effects such as hot carrier (¶ 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the processor circuitry of Ns to minimize, reduce and/or avoid hot carrier effects, as a means to prevent reduced performance or even non-functionality (Ge, ¶ 0033), improving circuit reliability. Regarding claim 19 , Ns teaches the standard cell of claim 14 wherein the least one transistor in the plurality of transistors is a singleton transistor subject to aging effects (col. 5 lines 47-57 & col. 6 lines 20-23: MN2 subject to reliability degradation). Ns is silent to the aging comprising hot carrier effects. Ge teaches a circuit (fig. 3) including a transistor subject to aging effects such as hot carrier (¶ 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the processor circuitry of Ns to minimize, reduce and/or avoid hot carrier effects, as a means to prevent reduced performance or even non-functionality (Ge, ¶ 0033), improving circuit reliability . 07-22-aia AIA Claim s 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ns as applied to claim 7 above, and further in view of Hsiao et al. (PG Pub. No. US 2015/0188541 A1) . Regarding claim 13 , Ns teaches the at least one non-transitory computer readable medium of claim 7, comprising a logic function (col. 5 line 47: NAND). Ns does not teach wherein the logic function for the logic gate is an OR/AND/INVERTER (OAI) or a AND/OR/INVERTER (AOI) logic function. Hsiao teaches a logic function for a NAND logic gate is an OR/AND/INVERTER (OAI) or a AND/OR/INVERTER (AOI) logic function (¶ 0037 & figs. 2A-2B: circuit includes NAND and OAI gates). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the logic function of Ns wo provide an OR/AND/INVERTER (OAI) or a AND/OR/INVERTER (AOI) logic function, as a means to increase functionality of the circuit, and/or to improve reliability of circuits with OR/AND/INVERTER (OAI) or AND/OR/INVERTER (AOI) logic functions. Regarding claim 20 , Ns teaches the standard cell of claim 14, comprising a logic function (col. 5 line 47: NAND). Ns does not teach wherein the logic function for the logic gate is an OR/AND/INVERTER (OAI) or a AND/OR/INVERTER (AOI) logic function. Hsiao teaches a logic function for a NAND logic gate is an OR/AND/INVERTER (OAI) or a AND/OR/INVERTER (AOI) logic function (¶ 0037 & figs. 2A-2B: circuit includes NAND and OAI gates). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the logic function of Ns wo provide an OR/AND/INVERTER (OAI) or a AND/OR/INVERTER (AOI) logic function, as a means to increase functionality of the circuit, and/or to improve reliability of circuits with OR/AND/INVERTER (OAI) or AND/OR/INVERTER (AOI) logic functions. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN TURNER/ Examiner, Art Unit 2818 Application/Control Number: 18/193,861 Page 2 Art Unit: 2818 Application/Control Number: 18/193,861 Page 3 Art Unit: 2818 Application/Control Number: 18/193,861 Page 4 Art Unit: 2818 Application/Control Number: 18/193,861 Page 5 Art Unit: 2818 Application/Control Number: 18/193,861 Page 6 Art Unit: 2818 Application/Control Number: 18/193,861 Page 7 Art Unit: 2818 Application/Control Number: 18/193,861 Page 8 Art Unit: 2818 Application/Control Number: 18/193,861 Page 9 Art Unit: 2818 Application/Control Number: 18/193,861 Page 10 Art Unit: 2818 Application/Control Number: 18/193,861 Page 11 Art Unit: 2818 Application/Control Number: 18/193,861 Page 12 Art Unit: 2818 Application/Control Number: 18/193,861 Page 13 Art Unit: 2818
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