DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because in lines 5-6, it appears that “the a first modulation gate” should be “the first modulation gate.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 7-9, 12, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 20190086519) in view of Oh et al. (US 20160204150).
Regarding claim 1, Roy teaches, in Fig. 6, an optical sensor ([0002]), comprising: a pixel (80, [0077]), comprising:
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a photoactive region configured to convert photons into electrons and holes (see Fig. 4C; PD, which includes 43, 45, 41A, and 69; [0051], [0056], [0059]);
a first modulation gate (59 of Tmem1) and a second modulation gate (59 of Tmem3) ([0056], see Fig. 6), wherein the first modulation gate and the second modulation gate are configured to be modulated for indirect time of flight measurement ([0041], “During the integration cycle, the charges photogenerated in photosensitive area PD are transferred to storage areas memi. To achieve this, transfer transistors Tmemi are each set to the on state in turn”; [0042], “sense transistors Tsni are each in turn set to the on state, and the voltage level on node SN is measured and stored”; [0044], “These three voltage levels enable to determine phase shift φ between light signals LE and LR, and thus to deduce therefrom the distance separating the pixel from the point in the scene associated with the pixel”), and wherein the first modulation gate (59 of Tmem1) and the second modulation gate (59 of Tmem3) are arranged on a front side of the pixel, above the photoactive region or extending into the photoactive region (PD) ([0055], the photoactive region; see, for example, Fig. 4C);
a first trench and a second trench (see marked 49 in Fig. 6 above, which includes 53 as shown in Fig. 4B, [0053]) arranged on opposite lateral sides of the photoactive region (leftmost and rightmost sides of 54, which is part of the photoactive region), wherein the first trench and the second trench extend from the front side into the pixel (see Fig. 4D); and
a first memory part (mem1) arranged laterally next to the first trench and at least partially separated from the photoactive region (partially separated from PD by being separated from 54) by the first trench and a second memory part (mem3) arranged laterally next to the second trench and at least partially separated from the photoactive region by the second trench (partially separated from PD by being separated from 54), wherein the first memory part (mem1) is configured to bin electrons generated in the photoactive region when the first modulation gate is active ([0041]) and the second memory part (mem3) is configured to bin electrons generated in the photoactive region when the second modulation gate is active ([0041]).
Roy does not teach that the first trench comprises a first air gap and is configured to act as a first reflective structure for photons in the photoactive region and the second trench comprises a second air gap and is configured to act as a second reflective structure for photons in the photoactive region.
In a similar field of endeavor, Oh teaches, in Fig. 22, that the first trench (116a in the middle) comprises a first air gap ([0099]) and is configured to act as a first reflective structure for photons in the photoactive region (PD) ([0114]) and the second trench (118h on the right) comprises a second air gap ([0099]) and is configured to act as a second reflective structure for photons in the photoactive region (PD) ([0103]), because air has a lower refractive index than the silicon and thus would increase the critical angle and help the trenches totally reflect incident light ([0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first trench and second trench of Roy with the trench structures of Oh, because air has a lower refractive index than the silicon and thus would increase the critical angle and help the trenches totally reflect incident light ([0103]).
Regarding claim 3, Roy in view of Oh teaches the limitations of claim 1. Oh further teaches, in Fig. 22, that sidewalls of the first trench (116a in the middle) and sidewalls of the second trench (118h on the right) are coated with an Al2O3 layer ([0099], [0130], labelled as 118a for second trench 118h, but first trench 116 can also be coated with an Al2O3 layer).
Regarding claim 7, Roy in view of Oh teaches the limitations of claim 1. Roy further teaches that the photoactive region (Fig. 4C; PD, which includes 43, 45, 41A, and 69) is coupled to the first memory part (mem1) at a first bridge region (67 and portion of 47 above 67, Fig. 4C, [0075]) and to the second memory part (mem3) at a second bridge region (67 and portion of 47 above 67, Fig. 4C, [0075]) ([0055], note that "mem2" in Fig. 4C can represent mem1 or mem3), and
that the first bridge region (67 and 47 corresponding with mem1) comprises a first electrical-field-optimizing implant configured to facilitate a transfer of electrons from the photoactive region (PD) to the first memory part (mem1) ([0075]), and that
the second bridge region (67 and 47 corresponding with mem3) comprises a second electrical-field-optimizing implant configured to facilitate a transfer of electrons from the photoactive region to the second memory part (mem3) ([0075]).
Regarding claim 8, Roy in view of Oh teaches the limitations of claim 7. Roy further teaches, in Figs. 4C and 6, that a first length of the first bridge region is no more than half of a length of the first trench, the first length being measured along a longer side of the first trench, parallel to the front side, and that a second length of the second bridge region is no more than half of a length of the second trench, the second length being measured along a longer side of the second trench, parallel to the front side (see how in Fig. 4C, the length of the first trench would be from the right of “Tmem2” to 53, the first length would be the width of 67, and that the width of 67 is less than half the length of the first trench; note that Fig. 4C can also represent either mem1 or mem3; Fig. 4C also applies to the second length compared to the second trench).
Regarding claim 9, Roy in view of Oh teaches the limitations of claim 7. Roy further teaches, in Fig. 4C, that the first electrical-field-optimizing implant and the second electrical-field-optimizing implant comprise a p-implant (47) close to the front side and an n-implant (67) deeper below the front side ([0075], see Fig. 4C).
Regarding claim 12, Roy in view of Oh teaches the limitations of claim 1. Roy further teaches that the first trench and the second trench (see marked 49 in Fig. 6 above) are partial trenches with a respective gap between bottoms of the first trench and the second trench (see marked Fig. 6 above and Fig. 4D) and a backside of the pixel (see Fig. 4D).
Regarding claim 13, Roy teaches a method for fabricating an optical sensor ([0020], [0091]), the method comprising: fabricating a pixel of the optical sensor (80, [0077]) by:
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fabricating a photoactive region configured to convert photons into electrons and holes (see Fig. 4C; PD, which includes 43, 45, 41A, and 69; [0051], [0056], [0059], [0061]);
fabricating a first modulation gate (59 of Tmem1) and a second modulation gate (59 of Tmem3) ([0056], see Fig. 6) configured to be modulated for indirect time of flight measurement ([0041], “During the integration cycle, the charges photogenerated in photosensitive area PD are transferred to storage areas memi. To achieve this, transfer transistors Tmemi are each set to the on state in turn”; [0042], “sense transistors Tsni are each in turn set to the on state, and the voltage level on node SN is measured and stored”; [0044], “These three voltage levels enable to determine phase shift φ between light signals LE and LR, and thus to deduce therefrom the distance separating the pixel from the point in the scene associated with the pixel”), the first (59 of Tmem1) and the second modulation gate (59 of Tmem3) being fabricated on a front side of the pixel, above the photoactive region or extending into the photoactive region (PD) ([0055], above the photoactive region; see, for example, Fig. 4C) ([0061]);
fabricating a first trench and a second trench (see marked 49 in Fig. 6 above, which includes 53 as shown in Fig. 4B, [0053]) on opposite lateral sides of the photoactive region (leftmost and rightmost sides of 54, which is part of the photoactive region), the first trench and the second trench extending from the front side into the pixel (see Fig. 4D) ([0061], [0064]); and
fabricating a first memory part (mem1) laterally next to the first trench such that the first memory part is at least partially separated from the photoactive region (partially separated from PD by being separated from 54) by the first trench and fabricating a second memory part (mem3) laterally next to the second trench such that the second memory part is at least partially separated from the photoactive region by the second trench (partially separated from PD by being separated from 54), wherein the first memory part (mem1) is configured to bin electrons generated in the photoactive region when the first modulation gate is active ([0041]) and the second memory part (mem3) is configured to bin electrons generated in the photoactive region when the second modulation gate is active ([0041]) ([0020]).
Roy does not teach that the first trench comprises a first air gap and is configured to act as a first reflective structure for photons in the photoactive region and the second trench comprises a second air gap and is configured to act as a second reflective structure for photons in the photoactive region.
In a similar field of endeavor, Oh teaches, in Fig. 22, that the first trench (116a in the middle) comprises a first air gap ([0099]) and is configured to act as a first reflective structure for photons in the photoactive region (PD) ([0114]) and the second trench (118h on the right) comprises a second air gap ([0099]) and is configured to act as a second reflective structure for photons in the photoactive region (PD) ([0103]), because air has a lower refractive index than the silicon and thus would increase the critical angle and help the trenches totally reflect incident light ([0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first trench and second trench of Roy with the trench structures of Oh, because air has a lower refractive index than the silicon and thus would increase the critical angle and help the trenches totally reflect incident light ([0103]).
Regarding claim 15, Roy in view of Oh teaches the limitations of claim 13. Roy further teaches, in Fig. 4C, implanting a first electrical field optimizing implant into a first bridge region (67 and portion of 47 above 67, Fig. 4C, [0061]) coupling the photoactive region (Fig. 4C; PD, which includes 43, 45, 41A, and 69) to the first memory part (mem1); and
implanting a second electrical field optimizing implant into a second bridge region (67 and portion of 47 above 67, Fig. 4C, [0061]) coupling the photoactive region (Fig. 4C; PD, which includes 43, 45, 41A, and 69) to the second memory part (mem3) (note that "mem2" in Fig. 4C can represent mem1 or mem3).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 20190086519) in view of Oh et al. (US 20160204150), and further in view of Huang et al. (US 20220115421).
Regarding claim 2, Roy in view of Oh teaches the limitations of claim 1. Roy in view of Oh does not explicitly teach that the first air gap has a first width measured parallel to the front side of 150nm or more, and that the second air gap has a second width measured parallel to the front side of 150nm or more.
In a similar field of endeavor, Huang teaches, in Fig. 2C, that the first air gap (leftmost 222, [0039]) has a first width measured parallel to the front side of 150nm or more, and that the second air gap (rightmost 222) has a second width measured parallel to the front side of 150nm or more ([0039], horizontal width of both air gaps is from 150 nm to 400 nm), because it “lowers the critical angle for a total internal reflection at the boundary between the material and the air gap in the DTI structure,” which “increases the likelihood that a total internal reflection of incident light will occur in the DTI stricture, which will cause the incident light to reflect off of the material-air gap boundary and be absorbed by an associated pixel region as opposed (or in addition) to the incident light traveling through the DTI structure” ([0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the air gap widths of Huang, in order to help the isolation trenches completely reflect incident light away from the memory parts.
Claims 4-6, 14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 20190086519) in view of Oh et al. (US 20160204150), and further in view of Lim et al. (US 20200127025) and Kim et al. (US 20200077055).
Regarding claim 4, Roy in view of Oh teaches the limitations of claim 3. Roy in view of Oh does not explicitly teach an electrically conductive coating arranged on the Al2O3 layer and electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Lim teaches, in Fig. 6A, an electrically conductive coating (45, [0051]) arranged on the Al2O3 layer (41, [0051]), for the purpose of “removing the dark currents from the insulation pattern 41” ([0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the electrically conductive coating of Lim, in order to remove dark currents from the Al2O3 layer.
Roy in view of Oh and Lim does not explicitly teach that the electrically conductive coating is electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Kim teaches, in Fig. 4A, that the electrically conductive coating (VP, [0062]) is electrically connected to contacts (GR, Fig. 3, [0062]) arranged on the front side, in order to “improve a dark current property of an image sensor” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh and Lim with the contact configuration of Kim, in order to improve a dark current property of the optical sensor ([0062]).
Regarding claim 5, Roy in view of Oh, Lim, and Kim teaches the limitations of claim 4. Roy further teaches that the pixel is configured to have a negative potential ([0065]) applied to the electrically conductive coating (57, Fig. 4D, [0065]) of the first trench (49, Fig. 4D) such that a hole accumulation due to the applied negative potential reduces a dark current in the pixel ([0065]), and wherein the pixel is configured to have the negative potential applied to the electrically conductive coating (57, Fig. 4D) of the second trench such that the hole accumulation due to the applied negative potential reduces the dark current in the pixel ([0065]).
Regarding claim 6, Roy in view of Oh, Lim, and Kim teaches the limitations of claim 4. Lim further teaches that the electrically conductive coating (45, Fig. 6A) comprises at least one of a poly-Si layer or a TiN layer (TiN layer, [0052]).
Regarding claim 14, Roy in view of Oh teaches the limitations of claim 13. Roy in view of Oh does not explicitly teach that fabricating the first and the second trenches comprises applying an electrically conductive coating to sidewalls of the first and the second trenches and electrically coupling the electrically conductive coating to contacts on the front side of the pixel.
In a similar field of endeavor, Lim teaches, in Fig. 6A, that fabricating the first and the second trenches comprises applying an electrically conductive coating (45, [0051]) to sidewalls of the first and the second trenches (middle and right trenches), for the purpose of “removing the dark currents from the insulation pattern 41” ([0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of making an optical sensor of Roy in view of Oh with the electrically conductive coating of Lim, in order to remove dark currents from the Al2O3 layer.
Roy in view of Oh and Lim does not explicitly teach electrically coupling the electrically conductive coating to contacts on the front side of the pixel.
In a similar field of endeavor, Kim teaches, in Fig. 4A, electrically coupling the electrically conductive coating (VP, [0062]) to contacts (GR, Fig. 3, [0062]) on the front side of the pixel, in order to “improve a dark current property of an image sensor” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of making optical sensor of Roy in view of Oh and Lim with the contact configuration of Kim, in order to improve a dark current property of the optical sensor ([0062]).
Regarding claim 16, Roy in view of Oh, Lim, and Kim teaches the limitations of claim 4. Roy further teaches that the pixel is configured to have a negative potential ([0065]) applied to the electrically conductive coating (57, Fig. 4D, [0065]) of the first trench (49, Fig. 4D) such that a hole accumulation due to the applied negative potential reduces a dark current in the pixel ([0065]).
Regarding claim 18, Roy in view of Oh teaches the limitations of claim 1. Roy further teaches that the pixel is configured to have a negative potential ([0065]) applied to an electrically conductive coating (57, Fig. 4D, [0065]) of the first trench (49, Fig. 4D) such that a hole accumulation due to the applied negative potential reduces a dark current in the pixel ([0065]).
Roy in view of Oh does not explicitly teach that the electrically conductive coating is arranged on sidewalls of the first trench and sidewalls of the second trench and electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Lim teaches, in Fig. 6A, that the electrically conductive coating (45, [0051]) is arranged on sidewalls of the first trench (middle trench) and sidewalls of the second trench (right trench) ([0051]), for the purpose of “removing the dark currents from the insulation pattern 41” ([0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the electrically conductive coating of Lim, in order to remove dark currents from the optical sensor.
Roy in view of Oh and Lim does not explicitly teach that the electrically conductive coating is electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Kim teaches, in Fig. 4A, that the electrically conductive coating (VP, [0062]) is electrically connected to contacts (GR, Fig. 3, [0062]) arranged on the front side, in order to “improve a dark current property of an image sensor” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh and Lim with the contact configuration of Kim, in order to improve a dark current property of the optical sensor ([0062]).
Regarding claim 19, Roy in view of Oh teaches the limitations of claim 1. Roy further teaches that the pixel is configured to have a negative potential ([0065]) applied to an electrically conductive coating (57, Fig. 4D, [0065]) of the first trench (49, Fig. 4D) such that a hole accumulation due to the applied negative potential reduces a dark current in the pixel ([0065]).
Roy in view of Oh does not explicitly teach that the electrically conductive coating is arranged on sidewalls of the first trench and electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Lim teaches, in Fig. 6A, that the electrically conductive coating (45, [0051]) is arranged on sidewalls of the first trench (middle trench) ([0051]), for the purpose of “removing the dark currents from the insulation pattern 41” ([0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the electrically conductive coating of Lim, in order to remove dark currents from the optical sensor.
Roy in view of Oh and Lim does not explicitly teach that the electrically conductive coating is electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Kim teaches, in Fig. 4A, that the electrically conductive coating (VP, [0062]) is electrically connected to contacts (GR, Fig. 3, [0062]) arranged on the front side, in order to “improve a dark current property of an image sensor” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh and Lim with the contact configuration of Kim, in order to improve a dark current property of the optical sensor ([0062]).
Regarding claim 20, Roy in view of Oh teaches the limitations of claim 1. Roy further teaches that the pixel is configured to have a negative potential ([0065]) applied to an electrically conductive coating (57, Fig. 4D, [0065]) of the second trench (49, Fig. 4D) such that a hole accumulation due to the applied negative potential reduces a dark current in the pixel ([0065]).
Roy in view of Oh does not explicitly teach that the electrically conductive coating is arranged on sidewalls of the second trench and electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Lim teaches, in Fig. 6A, that the electrically conductive coating (45, [0051]) is arranged on sidewalls of the second trench (right trench) ([0051]), for the purpose of “removing the dark currents from the insulation pattern 41” ([0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the electrically conductive coating of Lim, in order to remove dark currents from the optical sensor.
Roy in view of Oh and Lim does not explicitly teach that the electrically conductive coating is electrically connected to contacts arranged on the front side.
In a similar field of endeavor, Kim teaches, in Fig. 4A, that the electrically conductive coating (VP, [0062]) is electrically connected to contacts (GR, Fig. 3, [0062]) arranged on the front side, in order to “improve a dark current property of an image sensor” ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh and Lim with the contact configuration of Kim, in order to improve a dark current property of the optical sensor ([0062]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 20190086519) in view of Oh et al. (US 20160204150), and further in view of Saxod et al. (US 20220077208).
Regarding claim 10, Roy in view of Oh teaches the limitations of claim 1. Roy in view of Oh does not explicitly teach that the first modulation gate has a first L-shape according to a top view directed towards the front side of the pixel, and that the second modulation gate has a second L-shape according to the top view directed towards the front side of the pixel.
In a similar field of endeavor, Saxod teaches, in Figs. 1, that the first modulation gate (112T, [0072]) has a first L-shape according to a top view directed towards the front side of the pixel (see Fig. 1), and that the second modulation gate (112B, [0072]) has a second L-shape according to the top view directed towards the front side of the pixel (see Fig. 1), in order to “obtain image sensors having a low parasitic light sensitivity” ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the L-shaped modulation gates of Saxod, in order to lower the parasitic light sensitivity ([0004]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 20190086519) in view of Oh et al. (US 20160204150), and further in view of Sulfridge et al. (US 20240055537).
Regarding claim 11, Roy in view of Oh teaches the limitations of claim 1. Roy in view of Oh does not explicitly teach at least one backside trench extending from a backside of the pixel into the pixel towards the front side, wherein the at least one backside trench separates the pixel from a further pixel of the optical sensor.
In a similar field of endeavor, Sulfridge teaches, in Fig. 8, at least one backside trench (252 on the right, [0044], [0052]) extending from a backside of the pixel (204-1, [0042]) into the pixel towards the front side (see Fig. 8), wherein the at least one backside trench separates the pixel (204-1) from a further pixel (204-2) of the optical sensor (see Fig. 8), in order to prevent scattered light from reaching the pixel and causing cross-talk ([0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh with the backside trench of Sulfridge, in order to prevent scattered light from reaching the pixel and causing cross-talk ([0052]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 20190086519) in view of Oh et al. (US 20160204150) and Kim et al. (US 20200077055), and further in view of Ahn et al. (US 20140327051).
Regarding claim 17, Roy in view of Oh, Lim, and Kim teaches the limitations of claim 4. Roy further teaches that the pixel is configured to have a negative potential ([0065]) applied to the electrically conductive coating (57, Fig. 4D, [0065]) of the first trench (49, Fig. 4D) such that a hole accumulation due to the applied negative potential reduces a dark current in the pixel ([0065]).
Roy in view of Oh, Lim, and Kim does not teach that electrons collected in the first memory part are pushed out towards a first floating diffusion region of the pixel.
In a similar field of endeavor, Ahn teaches, in Figs. 1A-1B, that electrons collected in the first memory part (SD, [0039]) are pushed out towards a first floating diffusion region (FD, [0045]) of the pixel (100), so that “[a] voltage according to the charges received by the floating diffusion FD may be amplified by transistors … and be output to the outside of the unit pixel 100.” ([0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical sensor of Roy in view of Oh, Lim, and Kim with the floating diffusion region configuration of Ahn, so that a voltage according to the charges received by the floating diffusion region may be amplified by transistors and be output to the outside of the pixel ([0045]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Hsieh (US 20210082978) teaches, in Fig. 2, a configuration of a first trench and a second trench similar to that of claim 1.
Watanabe (US 20240313009) teaches, in Fig. 4 and [0097], materials of a first trench and a second trench similar to that of claim 6.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893