DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election without traverse of Group I, Species I, claims 1-9 in the reply filed on 12/04/2025 is acknowledged.
Group I, Species II, claims 10-18 and Group II, claims 19-20 are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 03/31/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claim 9 is objected to because of the following informalities:
In claim 9, lines 6-7, “a second surface region extending” should read --a second surface region of the sidewalls extending-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant et al. (US 2020/0051860; hereinafter ‘Wyant’) in view of Pagani (US 2018/0226307; hereinafter ‘Pagani’).
Regarding claim 1, Wyant teaches a method [0003], comprising:
thinning (thinning by polishing using a back-grind machine of the non-device side prior to dicing, [0013]) a first side (a backside, which is the non-device side; hereinafter ‘102B’) of a semiconductor substrate (substrate 102, FIG. 1A, [0015]), in which a plurality of dies (105) are formed on a second side (a frontside, which is the device side; hereinafter ‘120F’) of the substrate (102) opposite the first side (120B) and separated from each other by scribe streets (116) of the substrate (102); and
directing a laser beam (106, FIG. 1A, [0015]) at the first side (BS) with an entry point (an entry point on 102B aligned with 116, where 106 is incident and focused by 108) along a scribe street (one of 116) thereof, in which the laser beam (106) is focused inside the substrate (substrate 202, FIG. 2A, [0016]) to form at least one modified region (modified regions 210 and 224, FIG. 2B, [0016]) within the substrate (202) at a location (a location of 210 and 224) spaced apart (14 µm, 28 µm, and 56 µm, TABLES 1-3) from the first side (a frontside of substrate 202) and at least one crack (314, FIG. 3A, [0017]) propagates (shown in FIG. 5D) from the modified region (modified regions 510 and 524, FIG. 5D, [0044]) toward the first side (a frontside of substrate 502, FIG. 5D, [0043]).
Wyant does not teach the method comprising: electrically testing the dies on the substrate, in which the dies being tested are located between modified regions of respective scribe streets of the substrate.
Pagani teaches a method [0018] comprising: electrically testing (wafer-level testing using 38 and ATE, FIG. 4, [0014]) the dies (12 defined on 1 prior to dicing along 10, FIG. 2, [0009]) on the substrate (1 prior to singulation, [0009, 0011, 0014]), in which the dies being tested are located (12 remaining on 1 and separated from one another by 10 prior to dicing, [0009]) between respective scribe streets of the substrate (10 defining the boundaries between adjacent 12 on 1, [0009]).
Pagani does not explicitly disclose modified regions in scribe streets.
However, Wyant teaches modified regions formed in scribe streets prior to singulation. Therefore, when Pagani’s known wafer-level electrical testing prior to dicing is applied to the wafer of Wyant after formation of modified regions, the dies being tested are necessarily located between modified regions of respective scribe streets.
As taught by Pagani, one of ordinary skill in the art would utilize and modify the above teaching into Wyant to obtain and achieve the method comprising: electrically testing the dies on the substrate, in which the dies being tested are located between modified regions of respective scribe streets of the substrate as claimed, because performing wafer-level electrical testing prior to singulation allows identification of defective dies before dicing, thereby improving manufacturing yield and avoiding unnecessary downstream packaging of nonfunctional device [0011, 0014].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Pagani in combination with Wyant due to above reason.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Pagani (US 2018/0226307), and further in view of Inoue et al. (US 6406923; hereinafter ‘Inoue’).
Regarding claim 2, Wyant in view of Pagani teaches the method of claim 1, wherein thinning includes backgrinding to remove the thickness of the substrate from the first side of the substrate (Wyant: thinning using a back-grind machine to remove the thickness of 102B, [0013]).
Wyant in view of Pagani does not teaches the method wherein the substrate has a thickness and the thinning removes less than 10% of the thickness of the substrate.
Inoue teaches a method (Examples 1 and 2) wherein the substrate has a thickness (substrate having a thickness of 725 µm) and the thinning removes less than 10% of the thickness of the substrate (reduction amount of thickness in the range of 20-25 µm).
As taught by Inoue, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Pagani to obtain and achieve the method wherein the substrate has a thickness and the thinning removes less than 10% of the thickness of the substrate as claimed, because the thinning is performed to remove metallic contamination, scratches, and stains from the substrate surface, and excessive mechanical matching is known to introduce a damage layer and cause warp; thus selecting a limited removal amount represents a predictable process optimization (col. 4, lines 26-33).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Inoue in combination with Wyant in view of Pagani due to above reason
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Pagani (US 2018/0226307), and further in view of Poddar et al. (US 7354802; hereinafter ‘Poddar’).
Regarding claim 3, Wyant in view of Pagani teaches the method of claim 1, further comprising removing tape from the second side of the substrate after directing the laser beam (Wyant: removing 312 from the front side of 302 after laser-induced cracks are formed, FIG. 3B, [0018]).
Wyant in view of Pagani does not teaches the method further comprising removing tape prior to testing the dies.
Poddar teaches a method (col. 2, lines 13-17) comprising removing tape prior to testing the dies (removing 202 to expose the I/O pads for probing of the wafer, Figs. 2B and 2C, col. 7, lines 21-29)
As taught by Poddar, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Pagani to obtain and achieve the method further comprising removing tape prior to testing the dies as claimed, because electrical probing requires physical access to the I/O pads of the dies to obtain reliable electrical measurements.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Poddar in combination with Wyant in view of Pagani due to above reason.
Claims 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Pagani (US 2018/0226307), and further in view of Teh (MIT MBA Thesis, 2015).
Regarding claim 4, Wyant in view of Pagani teaches the method of claim 1, but does not teach the method wherein the substrate has a thickness, the thinning is a first thinning prior to directing the laser beam, and the method further comprises: second thinning the first side of the substrate to reduce the thickness of the substrate and separate the dies along the modified regions in the scribe streets.
Teh teaches a method (SDBG, Figure 3-1, p. 63) further comprises: second thinning (wafer backside grinding, Figure 3-1, p. 63) the first side of the substrate to reduce the thickness of the substrate (the backside of the substrate to reduce the thickness) and separate the dies along the modified regions in the scribe streets (die separation along SD in the dicing street, p. 55).
As taught by Teh, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Pagani to obtain and achieve the method further comprises: second thinning the first side of the substrate to reduce the thickness of the substrate and separate the dies along the modified regions in the scribe streets as claimed, because ultra-thin stacked die applications require a reduce final thickness, and the pre-formed SD layer provides a predictable fracture plane during subsequent separation (3.1 Preparation of NAND flash memory Si substrates).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Teh in combination with Wyant in view of Pagani due to above reason
Regarding claim 5, Wyant in view of Pagani and Teh teaches the method of claim 4, Wyant in view of Pagani does not teach the method wherein the second thinning includes backgrinding to remove at least 50% of the thickness of the substrate.
Teh teaches the method wherein the second thinning includes backgrinding to remove at least 50% of the thickness of the substrate (the wafer backside grinding reduces the substrate thickness from 775 µm to 25 µm, pp. 61 and 65).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method wherein the second thinning includes backgrinding to remove at least 50% of the thickness of the substrate as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 6, Wyant in view of Pagani and Teh teaches the method of claim 5, Wyant in view of Pagani does not teach the method wherein the backgrinding removes a portion of the substrate sufficient to remove cracks in the substrate between the first side and the modified region.
Teh teaches the method wherein the backgrinding removes a portion of the substrate between the first side and the modified region (the wafer backside grinding thinning the substrate from a full thickness 775 µm to about 25 µm, thereby removing material between the backside and the SD, pp. 61 and 65).
Teh does not explicitly teach removing cracks in the substrate.
Teh, however, teaches the wafer backside grinding to a depth sufficient to extend to the modified region, and removal of cracks located between the first side and the modified region would necessarily result from such material removal (see, Table 5.1, demonstrating that the SD modified region depth is controllable and predictable based on process settings).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method wherein the backgrinding removes a portion of the substrate sufficient to remove cracks in the substrate between the first side and the modified region as claimed, because grinding depth is a routine process parameter, and selecting a depth sufficient to extend to or into the modified region would predictably eliminate cracks located between the first side and the modified region as a consequence of material removal.
Regarding claim 7, Wyant in view of Pagani and Teh teaches the method of claim 4, further comprising: applying a first tape to the second side of the substrate prior to the second thinning (Wyant: applying 312 to the front side of 302 before laser-induced cracks are formed, FIG. 3B, [0018]).
Wyant in view of Pagani does not teach the method further comprising: applying a second tape to the first side of the substrate after the second thinning.
Teh teaches the method further comprising: applying a second tape to the first side of the substrate after the second thinning (DAF/DT lamination to the backside of the substrate after the wafer backside grinding).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method further comprising: applying a second tape to the first side of the substrate after the second thinning as claimed, because singulated dies must be retained and stabilized for downstream handling and packaging operations (2.5.4 Stealth dicing process integration schemes, p. 59).
Regarding claim 8, Wyant in view of Pagani and Teh teaches the method of claim 7, further comprising: removing the first tape from the second side of the substrate (Wyant: removing 312 from the front side of 302, FIG. 3B, [0018]).
Wyant in view of Pagani does not teach the method further comprising: expanding the substrate using the second tape to space the separated dies apart from one another by a distance.
Teh teaches the method further comprising: expanding the substrate using the second tape to space the separated dies apart from one another by a distance (die separation by cooling expansion with DAF/DT, Figure 3-1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method further comprising: expanding the substrate using the second tape to space the separated dies apart from one another by a distance as claimed, because separating the dies inherently requires controlled expansion and retention by a support tape to maintain die alignment and enable downstream processing (2.5.4 Stealth dicing process integration schemes, p. 59).
Regarding claim 9, Wyant in view of Pagani teaches a semiconductor device (Wyant: FIG. 1B, [0015]) including a die (105 and 605, FIGS. 1B and 6A) produced according to the method of claim 1, wherein: the die has a first surface on the first side (a surface of the backside, which is the non-device side; hereinafter ‘605BS’), a second surface on the second side (a surface of the frontside, which is the device side; hereinafter ‘605FS’) and respective sidewall surfaces (a surface of 602) extending between the first (605BS) and second surfaces (605FS), and a first surface region of the sidewalls (a region of 602 including 610) extending from the first surface (605BS) to an intermediate location (an intermediate location between 610 and 624; hereinafter ‘IL’) has a modified texture (polysilicon texture) responsive to separating adjacent dies (shown in FIG. 1A) through the modified region (610) and a second surface region (a lower region of 602 including IL) extending from the intermediate location (IL) toward the second surface (605FS) has a texture (single crystal texture, [0016]) responsive to separating adjacent dies (shown in FIG. 1A) through a crack (a scribe streets between 610 and 624).
Wyant in view of Pagani does not explicitly teaches that the first surface region of the sidewalls and the second surface region of the sidewalls have different texture.
Teh teaches a die (Figures 5-21 and 5-22) wherein the first surface region of the sidewalls (SD layer) and the second surface region of the sidewalls (cleavage plane {111} defect) have different texture (shown in Figures 5-21).
As taught by Teh, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Pagani to obtain and achieve the die wherein the first surface region of the sidewalls and the second surface region of the sidewalls have different texture as claimed, because laser-induced modification and crack-based fracture are fundamentally different separation mechanisms, and each inherently produces a different sidewall surface morphology as a predictable result of the underlying material modification and fracture processes.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Teh in combination with Wyant in view of Pagani due to above reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818