DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 8/21/2025. Claims 1-26 are pending in this application. Claims 1-9 are amended. Claims 21-26 are new. Claims 10-20 remain withdrawn.
Claim Objections
Claims 3, 6-8, 21-22 and 24 are objected to because of the following informalities:
In claim 3, line 2, “at the first side and” should read --at the first side of the semiconductor substrate and-- (emphasis added).
In claim 6, line 4, “the first side and” should read -- the first side of the semiconductor substrate and-- (emphasis added).
In claim 7, line 2, “the second side prior to” should read -- the second side of the semiconductor substrate prior to-- and line 4, “the first side after thinning” should read -- the first side of the semiconductor substrate after thinning-- (emphasis added).
In claim 8, line 2, “the second side; and” should read -- the second side of the semiconductor substrate; and-- (emphasis added).
In claim 21, line 4, “the first side and” should read -- the first side of the semiconductor substrate and-- and lines 4-5, “the another modified region toward the second side” should read -- the other modified region toward the second side of the semiconductor substrate-- (emphasis added).
In claim 22, line 2, “the another modified region” should read -- the other modified region-- (emphasis added).
In claim 24, line 1, “the another modified region” should read -- the other modified region-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 21-23, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Wyant et al. (US 2020/0051860; hereinafter ‘Wyant’) in view of Kasahara et al. (US 2020/0309637; hereinafter ‘Kasahara’).
Regarding claim 1, Wyant teaches a method [0003], comprising:
thinning a first side of a semiconductor substrate(thinning by polishing using a back-grind machine of the non-device side of semiconductor wafer102 prior to dicing, FIG. 1A, [0013, 0015]),
wherein a plurality of dies (105, FIG. 1A) are formed on a second side of the substrate opposite the first side (a device side of 102, FIG. 1A, [0015]) and
separated from each other by scribe streets (105 separated from one another by scribe streets 116, FIG. 1A, [0015]); and
directing a laser beam (206, FIGS. 2A and 2B, [0016])
at the first side (206 is directed through the non-device side of semiconductor wafer 202) with an entry point (an entry point on the non-device side of 202 where 206 is incident and focused by lens 208, FIGS. 2A and 2B, [0016]) along a scribe street (the entry point aligned with 116, FIGS. 2A and 2B),
wherein the laser beam is focused inside the semiconductor substrate (206 focused within 202, FIGS. 2A and 2B)
to form at least one modified region (polycrystalline modified regions 210 formed by the focused laser energy, FIG. 2B, [0016]) within the semiconductor substrate (210 within 202) at a location (a location of 210; hereinafter ‘210L’) spaced apart from the first side (210L spaced apart 28 µm from the non-device side, FIG. 2B, TABLE 1, [0023]) and
at least one crack (314, FIG. 3A, [0017]) propagates from the at least one modified region toward the first side (314 propagates from 310 corresponding to 210 of FIG. 2A toward the non-device side, FIG. 3A, [0017]).
Wyant does not teach the method comprising: electrically testing the plurality of dies on the semiconductor substrate, after the at least one modified region is formed.
Kasahara teaches a method [0012] comprising: electrically testing (electrical inspection using 500, Fig. 15, [0089-0091]) the plurality of dies on the semiconductor substrate (a plurality of Fabry-Perot interference filter portions 1A on the semiconductor substrate 110, Fig. 16, [0115]).
Kasahara does not explicitly teach performing the electrical testing after the at least one modified region is formed.
Kasahara, however, teaches performing the electrical inspection in the wafer state before subsequent processing and final assembly [0105], and detecting defects including breakage, wiring disconnection, and foreign substances by the electrical inspection [0107-0108].
As taught by Kasahara, one of ordinary skill in the art would utilize and modify the above teaching into Wyant to obtain and achieve the method comprising: electrically testing the plurality of dies on the semiconductor substrate, after the at least one modified region is formed as claimed, because performing the electrical inspection before separation of the dies avoids further processing of defective dies, thereby improving manufacturing efficiency and yield [0007].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Kasahara in combination with Wyant due to the above reason.
Regarding claim 9, Wyant in view of Kasahara teaches a semiconductor device (Wyant: FIG. 1B, [0015]) including a die (105 and 605, FIGS. 1B and 6A) produced according to the method of claim 1, wherein:
the die has a first surface (a non-device side of die 605, FIG. 6A; hereinafter ‘605S1’), a second surface (a device side of die 605, FIG. 6A; hereinafter ‘605S2’), and sidewall surfaces (sidewall surfaces of 605, FIG. 6A; hereinafter ‘605SS’) extending between the first and second surfaces (605SS extending between 605S1 and 605S2, FIG. 6A),
a first surface region of the sidewall surfaces (polysilicon regions 610 and 624 of 605SS, FIG. 6A, [0047]; hereinafter ‘605SS1’) having a first texture (605SS1 has a first texture) and a second surface region of the sidewall surfaces (a region of 605SS other than 605SS1, FIG. 6A; hereinafter ‘605SS2’) having a second texture (605SS2 has a second texture).
Regarding claim 21, Wyant in view of Kasahara teaches the method of claim 1, further comprising
directing the laser beam at the first side with another entry point along the scribe street (Wyant: 206 is directed through the non-device side of 202 with another entry point along scribe street 216, FIGS. 2A and 2B, [0016])
wherein the laser beam is focused inside the semiconductor substrate to form another modified region within the semiconductor substrate at a location spaced apart from the first side (224 formed by focused laser energy within 202 and 224 spaced apart from the non-device side of 202, FIG. 2B, [0016, 0023]), and
another crack propagates from the another modified region toward the second side (314 propagates from 324, corresponding to 224 of FIG. 2B, toward the device side, FIG 3A, [0017]).
Regarding claim 22, Wyant in view of Kasahara teaches the method of claim 21, wherein a third crack propagates between the at least one modified region and the another modified region (Wyant: crack 314 between polycrystalline modified regions 310 and 324, corresponding to 210 and 224 of FIG. 2B, respectively, FIG. 3A, [0017]).
Regarding claim 23, Wyant in view of Kasahara teaches the method of claim 21, wherein the at least one modified region has a first thickness (Wyant: 210 has a first thickness, FIG. 2B, [0016]).
Regarding claim 26, Wyant in view of Kasahara teaches the semiconductor of claim 9, wherein the first texture is different from the second texture (Wyant: the texture of 605SS1 is different from that of 605SS2 due to their different crystalline structures, [0047, 0051]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Kasahara (US 2020/0309637) as applied to claim 1 above, and further in view of Inoue et al. (US 6406923; hereinafter ‘Inoue’).
Regarding claim 2, Wyant in view of Kasahara teaches the method of claim 1, wherein thinning the first side of the semiconductor substrate includes backgrinding to remove a thickness of the semiconductor substrate (Wyant: thinning of the non-device side of 102 using a back-grind machine to remove the thickness of 102, [0013]).
Wyant in view of Kasahara does not teaches the method wherein the thinning of the semiconductor substrate removes less than 10% of the thickness of the semiconductor substrate.
Inoue teaches a method (Examples 1 and 2) wherein the thinning of the semiconductor substrate removes less than 10% of the thickness of the semiconductor substrate (substrate having a thickness of 725 µm and the reduction amount of thickness in the range of 20-25 µm, col. 5, lines 42-44 and col. 6, lines 34-36).
As taught by Inoue, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Kasahara to obtain and achieve the method wherein the substrate has a thickness and the thinning removes less than 10% of the thickness of the substrate as claimed, because the thinning is performed to remove metallic contamination, scratches, and stains from the substrate surface, and excessive mechanical matching is known to introduce a damage layer and cause warp; thus selecting a limited removal amount represents a predictable process optimization (col. 4, lines 26-33).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Inoue in combination with Wyant in view of Kasahara due to the above reason.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Kasahara (US 2020/0309637) as applied to claim 1 above, and further in view of Poddar et al. (US 7354802; hereinafter ‘Poddar’).
Regarding claim 3, Wyant in view of Kasahara teaches the method of claim 1, further comprising removing a tape from the second side of the semiconductor substrate after directing the laser beam at the first side (Wyant: removing 312 from the device side of 302 after directing 206 at the non-device side of 302, FIG. 3B, [0018]).
Wyant in view of Kasahara does not teach the method further comprising removing the tape from the second side of the semiconductor substrate prior to electrically testing the plurality of dies.
Poddar teaches a method (col. 2, lines 13-17) comprising removing a tape from the second side of the semiconductor substrate prior to electrically testing the plurality of dies (removing the backgrind tape 202 from the active surface 110 of the wafer substrate 204 to expose the I/O pads 106, which are used for electrical connection, thereby allowing probing (testing) of the wafer, Figs. 2A-2C, col. 4, lines 29-31, col. 5, lines 22-23, col. 7, lines 21-29).
As taught by Poddar, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Kasahara to obtain and achieve the method further comprising removing the tape from the second side of the semiconductor substrate prior to electrically testing the plurality of dies as claimed, because removing the backgrind tape exposes the I/O pads for electrical connection to the internal circuits of the dies, thereby allowing electrical probing and testing of the dies (col. 4, lines 29-31 and col. 7, lines 24-29).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Poddar in combination with Wyant in view of Kasahara due to the above reason.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Kasahara (US 2020/0309637) as applied to claim 1 above, and further in view of Teh (MIT MBA Thesis, 2015).
Regarding claim 4, Wyant in view of Kasahara teaches the method of claim 1, further comprising: thinning the first side of the semiconductor substrate to reduce a thickness of the semiconductor substrate (Wyant: thinning of the non-device side of 102 using a back-grind machine to remove the thickness of 102, [0013]).
Wyant does not teach the method further comprising separate the plurality of dies along the scribe streets after electrically testing the plurality of dies
Kasahara teaches the method further comprising: separate the plurality of dies along the scribe streets after electrically testing the plurality of dies (semiconductor substrate 110 is cut into a plurality of substrates 11 along each of lines 5 after electrical inspection of the plurality of portions 1A, Figs. 16 and 17, [0061, 0089-0091, 0093-0096]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Kasahara to obtain and achieve the method further comprising: separate the plurality of dies along the scribe streets after electrically testing the plurality of dies as claimed, because it allows faulty devices to be identified in the wafer state before separation, thereby preventing faulty devices from proceeding to the final assembly stage [0105].
Wyant in view of Kasahara does not teach the method further comprising: thinning the first side of the semiconductor substrate to separate the plurality of dies along the scribe streets.
Teh teaches a method (SDBG, Figure 3-1, p. 63) further comprising: thinning the first side of the semiconductor substrate to separate the plurality of dies along the scribe streets (wafer backside of the substrate grinding for die separation along SD in the dicing street, Figure 3-1, p. 55, 63).
As taught by Teh, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Kasahara to obtain and achieve the method further comprising: thinning the first side of the semiconductor substrate to separate the plurality of dies along the scribe streets as claimed, because ultra-thin stacked die applications require a reduce final thickness, and the pre-formed SD layer provides a predictable fracture plane during subsequent separation (3.1 Preparation of NAND flash memory Si substrates).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Teh in combination with Wyant in view of Kasahara due to the above reason
Regarding claim 5, Wyant in view of Kasahara and Tech teaches the method of claim 4, Wyant in view of Kasahara does not teach the method wherein thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate includes backgrinding to remove at least 50% of the thickness of the semiconductor substrate.
Teh teaches the method wherein thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate includes backgrinding to remove at least 50% of the thickness of the semiconductor substrate (the wafer backside grinding reduces the substrate thickness from 775 µm to 25 µm, pp. 61 and 65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method wherein thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate includes backgrinding to remove at least 50% of the thickness of the semiconductor substrate as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 6, Wyant in view of Kasahara and Tech teaches the method of claim 4, Wyant in view of Kasahara does not teach the method wherein thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate includes backgrinding to remove a portion of the semiconductor substrate sufficient to remove cracks in the semiconductor substrate between the first side and the at least one modified region.
Teh teaches the method wherein thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate includes backgrinding to remove a portion of the semiconductor substrate between the first side and the at least one modified region (the wafer backside grinding thinning the substrate from a full thickness 775 µm to about 25 µm, thereby removing material between the backside and the SD, pp. 61 and 65).
Teh does not explicitly teach removing cracks in the substrate.
Teh, however, teaches the wafer backside grinding to a depth sufficient to extend to the modified region, and removal of cracks located between the first side and the modified region would necessarily result from such material removal (see, Table 5.1, demonstrating that the SD modified region depth is controllable and predictable based on process settings).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method wherein thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate includes backgrinding to remove a portion of the semiconductor substrate sufficient to remove cracks in the semiconductor substrate between the first side and the at least one modified region as claimed, because grinding depth is a routine process parameter, and selecting a depth sufficient to extend to or into the modified region would predictably eliminate cracks located between the first side and the modified region as a consequence of material removal.
Regarding claim 7, Wyant in view of Kasahara and Tech teaches the method of claim 4, Wyant in view of Kasahara does not teach the method further comprising: applying a first tape to the second side prior to thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate ; and applying a second tape to the first side after thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate.
Teh teaches the method further comprising:
applying a first tape to the second side prior to thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate (wafter circuit-side/frontside taping prior to thinning the backside grinding, Figure 3-1, p. 62 and p. 69); and
applying a second tape to the first side after thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate (applying DAF/DT lamination to backside of the thinned wafer, Figure 3-1, p. 66)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Teh to obtain and achieve the method further comprising: applying a first tape to the second side prior to thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate ; and applying a second tape to the first side after thinning the first side of the semiconductor substrate to reduce the thickness of the semiconductor substrate as claimed, because the first tape provides support and protection to the wafer during thinning, while the second tape provides support and stabilization to the thinned wafer for subsequent handling and processing.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Kasahara (US 2020/0309637) and Teh (MIT MBA Thesis, 2015) as applied to claim 7 above, and further in view of Poddar (US 7354802).
Regarding claim 8, Wyant in view of Kasahara and Tech teaches the method of claim 7, but does not teach the method further comprising: removing the first tape from the second side; and expanding the semiconductor substrate using the second tape.
Poddar teaches a method (col. 2, lines 13-17) further comprising:
removing the first tape from the second side (removing the backgrind tape 202 from the active surface 110 of the wafer substrate 204, Figs. 2B and 2C; col. 4, lines 56-58, col. 5, lines 8-10) and
expanding the semiconductor substrate using the second tape (the mount tape 205 including an expandable thermal release layer 207, wherein expansion of 207 raises and separates a selected singulated die of 204 relative to adjacent dice, Figs. 2D-2E, col. 5, line 43-col. 6, line 13).
As taught by Poddar, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Kasahara and Tech to obtain and achieve the method further comprising: removing the first tape from the second side; and expanding the semiconductor substrate using the second tape as claimed, because it facilitates separation of the singulated semiconductor dies from adjacent dies without unduly stressing the dies, thereby facilitating subsequent picking thereof (col 6, lines 64-67).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Poddar in combination with Wyant in view of Kasahara and Tech due to the above reason.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Wyant (US 2020/0051860) in view of Kasahara (US 2020/0309637) as applied to claim 23 above, and further in view of Sakamoto et al. (US 2007/0287267; hereinafter ‘Sakamoto’).
Regarding claim 24, Wyant in view of Kasahara teaches the method of claim 23, but does not teach the method wherein the another modified region has a second thickness different from the first thickness.
Sakamoto teaches a method [0001] wherein the another modified region has a second thickness different from the first thickness (the divided modified region at 121 µm, farther form the rear face 21 and closer to the device side, has a greater thickness using 20 µJ laser energy than the HC modified region at 71 µm, closer to the rear face 21, using 10 µJ laser energy, Fig. 38, [0164, 0171-0172, 0175]).
As taught by Sakamoto, one of ordinary skill in the art would utilize and modify the above teaching into Wyant in view of Kasahara to obtain and achieve the method wherein the another modified region has a second thickness different from the first thickness as claimed, because varying the thicknesses of the modified regions allows the fracture-generating characteristics of the modified regions to be controlled, thereby facilitating desired fracture propagation through the semiconductor substrate [0015].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Sakamoto in combination with Wyant in view of Kasahara due to the above reason.
Regarding claim 25, Wyant in view of Kasahara and Sakamoto teaches the method of claim 24, Wyant in view of Kasahara does not teach the method wherein the first thickness is greater than the second thickness.
Sakamoto teaches the method wherein the first thickness is greater than the second thickness (the divided modified region at 121 µm, farther form the rear face 21 and closer to the device side, has a greater thickness using 20 µJ laser energy than the HC modified region at 71 µm, closer to the rear face 21, using 10 µJ laser energy, Fig. 38, [0164, 0171-0172, 0175]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Sakamoto to obtain and achieve the method wherein the first thickness is greater than the second thickness as claimed, because varying the thicknesses of the modified regions allows the fracture-generating characteristics of the modified regions to be controlled, thereby facilitating desired fracture propagation through the semiconductor substrate [0015].
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Zhang et al. (US 2023/0017286) and Kamphuis et al. (US 2016/0276306) as a method of electrically testing semiconductor dies after laser processing of a semiconductor wafer.
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/7/26
Prosecution Insights